2023-07-10 19:05:10

by Andrew Lunn

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

On Mon, Jul 10, 2023 at 08:56:18PM +0300, Vesa Jääskeläinen wrote:
> Add support to specify either class A or class B (default) for line driver.
>
> Class A: full MLT-3 on both Tx+ and Tx–
> Class B: reduced MLT-3
>
> By default the PHY is in Class B mode.

Hi Vesa

Do you have a reference to 802.3 or some other document which
describes these. How does reduced differ from full? Is this really a
hardware property of the board?

Thanks
Andrew


2023-07-10 19:33:06

by Vesa Jääskeläinen

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

On 10.7.2023 21.38, Andrew Lunn wrote:
> On Mon, Jul 10, 2023 at 08:56:18PM +0300, Vesa Jääskeläinen wrote:
>> Add support to specify either class A or class B (default) for line driver.
>>
>> Class A: full MLT-3 on both Tx+ and Tx–
>> Class B: reduced MLT-3
>>
>> By default the PHY is in Class B mode.
> Hi Vesa
>
> Do you have a reference to 802.3 or some other document which
> describes these. How does reduced differ from full? Is this really a
> hardware property of the board?
>
> Thanks
> Andrew

Hi Andrew,

This is needed for configuration in link between DP83822 and Ethernet
Switch chip. In the connection there there is no Ethernet cable at all
but routes within the circuit boards but instead has capacitive coupling
on routes.

The other Ethernet port with the same phy is connected to normal
Ethernet cable and in there this configuration is not needed.

So the setting itself is related to specific circuit board design.

MLT-3 is related to encoding used in the signals -- I suppose wiki page
is good introduction reference:

https://en.wikipedia.org/wiki/MLT-3_encoding

I suppose this question in TI's forum gives indication what is the
effect of the setting:

https://e2e.ti.com/support/interface-group/interface/f/interface-forum/572998/dp83822hf-transformerless-operation

TI's datasheet is not too verbose about the effect:

https://www.ti.com/lit/ds/symlink/dp83822hf.pdf?ts=1688188848392&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83822HF

I cannot say I am expert on the Ethernet line encoding -- my
understanding is that full MLT-3 is "normal" signaling mode and reduced
MLT-3 mode is extension on the chip to perhaps reduce energy consumption
with real Ethernet cables or something like that but in chip-to-chip
link the reduced mode does not work and full MLT-3 is needed in order
for link to come up.

I hope this helps?

Thanks,
Vesa Jääskeläinen


2023-07-10 19:51:03

by Andrew Lunn

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

> Hi Andrew,
>
> This is needed for configuration in link between DP83822 and Ethernet Switch
> chip.

What switch chip is it?

Most boards just connect the MACs together and don't have PHYs in the
middle. There are some boards which do have PHYs, but they don't need
any special mode.

> In the connection there there is no Ethernet cable at all but routes
> within the circuit boards but instead has capacitive coupling on routes.

So you also left out the magnetics?

> So the setting itself is related to specific circuit board design.

Agreed. So it is then valid to put it into DT, if it is actually
needed.

> MLT-3 is related to encoding used in the signals -- I suppose wiki page is
> good introduction reference:
>
> https://en.wikipedia.org/wiki/MLT-3_encoding

MLT-3 is well defined. What i could not find is any reference to what
reduced MLT-3 is. If it is not part of any standard, why don't you
just hard code the PHY to always use MTL-3 which is defined as part of
802.3?

I get the feeling reduced MLT-3 is TI proprietary. As such, it should
default to MLT-3 as defined in 802.3 and there could then be an option
to enable this proprietary mode for anybody we wants to use it.

So before accepting any patches, we need a better understanding of
that reduced MLT-3 is and why you would want to use it.

Andrew


2023-07-11 08:14:42

by Vesa Jääskeläinen

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

Hi Andrew,

On 10.7.2023 22.38, Andrew Lunn wrote:
>> Hi Andrew,
>>
>> This is needed for configuration in link between DP83822 and Ethernet Switch
>> chip.
> What switch chip is it?

Microchip's KSZ9897.

> Most boards just connect the MACs together and don't have PHYs in the
> middle. There are some boards which do have PHYs, but they don't need
> any special mode.

In here there is PHY<->PHY line link. My understanding is that in this
particular case PHY link works better than *MII links.

>> In the connection there there is no Ethernet cable at all but routes
>> within the circuit boards but instead has capacitive coupling on routes.
> So you also left out the magnetics?

Yes for this chip-to-chip link.

>> So the setting itself is related to specific circuit board design.
> Agreed. So it is then valid to put it into DT, if it is actually
> needed.
>
>> MLT-3 is related to encoding used in the signals -- I suppose wiki page is
>> good introduction reference:
>>
>> https://en.wikipedia.org/wiki/MLT-3_encoding
> MLT-3 is well defined. What i could not find is any reference to what
> reduced MLT-3 is. If it is not part of any standard, why don't you
> just hard code the PHY to always use MTL-3 which is defined as part of
> 802.3?
>
> I get the feeling reduced MLT-3 is TI proprietary. As such, it should
> default to MLT-3 as defined in 802.3 and there could then be an option
> to enable this proprietary mode for anybody we wants to use it.
>
> So before accepting any patches, we need a better understanding of
> that reduced MLT-3 is and why you would want to use it.

OK.

My understanding is that as we have PHY<->PHY link it needs to handle
itself in standard way. Thus the MLT-3 full mode is required for
communicating with Ethernet switch.

It seems that Texas Instruments has figured out additional power saving
mechanism by carefully selecting used magnetics (they have guidelines
for that and list of supported ones). Now the thinking might have
continued that let's make the power saving mode the default for all.

With carefully selected magnetics one most likely gets correct looking
signal when measured from the cable and thus the other party then gets
properly looking signal. I suppose this is the majority of the users.

Now what can be the default operation.

My thinking was that let's keep current functionality as is so that
no-one would get surprises with it -- and it is default setting for the
chip too.

Then again there has been also others like one in TI's e2e forum that
already had problems by not having the MLT-3 full mode enabled so
default could even be MLT-3 full and then have extra device tree setting
to enable this power saving feature. But then again one does not benefit
from power saving features developed by chip manufactures if we by
default try to cancel the effect. And this cancelling most likely would
happen afterwards of the original driver implementation as these are in
special registers.

I tried to look up what does this class A and class B mean but I am
unable to find the reasoning for that.

Do we have people from Texas Instruments that could share more insights?

In a way this could even be:

  ti,force-standard-mlt-3-signaling;

Then there is no ambiguity what it does.

Thanks,
Vesa Jääskeläinen

2023-07-11 16:06:09

by Andrew Lunn

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

On Tue, Jul 11, 2023 at 10:51:22AM +0300, Vesa J??skel?inen wrote:
> Hi Andrew,
>
> On 10.7.2023 22.38, Andrew Lunn wrote:
> > > Hi Andrew,
> > >
> > > This is needed for configuration in link between DP83822 and Ethernet Switch
> > > chip.
> > What switch chip is it?
>
> Microchip's KSZ9897.

O.K, so nothing special or oddball.

> > Most boards just connect the MACs together and don't have PHYs in the
> > middle. There are some boards which do have PHYs, but they don't need
> > any special mode.
>
> In here there is PHY<->PHY line link. My understanding is that in this
> particular case PHY link works better than *MII links.

I've seen PHY<->PHY done when the switch was on a daughter board, and
there was worries about getting RGMII over the connector etc.

> > So before accepting any patches, we need a better understanding of
> > that reduced MLT-3 is and why you would want to use it.
>
> OK.
>
> My understanding is that as we have PHY<->PHY link it needs to handle itself
> in standard way. Thus the MLT-3 full mode is required for communicating with
> Ethernet switch.
>
> It seems that Texas Instruments has figured out additional power saving
> mechanism by carefully selecting used magnetics (they have guidelines for
> that and list of supported ones). Now the thinking might have continued that
> let's make the power saving mode the default for all.

Do there guidelines for magnetic says anything about what to do when
using unsupported ones. Like turn reduced MLT-3 off?

> With carefully selected magnetics one most likely gets correct looking
> signal when measured from the cable and thus the other party then gets

> I tried to look up what does this class A and class B mean but I am unable
> to find the reasoning for that.

If you look at the oscilloscope screenshots in the support forum, it
looks like in reduced MLT-3 mode, The TX- and TX+ pins only have two
states, not three. It relies on the magnetics to combine the two
signals to produce a three state signal, and handle the bias in each
signal.

When in MLT-3 mode, i expect the TX- and TX+ pins do real MLT-3.

With real MLT-3, you can then do capacitor coupling to other devices
which conform to 802.3.

> Do we have people from Texas Instruments that could share more insights?

Maybe, but don't hold your breath. Since Dan Murphy left TI, TI does
not really support its own PHYs in mainline.

> In a way this could even be:
>
> ? ti,force-standard-mlt-3-signaling;

Maybe. Or ti,disable-proprietary-line-coding

Lets give TI a couple of days to comment.

Andrew

2023-07-11 16:18:31

by Vesa Jääskeläinen

[permalink] [raw]
Subject: Re: [PATCH 0/2] net: phy: dp83822: Add support for line class driver configuration

On 11.7.2023 18.35, Andrew Lunn wrote:
>
>>> So before accepting any patches, we need a better understanding of
>>> that reduced MLT-3 is and why you would want to use it.
>> OK.
>>
>> My understanding is that as we have PHY<->PHY link it needs to handle itself
>> in standard way. Thus the MLT-3 full mode is required for communicating with
>> Ethernet switch.
>>
>> It seems that Texas Instruments has figured out additional power saving
>> mechanism by carefully selecting used magnetics (they have guidelines for
>> that and list of supported ones). Now the thinking might have continued that
>> let's make the power saving mode the default for all.
> Do there guidelines for magnetic says anything about what to do when
> using unsupported ones. Like turn reduced MLT-3 off?
>
>> With carefully selected magnetics one most likely gets correct looking
>> signal when measured from the cable and thus the other party then gets
>> I tried to look up what does this class A and class B mean but I am unable
>> to find the reasoning for that.
> If you look at the oscilloscope screenshots in the support forum, it
> looks like in reduced MLT-3 mode, The TX- and TX+ pins only have two
> states, not three. It relies on the magnetics to combine the two
> signals to produce a three state signal, and handle the bias in each
> signal.
>
> When in MLT-3 mode, i expect the TX- and TX+ pins do real MLT-3.
>
> With real MLT-3, you can then do capacitor coupling to other devices
> which conform to 802.3.

From the datasheet
(https://www.ti.com/lit/ds/symlink/dp83822i.pdf?ts=1689018777543):

"8.4.3.1.4 Binary to MLT-3 Converter
The Binary to MLT-3 conversion is accomplished by converting the serial
binary data stream output from the
NRZI encoder into two binary data streams with alternately phased logic
one events. These two binary streams
are then fed to the twisted pair output driver which converts the
voltage to current and alternately drives either
side of the transmit transformer primary winding, resulting in a minimal
current MLT-3 signal.

The 100BASE-TX MLT-3 signal sourced by the PMD Output Pair common driver
is slew rate controlled. This
should be considered when selecting AC coupling magnetics to ensure
TP-PMD Standard compliant transition
times (3 ns < Trise/fall < 5 ns).

The 100BASE-TX transmit TP-PMD function within the DP83822 is capable of
sourcing only MLT-3 encoded
data. Binary output from the PMD Output Pair is not possible in 100 Mbps
mode. Fully encoded MLT-3 on both
Tx+ and Tx- and can be configured by configuring Register 0x0404h (for
example, in transformer-less designs)."

and then about transformer:

"11.1.3.1 Transformer Recommendations
The following magnetics have been tested with the DP83822 using the
DP83822EVM.
Table 11-1. Recommended Transformers

[table here]

Table 11-2. Transformer Electrical Specifications

[table here]

"

They have also application note
(https://www.ti.com/lit/an/snla079d/snla079d.pdf?ts=1689063082391&ref_url=https%253A%252F%252Fwww.ti.com%252Fproduct%252FDP83822I%253FkeyMatch%253D%2526tisearch%253Dsearch-everything%2526usecase%253Dpartmatches):

"2 MDI (TP/CAT-V) Connections"

and

"10.2 Magnetics"

Which has more or less same info as the datasheet.

To me that just says follow these guidelines and please select one form
already tested lists. And if you must then look for similar products and
make sure that these limits are matched.

Perhaps you are able to decode that better :). I trust our electrical
engineers to do the right job ;)

>
>> In a way this could even be:
>>
>>   ti,force-standard-mlt-3-signaling;
> Maybe. Or ti,disable-proprietary-line-coding
>
> Lets give TI a couple of days to comment.
>
> Andrew

Sure.

I am OK with any of the three variants proposed so far.

Perhaps leaning towards more to new ones above.

Thanks,
Vesa Jääskeläinen