Subject: [PATCH 0/2] Support MSM8976 SAW2 for both clusters

This series adds support for the L2 cache SAW2 on MSM8976,
required to configure sleep modes and managing part of DVFS.

AngeloGioacchino Del Regno (2):
dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2
soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

.../bindings/soc/qcom/qcom,spm.yaml | 2 ++
drivers/soc/qcom/spm.c | 33 +++++++++++++++++++
2 files changed, 35 insertions(+)

--
2.37.2



Subject: [PATCH 1/2] dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2

Add SPM AVS Wrapper 2 compatibles for MSM8976's L2 cache.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml | 2 ++
1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
index f433e6e0a19f..80434d7111d9 100644
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
@@ -24,6 +24,8 @@ properties:
- qcom,msm8998-silver-saw2-v4.1-l2
- qcom,msm8909-saw2-v3.0-cpu
- qcom,msm8916-saw2-v3.0-cpu
+ - qcom,msm8976-gold-saw2-v2.3-l2
+ - qcom,msm8976-silver-saw2-v2.3-l2
- qcom,msm8226-saw2-v2.1-cpu
- qcom,msm8974-saw2-v2.1-cpu
- qcom,apq8084-saw2-v2.1-cpu
--
2.37.2


Subject: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

From: AngeloGioacchino Del Regno <[email protected]>

Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
and APQ variants and while at it also add the configuration for the
MSM8976's little (a53) and big (a72) clusters cache power management.

Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
[Marijn: reorder struct definitions to follow high-to-low order]
Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
---
drivers/soc/qcom/spm.c | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)

diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
index 484b42b7454e..bfcd321d7837 100644
--- a/drivers/soc/qcom/spm.c
+++ b/drivers/soc/qcom/spm.c
@@ -98,6 +98,35 @@ static const struct spm_reg_data spm_reg_8916_cpu = {
.start_index[PM_SLEEP_MODE_SPC] = 5,
};

+static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
+ [SPM_REG_CFG] = 0x08,
+ [SPM_REG_SPM_CTL] = 0x30,
+ [SPM_REG_DLY] = 0x34,
+ [SPM_REG_PMIC_DATA_0] = 0x40,
+ [SPM_REG_PMIC_DATA_1] = 0x44,
+};
+
+/* SPM register data for 8976 */
+static const struct spm_reg_data spm_reg_8976_gold_l2 = {
+ .reg_offset = spm_reg_offset_v2_3,
+ .spm_cfg = 0x14,
+ .spm_dly = 0x3c11840a,
+ .pmic_data[0] = 0x03030080,
+ .pmic_data[1] = 0x00030000,
+ .start_index[PM_SLEEP_MODE_STBY] = 0,
+ .start_index[PM_SLEEP_MODE_SPC] = 3,
+};
+
+static const struct spm_reg_data spm_reg_8976_silver_l2 = {
+ .reg_offset = spm_reg_offset_v2_3,
+ .spm_cfg = 0x14,
+ .spm_dly = 0x3c102800,
+ .pmic_data[0] = 0x03030080,
+ .pmic_data[1] = 0x00030000,
+ .start_index[PM_SLEEP_MODE_STBY] = 0,
+ .start_index[PM_SLEEP_MODE_SPC] = 2,
+};
+
static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
[SPM_REG_CFG] = 0x08,
[SPM_REG_SPM_CTL] = 0x30,
@@ -213,6 +242,10 @@ static const struct of_device_id spm_match_table[] = {
.data = &spm_reg_8916_cpu },
{ .compatible = "qcom,msm8974-saw2-v2.1-cpu",
.data = &spm_reg_8974_8084_cpu },
+ { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
+ .data = &spm_reg_8976_gold_l2 },
+ { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
+ .data = &spm_reg_8976_silver_l2 },
{ .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
.data = &spm_reg_8998_gold_l2 },
{ .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
--
2.37.2


2022-11-04 14:31:26

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 1/2] dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2

On 04/11/2022 09:34, AngeloGioacchino Del Regno wrote:
> Add SPM AVS Wrapper 2 compatibles for MSM8976's L2 cache.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
> index f433e6e0a19f..80434d7111d9 100644
> --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
> +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml
> @@ -24,6 +24,8 @@ properties:
> - qcom,msm8998-silver-saw2-v4.1-l2
> - qcom,msm8909-saw2-v3.0-cpu
> - qcom,msm8916-saw2-v3.0-cpu
> + - qcom,msm8976-gold-saw2-v2.3-l2
> + - qcom,msm8976-silver-saw2-v2.3-l2


I don't know what is the ordering in the file, so:

Acked-by: Krzysztof Kozlowski <[email protected]>

Best regards,
Krzysztof


2022-11-04 14:36:13

by Krzysztof Kozlowski

[permalink] [raw]
Subject: Re: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

On 04/11/2022 10:25, Konrad Dybcio wrote:
>
> On 04/11/2022 14:34, AngeloGioacchino Del Regno wrote:
>> From: AngeloGioacchino Del Regno <[email protected]>
>>
>> Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
>> and APQ variants and while at it also add the configuration for the
>> MSM8976's little (a53) and big (a72) clusters cache power management.
>>
>> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
>> [Marijn: reorder struct definitions to follow high-to-low order]
>
> Weird to have a name without an email address in any of the tags, but I
>
> suppose it's not much of an issue?
>

This looks like missing Signed-off-bu from Marijn.

Best regards,
Krzysztof


2022-11-04 15:20:18

by Konrad Dybcio

[permalink] [raw]
Subject: Re: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM


On 04/11/2022 14:34, AngeloGioacchino Del Regno wrote:
> From: AngeloGioacchino Del Regno <[email protected]>
>
> Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
> and APQ variants and while at it also add the configuration for the
> MSM8976's little (a53) and big (a72) clusters cache power management.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> [Marijn: reorder struct definitions to follow high-to-low order]

Weird to have a name without an email address in any of the tags, but I

suppose it's not much of an issue?


> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---

For the code:

Reviewed-by: Konrad Dybcio <[email protected]>


Konrad

> drivers/soc/qcom/spm.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> index 484b42b7454e..bfcd321d7837 100644
> --- a/drivers/soc/qcom/spm.c
> +++ b/drivers/soc/qcom/spm.c
> @@ -98,6 +98,35 @@ static const struct spm_reg_data spm_reg_8916_cpu = {
> .start_index[PM_SLEEP_MODE_SPC] = 5,
> };
>
> +static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
> + [SPM_REG_CFG] = 0x08,
> + [SPM_REG_SPM_CTL] = 0x30,
> + [SPM_REG_DLY] = 0x34,
> + [SPM_REG_PMIC_DATA_0] = 0x40,
> + [SPM_REG_PMIC_DATA_1] = 0x44,
> +};
> +
> +/* SPM register data for 8976 */
> +static const struct spm_reg_data spm_reg_8976_gold_l2 = {
> + .reg_offset = spm_reg_offset_v2_3,
> + .spm_cfg = 0x14,
> + .spm_dly = 0x3c11840a,
> + .pmic_data[0] = 0x03030080,
> + .pmic_data[1] = 0x00030000,
> + .start_index[PM_SLEEP_MODE_STBY] = 0,
> + .start_index[PM_SLEEP_MODE_SPC] = 3,
> +};
> +
> +static const struct spm_reg_data spm_reg_8976_silver_l2 = {
> + .reg_offset = spm_reg_offset_v2_3,
> + .spm_cfg = 0x14,
> + .spm_dly = 0x3c102800,
> + .pmic_data[0] = 0x03030080,
> + .pmic_data[1] = 0x00030000,
> + .start_index[PM_SLEEP_MODE_STBY] = 0,
> + .start_index[PM_SLEEP_MODE_SPC] = 2,
> +};
> +
> static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
> [SPM_REG_CFG] = 0x08,
> [SPM_REG_SPM_CTL] = 0x30,
> @@ -213,6 +242,10 @@ static const struct of_device_id spm_match_table[] = {
> .data = &spm_reg_8916_cpu },
> { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
> .data = &spm_reg_8974_8084_cpu },
> + { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
> + .data = &spm_reg_8976_gold_l2 },
> + { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
> + .data = &spm_reg_8976_silver_l2 },
> { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
> .data = &spm_reg_8998_gold_l2 },
> { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",

2022-11-04 15:24:37

by Marijn Suijten

[permalink] [raw]
Subject: Re: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

On 2022-11-04 14:34:52, AngeloGioacchino Del Regno wrote:
> From: AngeloGioacchino Del Regno <[email protected]>
>
> Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
> and APQ variants and while at it also add the configuration for the
> MSM8976's little (a53) and big (a72) clusters cache power management.
>
> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> [Marijn: reorder struct definitions to follow high-to-low order]

Signed-off-by: Marijn Suijten <[email protected]>

> Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> ---
> drivers/soc/qcom/spm.c | 33 +++++++++++++++++++++++++++++++++
> 1 file changed, 33 insertions(+)
>
> diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> index 484b42b7454e..bfcd321d7837 100644
> --- a/drivers/soc/qcom/spm.c
> +++ b/drivers/soc/qcom/spm.c
> @@ -98,6 +98,35 @@ static const struct spm_reg_data spm_reg_8916_cpu = {
> .start_index[PM_SLEEP_MODE_SPC] = 5,
> };
>
> +static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
> + [SPM_REG_CFG] = 0x08,
> + [SPM_REG_SPM_CTL] = 0x30,
> + [SPM_REG_DLY] = 0x34,
> + [SPM_REG_PMIC_DATA_0] = 0x40,
> + [SPM_REG_PMIC_DATA_1] = 0x44,
> +};
> +
> +/* SPM register data for 8976 */
> +static const struct spm_reg_data spm_reg_8976_gold_l2 = {
> + .reg_offset = spm_reg_offset_v2_3,
> + .spm_cfg = 0x14,
> + .spm_dly = 0x3c11840a,
> + .pmic_data[0] = 0x03030080,
> + .pmic_data[1] = 0x00030000,
> + .start_index[PM_SLEEP_MODE_STBY] = 0,
> + .start_index[PM_SLEEP_MODE_SPC] = 3,
> +};
> +
> +static const struct spm_reg_data spm_reg_8976_silver_l2 = {
> + .reg_offset = spm_reg_offset_v2_3,
> + .spm_cfg = 0x14,
> + .spm_dly = 0x3c102800,
> + .pmic_data[0] = 0x03030080,
> + .pmic_data[1] = 0x00030000,
> + .start_index[PM_SLEEP_MODE_STBY] = 0,
> + .start_index[PM_SLEEP_MODE_SPC] = 2,
> +};
> +
> static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
> [SPM_REG_CFG] = 0x08,
> [SPM_REG_SPM_CTL] = 0x30,
> @@ -213,6 +242,10 @@ static const struct of_device_id spm_match_table[] = {
> .data = &spm_reg_8916_cpu },
> { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
> .data = &spm_reg_8974_8084_cpu },
> + { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
> + .data = &spm_reg_8976_gold_l2 },
> + { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
> + .data = &spm_reg_8976_silver_l2 },
> { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
> .data = &spm_reg_8998_gold_l2 },
> { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
> --
> 2.37.2
>

2022-11-04 22:05:11

by Dmitry Baryshkov

[permalink] [raw]
Subject: Re: [PATCH 2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM

On Fri, 4 Nov 2022 at 17:34, Marijn Suijten
<[email protected]> wrote:
>
> On 2022-11-04 14:34:52, AngeloGioacchino Del Regno wrote:
> > From: AngeloGioacchino Del Regno <[email protected]>
> >
> > Implement the support for SAW v2.3, used in at least MSM8976, MSM8956
> > and APQ variants and while at it also add the configuration for the
> > MSM8976's little (a53) and big (a72) clusters cache power management.
> >
> > Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> > [Marijn: reorder struct definitions to follow high-to-low order]
>
> Signed-off-by: Marijn Suijten <[email protected]>

With this sign-off in place,

Reviewed-by: Dmitry Baryshkov <[email protected]>

>
> > Signed-off-by: AngeloGioacchino Del Regno <[email protected]>
> > ---
> > drivers/soc/qcom/spm.c | 33 +++++++++++++++++++++++++++++++++
> > 1 file changed, 33 insertions(+)
> >
> > diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c
> > index 484b42b7454e..bfcd321d7837 100644
> > --- a/drivers/soc/qcom/spm.c
> > +++ b/drivers/soc/qcom/spm.c
> > @@ -98,6 +98,35 @@ static const struct spm_reg_data spm_reg_8916_cpu = {
> > .start_index[PM_SLEEP_MODE_SPC] = 5,
> > };
> >
> > +static const u16 spm_reg_offset_v2_3[SPM_REG_NR] = {
> > + [SPM_REG_CFG] = 0x08,
> > + [SPM_REG_SPM_CTL] = 0x30,
> > + [SPM_REG_DLY] = 0x34,
> > + [SPM_REG_PMIC_DATA_0] = 0x40,
> > + [SPM_REG_PMIC_DATA_1] = 0x44,
> > +};
> > +
> > +/* SPM register data for 8976 */
> > +static const struct spm_reg_data spm_reg_8976_gold_l2 = {
> > + .reg_offset = spm_reg_offset_v2_3,
> > + .spm_cfg = 0x14,
> > + .spm_dly = 0x3c11840a,
> > + .pmic_data[0] = 0x03030080,
> > + .pmic_data[1] = 0x00030000,
> > + .start_index[PM_SLEEP_MODE_STBY] = 0,
> > + .start_index[PM_SLEEP_MODE_SPC] = 3,
> > +};
> > +
> > +static const struct spm_reg_data spm_reg_8976_silver_l2 = {
> > + .reg_offset = spm_reg_offset_v2_3,
> > + .spm_cfg = 0x14,
> > + .spm_dly = 0x3c102800,
> > + .pmic_data[0] = 0x03030080,
> > + .pmic_data[1] = 0x00030000,
> > + .start_index[PM_SLEEP_MODE_STBY] = 0,
> > + .start_index[PM_SLEEP_MODE_SPC] = 2,
> > +};
> > +
> > static const u16 spm_reg_offset_v2_1[SPM_REG_NR] = {
> > [SPM_REG_CFG] = 0x08,
> > [SPM_REG_SPM_CTL] = 0x30,
> > @@ -213,6 +242,10 @@ static const struct of_device_id spm_match_table[] = {
> > .data = &spm_reg_8916_cpu },
> > { .compatible = "qcom,msm8974-saw2-v2.1-cpu",
> > .data = &spm_reg_8974_8084_cpu },
> > + { .compatible = "qcom,msm8976-gold-saw2-v2.3-l2",
> > + .data = &spm_reg_8976_gold_l2 },
> > + { .compatible = "qcom,msm8976-silver-saw2-v2.3-l2",
> > + .data = &spm_reg_8976_silver_l2 },
> > { .compatible = "qcom,msm8998-gold-saw2-v4.1-l2",
> > .data = &spm_reg_8998_gold_l2 },
> > { .compatible = "qcom,msm8998-silver-saw2-v4.1-l2",
> > --
> > 2.37.2
> >



--
With best wishes
Dmitry

2022-11-07 03:26:06

by Bjorn Andersson

[permalink] [raw]
Subject: Re: [PATCH 0/2] Support MSM8976 SAW2 for both clusters

On Fri, 4 Nov 2022 14:34:50 +0100, AngeloGioacchino Del Regno wrote:
> This series adds support for the L2 cache SAW2 on MSM8976,
> required to configure sleep modes and managing part of DVFS.
>
> AngeloGioacchino Del Regno (2):
> dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2
> soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM
>
> [...]

Applied, thanks!

[1/2] dt-bindings: soc: qcom: spm: Add compatibles for MSM8976 L2
commit: 7a21fddb355a01c5655d43e4723c6fe99f2a4146
[2/2] soc: qcom: spm: Implement support for SAWv2.3, MSM8976 L2 PM
commit: 33268bb9fdb64f57c08d400709bae7b9cda3120a

Best regards,
--
Bjorn Andersson <[email protected]>