On Fri, 25 Aug 2023 19:43:34 +0100,
Dmitry Baryshkov <[email protected]> wrote:
>
> On Wed, 23 Aug 2023 at 12:49, Neil Armstrong <[email protected]> wrote:
> >
> > Starting from HW version 3.2 the IRQ_ENABLE bit has moved to the
> > IRQ_i_CFG register and requires a change of the driver to avoid
> > writing into an undefined register address.
> >
> > Get the HW version from registers and set the IRQ_ENABLE bit to the
> > correct register depending on the HW version.
> >
> > Reviewed-by: Maulik Shah <[email protected]>
> > Signed-off-by: Neil Armstrong <[email protected]>
> > ---
> > Changes in v3:
> > - Simplify qcom_pdc_gic_set_type()
> > - Used __assign_bit in pdc_setup_pin_mapping()
> > - remove BIT() from IRQ_i_CFG_IRQ_ENABLE to be used with __assign_bit()
> > - Add Reviewed-by tag
> > - Link to v2: https://lore.kernel.org/r/20230822-topic-sm8x50-upstream-pdc-ver-v2-1-3035b8d388f7@linaro.org
> >
> > Changes in v2:
> > - Changed IRQ_ENABLE handling based on Maulik's comments
> > - Link to v1: https://lore.kernel.org/r/20230821-topic-sm8x50-upstream-pdc-ver-v1-1-6d7f4dd95719@linaro.org
> > ---
> > drivers/irqchip/qcom-pdc.c | 61 ++++++++++++++++++++++++++++++++++++----------
> > 1 file changed, 48 insertions(+), 13 deletions(-)
>
> This patch in linux-next broke sm8150. On that platform the PDC region
> has size 0x400, so reading the version crashes the kernel.
> I'll send a patch fixing device tree, but we'd still need to handle
> this in a driver too.
Thanks for reporting the breakage.
Given that this has direct platform implications, I've dropped the
patch from my tree until people figure out whether the proposed fix is
the correct one and take the time it takes to test it.
Please work with Neil to post an updated series that contains the
fixed support for v3.2 and the DT churn.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.