Hi All,
Just booting up v5.5.11 on a Freescale T2080RDB and I'm seeing the
following mesage.
kern.warning linuxbox kernel: Argh, can't find dcache properties !
kern.warning linuxbox kernel: Argh, can't find icache properties !
This was changed from DBG() to pr_warn() in commit 3b9176e9a874
("powerpc/setup_64: fix -Wempty-body warnings") but the message seems
to be much older than that. So it's probably been an issue on the T2080
(and other QorIQ SoCs) for a while.
Looking at the code the t208x doesn't specifiy any of the d-cache-
size/i-cache-size properties. Should I add them to silence the warning
or switch it to pr_debug()/pr_info()?
Thanks,
Chris
Chris Packham <[email protected]> writes:
> Hi All,
>
> Just booting up v5.5.11 on a Freescale T2080RDB and I'm seeing the
> following mesage.
>
> kern.warning linuxbox kernel: Argh, can't find dcache properties !
> kern.warning linuxbox kernel: Argh, can't find icache properties !
>
> This was changed from DBG() to pr_warn() in commit 3b9176e9a874
> ("powerpc/setup_64: fix -Wempty-body warnings") but the message seems
> to be much older than that. So it's probably been an issue on the T2080
> (and other QorIQ SoCs) for a while.
That's an e6500 I think? So 64-bit Book3E.
You'll be getting the default values, which is 64 bytes so I guess that
works in practice.
> Looking at the code the t208x doesn't specifiy any of the d-cache-
> size/i-cache-size properties. Should I add them to silence the warning
> or switch it to pr_debug()/pr_info()?
Yeah ideally you'd add them to the device tree(s) for those boards.
cheers
On Tue, 2020-03-24 at 15:47 +1100, Michael Ellerman wrote:
> Chris Packham <[email protected]> writes:
> > Hi All,
> >
> > Just booting up v5.5.11 on a Freescale T2080RDB and I'm seeing the
> > following mesage.
> >
> > kern.warning linuxbox kernel: Argh, can't find dcache properties !
> > kern.warning linuxbox kernel: Argh, can't find icache properties !
> >
> > This was changed from DBG() to pr_warn() in commit 3b9176e9a874
> > ("powerpc/setup_64: fix -Wempty-body warnings") but the message
> > seems
> > to be much older than that. So it's probably been an issue on the
> > T2080
> > (and other QorIQ SoCs) for a while.
>
> That's an e6500 I think? So 64-bit Book3E.
>
Yes that's correct.
> You'll be getting the default values, which is 64 bytes so I guess
> that
> works in practice.
>
> > Looking at the code the t208x doesn't specifiy any of the d-cache-
> > size/i-cache-size properties. Should I add them to silence the
> > warning
> > or switch it to pr_debug()/pr_info()?
>
> Yeah ideally you'd add them to the device tree(s) for those boards.
>
I think the info I need is in the block diagram[0]. I'll whip up
a patch.
--
[1] - https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/qoriq-communication-processors/t-series/qoriq-t2080-and-t2081-multicore-communications-processors:T2080
> On Mar 24, 2020, at 4:06 PM, Chris Packham <[email protected]> wrote:
>
> On Tue, 2020-03-24 at 15:47 +1100, Michael Ellerman wrote:
>> Chris Packham <[email protected]> writes:
>>> Hi All,
>>>
>>> Just booting up v5.5.11 on a Freescale T2080RDB and I'm seeing the
>>> following mesage.
>>>
>>> kern.warning linuxbox kernel: Argh, can't find dcache properties !
>>> kern.warning linuxbox kernel: Argh, can't find icache properties !
>>>
>>> This was changed from DBG() to pr_warn() in commit 3b9176e9a874
>>> ("powerpc/setup_64: fix -Wempty-body warnings") but the message
>>> seems
>>> to be much older than that. So it's probably been an issue on the
>>> T2080
>>> (and other QorIQ SoCs) for a while.
>>
>> That's an e6500 I think? So 64-bit Book3E.
>>
>
> Yes that's correct.
>
>> You'll be getting the default values, which is 64 bytes so I guess
>> that
>> works in practice.
>>
>>> Looking at the code the t208x doesn't specifiy any of the d-cache-
>>> size/i-cache-size properties. Should I add them to silence the
>>> warning
>>> or switch it to pr_debug()/pr_info()?
>>
>> Yeah ideally you'd add them to the device tree(s) for those boards.
>>
>
> I think the info I need is in the block diagram[0]. I'll whip up
> a patch.
>
> --
> [1] - https://www.nxp.com/products/processors-and-microcontrollers/power-architecture/qoriq-communication-processors/t-series/qoriq-t2080-and-t2081-multicore-communications-processors:T2080
BTW, POWER9 PowerNV would have the same thing.
[ 0.000000][ T0] Setting debug_guardpage_minorder to 1
[ 0.000000][ T0] Reserving 512MB of memory at 128MB for crashkernel (System RAM: 262144MB)
[ 0.000000][ T0] radix-mmu: Page sizes from device-tree:
[ 0.000000][ T0] radix-mmu: Page size shift = 12 AP=0x0
[ 0.000000][ T0] radix-mmu: Page size shift = 16 AP=0x5
[ 0.000000][ T0] radix-mmu: Page size shift = 21 AP=0x1
[ 0.000000][ T0] radix-mmu: Page size shift = 30 AP=0x2
[ 0.000000][ T0] radix-mmu: Activating Kernel Userspace Execution Prevention
[ 0.000000][ T0] radix-mmu: Activating Kernel Userspace Access Prevention
[ 0.000000][ T0] radix-mmu: Mapped 0x0000000000000000-0x0000000001600000 with 2.00 MiB pages (exec)
[ 0.000000][ T0] radix-mmu: Mapped 0x0000000001600000-0x0000000040000000 with 2.00 MiB pages
[ 0.000000][ T0] radix-mmu: Mapped 0x0000000040000000-0x0000002000000000 with 1.00 GiB pages
[ 0.000000][ T0] radix-mmu: Mapped 0x0000200000000000-0x0000202000000000 with 1.00 GiB pages
[ 0.000000][ T0] radix-mmu: Initializing Radix MMU
[ 0.000000][ T0] Linux version 5.6.0-rc7-next-20200324+ (root@ibm-p9wr) (gcc version 8.3.1 20191121 (Red Hat 8.3.1-5) (GCC)) #2 SMP Tue Mar 24 15:52:36 EDT 2020
[ 0.000000][ T0] Argh, can't find dcache properties !
[ 0.000000][ T0] Argh, can't find icache properties !
[ 0.000000][ T0] Found initrd at 0xc000000007850000:0xc00000000ad26142
[ 0.000000][ T0] OPAL: Found memory mapped LPC bus on chip 0
[ 0.000000][ T0] Using PowerNV machine description
[ 0.000000][ T0] printk: bootconsole [udbg0] enabled
[ 0.000000][ T0] CPU maps initialized for 4 threads per core
[ 0.000000][ T0] -----------------------------------------------------
[ 0.000000][ T0] phys_mem_size = 0x4000000000
[ 0.000000][ T0] dcache_bsize = 0x80
[ 0.000000][ T0] icache_bsize = 0x80
[ 0.000000][ T0] cpu_features = 0x0001f86f8f5fb1a7
[ 0.000000][ T0] possible = 0x0003fbffcf5fb1a7
[ 0.000000][ T0] always = 0x0000006f8b5c91a1
[ 0.000000][ T0] cpu_user_features = 0xdc0065c2 0xaee00000
[ 0.000000][ T0] mmu_features = 0xbc006041
[ 0.000000][ T0] firmware_features = 0x0000000010000000
[ 0.000000][ T0] vmalloc start = 0xc008000000000000
[ 0.000000][ T0] IO start = 0xc00a000000000000
[ 0.000000][ T0] vmemmap start = 0xc00c000000000000
[ 0.000000][ T0] -----------------------------------------------------
Qian Cai <[email protected]> writes:
>> On Mar 24, 2020, at 4:06 PM, Chris Packham <[email protected]> wrote:
>> On Tue, 2020-03-24 at 15:47 +1100, Michael Ellerman wrote:
>>> Chris Packham <[email protected]> writes:
>>>> Hi All,
>>>>
>>>> Just booting up v5.5.11 on a Freescale T2080RDB and I'm seeing the
>>>> following mesage.
>>>>
>>>> kern.warning linuxbox kernel: Argh, can't find dcache properties !
>>>> kern.warning linuxbox kernel: Argh, can't find icache properties !
...
>
> BTW, POWER9 PowerNV would have the same thing.
Ugh, you're right.
Because we're missing the cache-line-size properties, even though they
are optional when the block & line size are the same.
# find /proc/device-tree/cpus/PowerPC\,POWER9@0/ -name '*cache*'
/proc/device-tree/cpus/PowerPC,POWER9@0/l2-cache
/proc/device-tree/cpus/PowerPC,POWER9@0/d-cache-block-size
/proc/device-tree/cpus/PowerPC,POWER9@0/d-cache-size
/proc/device-tree/cpus/PowerPC,POWER9@0/i-cache-size
/proc/device-tree/cpus/PowerPC,POWER9@0/d-cache-sets
/proc/device-tree/cpus/PowerPC,POWER9@0/i-cache-block-size
/proc/device-tree/cpus/PowerPC,POWER9@0/i-cache-sets
skiboot even explicitly omits them:
if (cache->icache_line_size != cache->icache_block_size)
dt_add_property_cells(cpu, "i-cache-line-size",
be32_to_cpu(cache->icache_line_size));
if (cache->l1_dcache_line_size != cache->dcache_block_size)
dt_add_property_cells(cpu, "d-cache-line-size",
be32_to_cpu(cache->l1_dcache_line_size));
Looks like it was broken ~3 years ago, in:
bd067f83b084 ("powerpc/64: Fix naming of cache block vs. cache line")
Previously we did:
lsizep = of_get_property(np, "d-cache-block-size",
NULL);
/* fallback if block size missing */
if (lsizep == NULL)
lsizep = of_get_property(np,
"d-cache-line-size",
NULL);
if (lsizep != NULL)
lsize = be32_to_cpu(*lsizep);
if (sizep == NULL || lsizep == NULL)
DBG("Argh, can't find dcache properties ! "
"sizep: %p, lsizep: %p\n", sizep, lsizep);
ie. fallback from block size to line size, and only print if both are missing.
That commit changed the names and the logic, but not in a consistent
fashion, making "d-cache-line-size" required to avoid the Argh:
bsizep = of_get_property(np, "d-cache-block-size",
NULL);
lsizep = of_get_property(np, "d-cache-line-size",
NULL);
if (bsizep == NULL)
bsizep = lsizep;
if (lsizep != NULL)
lsize = be32_to_cpu(*lsizep);
if (bsizep != NULL)
bsize = be32_to_cpu(*bsizep);
if (sizep == NULL || bsizep == NULL || lsizep == NULL)
DBG("Argh, can't find dcache properties ! "
"sizep: %p, bsizep: %p, lsizep: %p\n",
sizep, bsizep, lsizep);
Back then we fell back to cur_cpu_spec->dcache_bsize, which should be
correct. But since then we introduced the device tree CPU features
parsing, which does:
static struct cpu_spec __initdata base_cpu_spec = {
...
.icache_bsize = 32, /* minimum block size, fixed by */
.dcache_bsize = 32, /* cache info init. */
So on systems with new enough skiboot we now default to 32, which is
wrong on Power9.
Luckily this info is not used by the sysfs cache files, because that
code doesn't use the values we parse here, it goes and looks at the
device tree itself. Which is pretty gross but actually saves us in this
case.
These values do end up in the vdso_data, and I can see the wrong values
in the vdso_data:
1c:mon> d4 c000000002390000
c000000002390000 54535953 46434d45 50503a47 00343643 eyecatcher
c000000002390010 00000001 00000001 00000100 004e1202 major minor platform processor
c000000002390020 000000b0 00000000 00000000 0000003c processorCount physicalMemorySize
c000000002390030 57b7623f 0000ac10 1e848000 00000000 tb_orig_stamp tb_ticks_per_sec
c000000002390040 de6d9e42 008637af 8de66bca 0005e7ae tb_to_xs stamp_xsec
c000000002390050 000ff730 00000000 00000000 00000000 tb_update_count tz_minuteswest tz_dsttime
c000000002390060 00008000 00000020 00008000 00000020 dcache_size line_size icache_size icache_line_size
^
32 != 128
And that appears to flow through to glibc, ie. I see:
_SC_LEVEL1_ICACHE_LINESIZE = 32
_SC_LEVEL1_DCACHE_LINESIZE = 32
_SC_LEVEL2_CACHE_LINESIZE = 32
_SC_LEVEL3_CACHE_LINESIZE = 32
So excuse me while I go and swear at something.
cheers