2022-02-10 23:11:29

by Andreas Schwab

Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN

On Feb 10 2022, Atish Patra wrote:

> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 469b9739faf7..cca579bae8a0 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> for_each_of_cpu_node(node) {
> unsigned long this_hwcap = 0;
> uint64_t this_isa = 0;
> + char *temp;
>
> if (riscv_of_processor_hartid(node) < 0)
> continue;
> @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> continue;
> }
>
> + temp = (char *)isa;

There should be no need for this cast.

--
Andreas Schwab, [email protected]
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."

2022-02-14 10:22:09

by Geert Uytterhoeven

Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN

Hi Andreas,

On Thu, Feb 10, 2022 at 11:00 PM Andreas Schwab <[email protected]> wrote:
> On Feb 10 2022, Atish Patra wrote:
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 469b9739faf7..cca579bae8a0 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> > for_each_of_cpu_node(node) {
> > unsigned long this_hwcap = 0;
> > uint64_t this_isa = 0;
> > + char *temp;
> >
> > if (riscv_of_processor_hartid(node) < 0)
> > continue;
> > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> > continue;
> > }
> >
> > + temp = (char *)isa;
>
> There should be no need for this cast.

Indeed, but only if "temp" is changed to "const char *".

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds

2022-02-14 21:32:16

by Atish Patra

Subject: Re: [PATCH v2 5/6] RISC-V: Do no continue isa string parsing without correct XLEN

On Fri, Feb 11, 2022 at 4:52 AM Geert Uytterhoeven <[email protected]> wrote:
>
> Hi Andreas,
>
> On Thu, Feb 10, 2022 at 11:00 PM Andreas Schwab <[email protected]> wrote:
> > On Feb 10 2022, Atish Patra wrote:
> > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > > index 469b9739faf7..cca579bae8a0 100644
> > > --- a/arch/riscv/kernel/cpufeature.c
> > > +++ b/arch/riscv/kernel/cpufeature.c
> > > @@ -84,6 +84,7 @@ void __init riscv_fill_hwcap(void)
> > > for_each_of_cpu_node(node) {
> > > unsigned long this_hwcap = 0;
> > > uint64_t this_isa = 0;
> > > + char *temp;
> > >
> > > if (riscv_of_processor_hartid(node) < 0)
> > > continue;
> > > @@ -93,6 +94,7 @@ void __init riscv_fill_hwcap(void)
> > > continue;
> > > }
> > >
> > > + temp = (char *)isa;
> >
> > There should be no need for this cast.
>
> Indeed, but only if "temp" is changed to "const char *".
>

Yes. Fixed it in v3. Thanks.

> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- [email protected]
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds



--
Regards,
Atish