2022-06-29 08:22:04

by Krzysztof Kozlowski

Subject: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON

Add device node for CPU-memory BWMON device (bandwidth monitoring) on
SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level
Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth
votes from cpufreq (CPU nodes) thus achieve high memory throughput even
with lower CPU frequencies.

Co-developed-by: Thara Gopinath <[email protected]>
Signed-off-by: Thara Gopinath <[email protected]>
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 83e8b63f0910..e0f088996390 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 {
interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
};

+ pmu@1436400 {
+ compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon";
+ reg = <0 0x01436400 0 0x600>;
+ interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
+ interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ /*
+ * The interconnect paths bandwidths taken from
+ * cpu4_opp_table bandwidth.
+ * They also match different tables from
+ * msm-4.9 downstream kernel:
+ * - the OSM L3 from bandwidth table of
+ * qcom,cpu4-l3lat-mon (qcom,core-dev-table);
+ * bus width: 16 bytes;
+ */
+ opp-0 {
+ opp-peak-kBps = <4800000>;
+ };
+ opp-1 {
+ opp-peak-kBps = <9216000>;
+ };
+ opp-2 {
+ opp-peak-kBps = <15052800>;
+ };
+ opp-3 {
+ opp-peak-kBps = <20889600>;
+ };
+ opp-4 {
+ opp-peak-kBps = <25497600>;
+ };
+ };
+ };
+
pcie0: pci@1c00000 {
compatible = "qcom,pcie-sdm845";
reg = <0 0x01c00000 0 0x2000>,
--
2.34.1

2022-06-29 11:39:59

by Rajendra Nayak

Subject: Re: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON

On 6/29/2022 1:22 PM, Krzysztof Kozlowski wrote:
> Add device node for CPU-memory BWMON device (bandwidth monitoring) on
> SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level
> Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth
> votes from cpufreq (CPU nodes) thus achieve high memory throughput even
> with lower CPU frequencies.
>
> Co-developed-by: Thara Gopinath <[email protected]>
> Signed-off-by: Thara Gopinath <[email protected]>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> index 83e8b63f0910..e0f088996390 100644
> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
> @@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 {
> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> + pmu@1436400 {
> + compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon";
> + reg = <0 0x01436400 0 0x600>;
> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
> +
> + operating-points-v2 = <&cpu_bwmon_opp_table>;
> +
> + cpu_bwmon_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + /*
> + * The interconnect paths bandwidths taken from
> + * cpu4_opp_table bandwidth.
> + * They also match different tables from
> + * msm-4.9 downstream kernel:
> + * - the OSM L3 from bandwidth table of
> + * qcom,cpu4-l3lat-mon (qcom,core-dev-table);
> + * bus width: 16 bytes;
> + */

Maybe the comment needs an update?

> + opp-0 {
> + opp-peak-kBps = <4800000>;
> + };
> + opp-1 {
> + opp-peak-kBps = <9216000>;
> + };
> + opp-2 {
> + opp-peak-kBps = <15052800>;
> + };
> + opp-3 {
> + opp-peak-kBps = <20889600>;
> + };
> + opp-4 {
> + opp-peak-kBps = <25497600>;
> + };
> + };
> + };
> +
> pcie0: pci@1c00000 {
> compatible = "qcom,pcie-sdm845";
> reg = <0 0x01c00000 0 0x2000>,

2022-06-29 11:50:39

by Krzysztof Kozlowski

Subject: Re: [PATCH v5 4/4] arm64: dts: qcom: sdm845: Add CPU BWMON

On 29/06/2022 13:22, Rajendra Nayak wrote:
>
>
> On 6/29/2022 1:22 PM, Krzysztof Kozlowski wrote:
>> Add device node for CPU-memory BWMON device (bandwidth monitoring) on
>> SDM845 measuring bandwidth between CPU (gladiator_noc) and Last Level
>> Cache (memnoc). Usage of this BWMON allows to remove fixed bandwidth
>> votes from cpufreq (CPU nodes) thus achieve high memory throughput even
>> with lower CPU frequencies.
>>
>> Co-developed-by: Thara Gopinath <[email protected]>
>> Signed-off-by: Thara Gopinath <[email protected]>
>> Signed-off-by: Krzysztof Kozlowski <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sdm845.dtsi | 38 ++++++++++++++++++++++++++++
>> 1 file changed, 38 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> index 83e8b63f0910..e0f088996390 100644
>> --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
>> @@ -2026,6 +2026,44 @@ llcc: system-cache-controller@1100000 {
>> interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
>> };
>>
>> + pmu@1436400 {
>> + compatible = "qcom,sdm845-cpu-bwmon", "qcom,msm8998-cpu-bwmon";
>> + reg = <0 0x01436400 0 0x600>;
>> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
>> + interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
>> +
>> + operating-points-v2 = <&cpu_bwmon_opp_table>;
>> +
>> + cpu_bwmon_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + /*
>> + * The interconnect paths bandwidths taken from
>> + * cpu4_opp_table bandwidth.
>> + * They also match different tables from
>> + * msm-4.9 downstream kernel:
>> + * - the OSM L3 from bandwidth table of
>> + * qcom,cpu4-l3lat-mon (qcom,core-dev-table);
>> + * bus width: 16 bytes;
>> + */
>
> Maybe the comment needs an update?

Yes, a bit.

Best regards,
Krzysztof