On sparc, irqs are not present as an IORESOURCE in the struct platform_device
representation. Therefore, for sparc the irq needs to be fetched in a different
manner.
The GRLIB port of the ocores i2c controller needs custom getreg and setreg
functions to allow for big endian register access and to deal with the fact that
the PRELOW and PREHIGH registers have been merged into one register.
Signed-off-by: Andreas Larsson <[email protected]>
Andreas Larsson (2):
i2c: i2c-ocores: Add irq support for sparc
i2c: i2c-ocores: Add support for the GRLIB port of the controller and
custom getreg and setreg functions
drivers/i2c/busses/i2c-ocores.c | 70 +++++++++++++++++++++++++++++++++++---
1 files changed, 64 insertions(+), 6 deletions(-)
There are no platform resources of type IORESOURCE_IRQ on sparc, so the irq
number is acquired in a different manner for sparc. The general case uses
platform_get_irq, that internally still uses platform_get_resource.
Signed-off-by: Andreas Larsson <[email protected]>
---
drivers/i2c/busses/i2c-ocores.c | 13 +++++++++----
1 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index bffd550..1eb8a65 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -267,16 +267,21 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
{
struct ocores_i2c *i2c;
struct ocores_i2c_platform_data *pdata;
- struct resource *res, *res2;
+ struct resource *res;
int ret;
int i;
+ int irq;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res)
return -ENODEV;
- res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
- if (!res2)
+#ifdef CONFIG_SPARC
+ irq = pdev->archdata.irqs[0];
+#else
+ irq = platform_get_irq(pdev, 0);
+#endif
+ if (irq < 0)
return -ENODEV;
i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
@@ -313,7 +318,7 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
ocores_init(i2c);
init_waitqueue_head(&i2c->wait);
- ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
+ ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
pdev->name, i2c);
if (ret) {
dev_err(&pdev->dev, "Cannot claim IRQ\n");
--
1.7.0.4
The registers in the GRLIB port of the controller are 32-bit and in big endian
byte order. The PRELOW and PREHIGH registers are merged into one register. The
subsequent registers have their offset decreased accordingly. Hence the register
access needs to be handled in a non-standard manner using custom getreg and
setreg functions.
Signed-off-by: Andreas Larsson <[email protected]>
---
drivers/i2c/busses/i2c-ocores.c | 57 +++++++++++++++++++++++++++++++++++++-
1 files changed, 55 insertions(+), 2 deletions(-)
diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
index 1eb8a65..e3df62f 100644
--- a/drivers/i2c/busses/i2c-ocores.c
+++ b/drivers/i2c/busses/i2c-ocores.c
@@ -4,6 +4,9 @@
*
* Peter Korsgaard <[email protected]>
*
+ * Support for the GRLIB port of the controller by
+ * Andreas Larsson <[email protected]>
+ *
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
@@ -38,6 +41,8 @@ struct ocores_i2c {
int nmsgs;
int state; /* see STATE_ */
int clock_khz;
+ void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
+ u8 (*getreg)(struct ocores_i2c *i2c, int reg);
};
/* registers */
@@ -73,7 +78,9 @@ struct ocores_i2c {
static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
{
- if (i2c->reg_io_width == 4)
+ if (i2c->setreg)
+ i2c->setreg(i2c, reg, value);
+ else if (i2c->reg_io_width == 4)
iowrite32(value, i2c->base + (reg << i2c->reg_shift));
else if (i2c->reg_io_width == 2)
iowrite16(value, i2c->base + (reg << i2c->reg_shift));
@@ -83,7 +90,9 @@ static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
{
- if (i2c->reg_io_width == 4)
+ if (i2c->getreg)
+ return i2c->getreg(i2c, reg);
+ else if (i2c->reg_io_width == 4)
return ioread32(i2c->base + (reg << i2c->reg_shift));
else if (i2c->reg_io_width == 2)
return ioread16(i2c->base + (reg << i2c->reg_shift));
@@ -91,6 +100,40 @@ static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
return ioread8(i2c->base + (reg << i2c->reg_shift));
}
+/* Read and write functions for the GRLIB port of the controller. Registers are
+ * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
+ * register. The subsequent registers has their offset decreased accordingly. */
+static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
+{
+ u32 rd;
+ int rreg = reg;
+ if (reg != OCI2C_PRELOW)
+ rreg--;
+ rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
+ if (reg == OCI2C_PREHIGH)
+ return (u8)rd >> 8;
+ else
+ return (u8)rd;
+}
+
+static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
+{
+ u32 curr, wr;
+ int rreg = reg;
+ if (reg != OCI2C_PRELOW)
+ rreg--;
+ if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
+ curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
+ if (reg == OCI2C_PRELOW)
+ wr = (curr & 0xff00) | value;
+ else
+ wr = (((u32)value) << 8) | (curr & 0xff);
+ } else {
+ wr = value;
+ }
+ iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
+}
+
static void ocores_process(struct ocores_i2c *i2c)
{
struct i2c_msg *msg = i2c->msg;
@@ -233,6 +276,7 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
{
struct device_node *np = pdev->dev.of_node;
u32 val;
+ const char *name;
if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
/* no 'reg-shift', check for deprecated 'regstep' */
@@ -257,6 +301,15 @@ static int ocores_i2c_of_probe(struct platform_device *pdev,
of_property_read_u32(pdev->dev.of_node, "reg-io-width",
&i2c->reg_io_width);
+
+ name = of_get_property(pdev->dev.of_node, "name", NULL);
+ if (name && (!strcmp(name, "GAISLER_I2CMST") ||
+ !strcmp(name, "01_028"))) {
+ dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
+ i2c->setreg = oc_setreg_grlib;
+ i2c->getreg = oc_getreg_grlib;
+ }
+
return 0;
}
#else
--
1.7.0.4
>>>>> "Andreas" == Andreas Larsson <[email protected]> writes:
Andreas> There are no platform resources of type IORESOURCE_IRQ on
Andreas> sparc, so the irq number is acquired in a different manner for
Andreas> sparc. The general case uses platform_get_irq, that internally
Andreas> still uses platform_get_resource.
I have no idea why sparc is being odd in this regard, but assuming this
is how it's done, I'm fine with this change.
A quick grep doesn't find any other drivers doing this though:
git grep -l archdata.irqs drivers | xargs grep platform_get_irq
Acked-by: Peter Korsgaard <[email protected]>
Andreas> Signed-off-by: Andreas Larsson <[email protected]>
Andreas> ---
Andreas> drivers/i2c/busses/i2c-ocores.c | 13 +++++++++----
Andreas> 1 files changed, 9 insertions(+), 4 deletions(-)
Andreas> diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
Andreas> index bffd550..1eb8a65 100644
Andreas> --- a/drivers/i2c/busses/i2c-ocores.c
Andreas> +++ b/drivers/i2c/busses/i2c-ocores.c
Andreas> @@ -267,16 +267,21 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
Andreas> {
Andreas> struct ocores_i2c *i2c;
Andreas> struct ocores_i2c_platform_data *pdata;
Andreas> - struct resource *res, *res2;
Andreas> + struct resource *res;
Andreas> int ret;
Andreas> int i;
Andreas> + int irq;
Andreas> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Andreas> if (!res)
Andreas> return -ENODEV;
Andreas> - res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
Andreas> - if (!res2)
Andreas> +#ifdef CONFIG_SPARC
Andreas> + irq = pdev->archdata.irqs[0];
Andreas> +#else
Andreas> + irq = platform_get_irq(pdev, 0);
Andreas> +#endif
Andreas> + if (irq < 0)
Andreas> return -ENODEV;
Andreas> i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
Andreas> @@ -313,7 +318,7 @@ static int __devinit ocores_i2c_probe(struct platform_device *pdev)
Andreas> ocores_init(i2c);
Andreas> init_waitqueue_head(&i2c->wait);
Andreas> - ret = devm_request_irq(&pdev->dev, res2->start, ocores_isr, 0,
Andreas> + ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
pdev-> name, i2c);
Andreas> if (ret) {
Andreas> dev_err(&pdev->dev, "Cannot claim IRQ\n");
Andreas> --
Andreas> 1.7.0.4
Andreas> --
Andreas> To unsubscribe from this list: send the line "unsubscribe linux-i2c" in
Andreas> the body of a message to [email protected]
Andreas> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Bye, Peter Korsgaard
>>>>> "Andreas" == Andreas Larsson <[email protected]> writes:
Andreas> The registers in the GRLIB port of the controller are 32-bit
Andreas> and in big endian byte order. The PRELOW and PREHIGH registers
Andreas> are merged into one register. The subsequent registers have
Andreas> their offset decreased accordingly. Hence the register access
Andreas> needs to be handled in a non-standard manner using custom
Andreas> getreg and
Andreas> setreg functions.
Andreas> Signed-off-by: Andreas Larsson <[email protected]>
Andreas> ---
Andreas> drivers/i2c/busses/i2c-ocores.c | 57 +++++++++++++++++++++++++++++++++++++-
Andreas> 1 files changed, 55 insertions(+), 2 deletions(-)
Andreas> diff --git a/drivers/i2c/busses/i2c-ocores.c b/drivers/i2c/busses/i2c-ocores.c
Andreas> index 1eb8a65..e3df62f 100644
Andreas> --- a/drivers/i2c/busses/i2c-ocores.c
Andreas> +++ b/drivers/i2c/busses/i2c-ocores.c
Andreas> @@ -4,6 +4,9 @@
Andreas> *
Andreas> * Peter Korsgaard <[email protected]>
Andreas> *
Andreas> + * Support for the GRLIB port of the controller by
Andreas> + * Andreas Larsson <[email protected]>
Andreas> + *
Andreas> * This file is licensed under the terms of the GNU General Public License
Andreas> * version 2. This program is licensed "as is" without any warranty of any
Andreas> * kind, whether express or implied.
Andreas> @@ -38,6 +41,8 @@ struct ocores_i2c {
Andreas> int nmsgs;
Andreas> int state; /* see STATE_ */
Andreas> int clock_khz;
Andreas> + void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
Andreas> + u8 (*getreg)(struct ocores_i2c *i2c, int reg);
Andreas> };
Andreas> /* registers */
Andreas> @@ -73,7 +78,9 @@ struct ocores_i2c {
Andreas> static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
Andreas> {
Andreas> - if (i2c->reg_io_width == 4)
Andreas> + if (i2c->setreg)
Andreas> + i2c->setreg(i2c, reg, value);
Andreas> + else if (i2c->reg_io_width == 4)
Andreas> iowrite32(value, i2c->base + (reg << i2c->reg_shift));
Andreas> else if (i2c->reg_io_width == 2)
Andreas> iowrite16(value, i2c->base + (reg << i2c->reg_shift));
Andreas> @@ -83,7 +90,9 @@ static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
Andreas> static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
Andreas> {
Andreas> - if (i2c->reg_io_width == 4)
Andreas> + if (i2c->getreg)
Andreas> + return i2c->getreg(i2c, reg);
Andreas> + else if (i2c->reg_io_width == 4)
Andreas> return ioread32(i2c->base + (reg << i2c->reg_shift));
Andreas> else if (i2c->reg_io_width == 2)
Andreas> return ioread16(i2c->base + (reg << i2c->reg_shift));
Andreas> @@ -91,6 +100,40 @@ static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
Andreas> return ioread8(i2c->base + (reg << i2c->reg_shift));
Andreas> }
Andreas> +/* Read and write functions for the GRLIB port of the controller. Registers are
Andreas> + * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
Andreas> + * register. The subsequent registers has their offset decreased accordingly. */
Andreas> +static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
Andreas> +{
Andreas> + u32 rd;
Andreas> + int rreg = reg;
Andreas> + if (reg != OCI2C_PRELOW)
Andreas> + rreg--;
Andreas> + rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
Andreas> + if (reg == OCI2C_PREHIGH)
Andreas> + return (u8)rd >> 8;
Andreas> + else
Andreas> + return (u8)rd;
Andreas> +}
Andreas> +
Andreas> +static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
Andreas> +{
Andreas> + u32 curr, wr;
Andreas> + int rreg = reg;
Andreas> + if (reg != OCI2C_PRELOW)
Andreas> + rreg--;
Andreas> + if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
Andreas> + curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
Andreas> + if (reg == OCI2C_PRELOW)
Andreas> + wr = (curr & 0xff00) | value;
Andreas> + else
Andreas> + wr = (((u32)value) << 8) | (curr & 0xff);
Andreas> + } else {
Andreas> + wr = value;
Andreas> + }
Andreas> + iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
Are all platforms using i2c-ocores guaranteed to provide ioread32be /
iowrite32be or should we stick an #ifdef CONFIG_SPARC around it?
--
Bye, Peter Korsgaard
On 10/23/2012 10:13 PM, Peter Korsgaard wrote:
>>>>>> "Andreas" == Andreas Larsson <[email protected]> writes:
>
> Andreas> There are no platform resources of type IORESOURCE_IRQ on
> Andreas> sparc, so the irq number is acquired in a different manner for
> Andreas> sparc. The general case uses platform_get_irq, that internally
> Andreas> still uses platform_get_resource.
>
> I have no idea why sparc is being odd in this regard, but assuming this
> is how it's done, I'm fine with this change.
>
> A quick grep doesn't find any other drivers doing this though:
>
> git grep -l archdata.irqs drivers | xargs grep platform_get_irq
>
> Acked-by: Peter Korsgaard <[email protected]>
Other drivers that work both on sparc and on other platforms usually use
irq_of_parse_and_map on a corresponding device_node. For non-sparc
architectures irq_of_parse_and_map sets up mappings that needs to be
teared down on module exit. Sparc however has its own version of
irq_of_parse_and_map that just returns the irq number using archdata.irq[].
I am trying to get through a patch platform_get_irq to work for sparc as
well. If that eventually goes through, the CONFIG_SPARC stuff can then
be removed cleanly from this driver withouth having to mess with
irq_of_parse_and_map and tearing mappings down.
Another solution is to use irq_of_parse_and_map for the of-case if no
irq was found using platform_get_irq. But that would make for more
rearrangements and add the need for irq_dispose_mapping to be added on
module exit as well (even though the disposing would do nothing for sparc).
Cheers,
Andreas Larsson
On 10/23/2012 10:24 PM, Peter Korsgaard wrote:
>>>>>> "Andreas" == Andreas Larsson <[email protected]> writes:
> [...]
> Andreas> +/* Read and write functions for the GRLIB port of the controller. Registers are
> Andreas> + * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
> Andreas> + * register. The subsequent registers has their offset decreased accordingly. */
> Andreas> +static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
> Andreas> +{
> Andreas> + u32 rd;
> Andreas> + int rreg = reg;
> Andreas> + if (reg != OCI2C_PRELOW)
> Andreas> + rreg--;
> Andreas> + rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
> Andreas> + if (reg == OCI2C_PREHIGH)
> Andreas> + return (u8)rd >> 8;
> Andreas> + else
> Andreas> + return (u8)rd;
> Andreas> +}
> Andreas> +
> Andreas> +static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
> Andreas> +{
> Andreas> + u32 curr, wr;
> Andreas> + int rreg = reg;
> Andreas> + if (reg != OCI2C_PRELOW)
> Andreas> + rreg--;
> Andreas> + if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
> Andreas> + curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
> Andreas> + if (reg == OCI2C_PRELOW)
> Andreas> + wr = (curr & 0xff00) | value;
> Andreas> + else
> Andreas> + wr = (((u32)value) << 8) | (curr & 0xff);
> Andreas> + } else {
> Andreas> + wr = value;
> Andreas> + }
> Andreas> + iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
>
> Are all platforms using i2c-ocores guaranteed to provide ioread32be /
> iowrite32be or should we stick an #ifdef CONFIG_SPARC around it?
As far as I can see, after digging around, the only platforms that have
ioread/write32, but not ioread/write32be are frv and mn10300. Do you
know if those platforms are using i2c-ocores?
Cheers,
Andreas Larsson
>>>>> "Andreas" == Andreas Larsson <[email protected]> writes:
>> Are all platforms using i2c-ocores guaranteed to provide ioread32be /
>> iowrite32be or should we stick an #ifdef CONFIG_SPARC around it?
Andreas> As far as I can see, after digging around, the only platforms that
Andreas> have ioread/write32, but not ioread/write32be are frv and mn10300. Do
Andreas> you know if those platforms are using i2c-ocores?
Not to my knowledge, no. In that case:
Acked-by: Peter Korsgaard <[email protected]>
--
Bye, Peter Korsgaard