This adds the main Sparx5 SoC DT documentation file, with information
abut the supported board types.
Reviewed-by: Alexandre Belloni <[email protected]>
Signed-off-by: Lars Povlsen <[email protected]>
---
.../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
new file mode 100644
index 0000000000000..83b36d1217988
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Boards Device Tree Bindings
+
+maintainers:
+ - Lars Povlsen <[email protected]>
+
+description: |+
+ The Microchip Sparx5 SoC is a ARMv8-based used in a family of
+ gigabit TSN-capable gigabit switches.
+
+ The SparX-5 Ethernet switch family provides a rich set of switching
+ features such as advanced TCAM-based VLAN and QoS processing
+ enabling delivery of differentiated services, and security through
+ TCAM-based frame processing using versatile content aware processor
+ (VCAP)
+
+properties:
+ $nodename:
+ const: '/'
+ compatible:
+ oneOf:
+ - description: The Sparx5 pcb125 board is a modular board,
+ which has both spi-nor and eMMC storage. The modular design
+ allows for connection of different network ports.
+ items:
+ - const: microchip,sparx5-pcb125
+ - const: microchip,sparx5
+
+ - description: The Sparx5 pcb134 is a pizzabox form factor
+ gigabit switch with 20 SFP ports. It features spi-nor and
+ either spi-nand or eMMC storage (mount option).
+ items:
+ - const: microchip,sparx5-pcb134
+ - const: microchip,sparx5
+
+ - description: The Sparx5 pcb135 is a pizzabox form factor
+ gigabit switch with 48+4 Cu ports. It features spi-nor and
+ either spi-nand or eMMC storage (mount option).
+ items:
+ - const: microchip,sparx5-pcb135
+ - const: microchip,sparx5
+
+ axi@600000000:
+ type: object
+ description: the root node in the Sparx5 platforms must contain
+ an axi bus child node. They are always at physical address
+ 0x600000000 in all the Sparx5 variants.
+ properties:
+ compatible:
+ items:
+ - const: simple-bus
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+patternProperties:
+ "^syscon@[0-9a-f]+$":
+ description: All Sparx5 boards must provide a system controller,
+ typically under the axi bus node. It contain reset registers and
+ other system control.
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: microchip,sparx5-cpu-syscon
+ - const: syscon
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - reg
+
+required:
+ - compatible
+ - axi@600000000
+ - syscon@600000000
+
+...
--
2.26.2
On Wed, May 13, 2020 at 02:55:23PM +0200, Lars Povlsen wrote:
> This adds the main Sparx5 SoC DT documentation file, with information
> abut the supported board types.
>
> Reviewed-by: Alexandre Belloni <[email protected]>
> Signed-off-by: Lars Povlsen <[email protected]>
> ---
> .../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++
> 1 file changed, 87 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
>
> diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
> new file mode 100644
> index 0000000000000..83b36d1217988
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip Sparx5 Boards Device Tree Bindings
> +
> +maintainers:
> + - Lars Povlsen <[email protected]>
> +
> +description: |+
> + The Microchip Sparx5 SoC is a ARMv8-based used in a family of
> + gigabit TSN-capable gigabit switches.
> +
> + The SparX-5 Ethernet switch family provides a rich set of switching
> + features such as advanced TCAM-based VLAN and QoS processing
> + enabling delivery of differentiated services, and security through
> + TCAM-based frame processing using versatile content aware processor
> + (VCAP)
> +
> +properties:
> + $nodename:
> + const: '/'
> + compatible:
> + oneOf:
> + - description: The Sparx5 pcb125 board is a modular board,
> + which has both spi-nor and eMMC storage. The modular design
> + allows for connection of different network ports.
> + items:
> + - const: microchip,sparx5-pcb125
> + - const: microchip,sparx5
> +
> + - description: The Sparx5 pcb134 is a pizzabox form factor
> + gigabit switch with 20 SFP ports. It features spi-nor and
> + either spi-nand or eMMC storage (mount option).
> + items:
> + - const: microchip,sparx5-pcb134
> + - const: microchip,sparx5
> +
> + - description: The Sparx5 pcb135 is a pizzabox form factor
> + gigabit switch with 48+4 Cu ports. It features spi-nor and
> + either spi-nand or eMMC storage (mount option).
> + items:
> + - const: microchip,sparx5-pcb135
> + - const: microchip,sparx5
> +
> + axi@600000000:
> + type: object
> + description: the root node in the Sparx5 platforms must contain
> + an axi bus child node. They are always at physical address
> + 0x600000000 in all the Sparx5 variants.
> + properties:
> + compatible:
> + items:
> + - const: simple-bus
> + reg:
> + maxItems: 1
simple-bus doesn't have 'reg'. If there's bus registers, then it's not
simple.
> +
> + required:
> + - compatible
> + - reg
> +
> +patternProperties:
> + "^syscon@[0-9a-f]+$":
This should be under a bus node.
> + description: All Sparx5 boards must provide a system controller,
> + typically under the axi bus node. It contain reset registers and
> + other system control.
> + type: object
> + properties:
> + compatible:
> + items:
> + - const: microchip,sparx5-cpu-syscon
> + - const: syscon
This probably should be in its own document. If really this simple,
there's already syscon.yaml you can add to.
> + reg:
> + maxItems: 1
> +
> + required:
> + - compatible
> + - reg
> +
> +required:
> + - compatible
> + - axi@600000000
> + - syscon@600000000
> +
> +...
> --
> 2.26.2
Rob Herring writes:
> On Wed, May 13, 2020 at 02:55:23PM +0200, Lars Povlsen wrote:
>> This adds the main Sparx5 SoC DT documentation file, with information
>> abut the supported board types.
>>
>> Reviewed-by: Alexandre Belloni <[email protected]>
>> Signed-off-by: Lars Povlsen <[email protected]>
>> ---
>> .../bindings/arm/microchip,sparx5.yaml | 87 +++++++++++++++++++
>> 1 file changed, 87 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
>> new file mode 100644
>> index 0000000000000..83b36d1217988
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/microchip,sparx5.yaml
>> @@ -0,0 +1,87 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/arm/microchip,sparx5.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Microchip Sparx5 Boards Device Tree Bindings
>> +
>> +maintainers:
>> + - Lars Povlsen <[email protected]>
>> +
>> +description: |+
>> + The Microchip Sparx5 SoC is a ARMv8-based used in a family of
>> + gigabit TSN-capable gigabit switches.
>> +
>> + The SparX-5 Ethernet switch family provides a rich set of switching
>> + features such as advanced TCAM-based VLAN and QoS processing
>> + enabling delivery of differentiated services, and security through
>> + TCAM-based frame processing using versatile content aware processor
>> + (VCAP)
>> +
>> +properties:
>> + $nodename:
>> + const: '/'
>> + compatible:
>> + oneOf:
>> + - description: The Sparx5 pcb125 board is a modular board,
>> + which has both spi-nor and eMMC storage. The modular design
>> + allows for connection of different network ports.
>> + items:
>> + - const: microchip,sparx5-pcb125
>> + - const: microchip,sparx5
>> +
>> + - description: The Sparx5 pcb134 is a pizzabox form factor
>> + gigabit switch with 20 SFP ports. It features spi-nor and
>> + either spi-nand or eMMC storage (mount option).
>> + items:
>> + - const: microchip,sparx5-pcb134
>> + - const: microchip,sparx5
>> +
>> + - description: The Sparx5 pcb135 is a pizzabox form factor
>> + gigabit switch with 48+4 Cu ports. It features spi-nor and
>> + either spi-nand or eMMC storage (mount option).
>> + items:
>> + - const: microchip,sparx5-pcb135
>> + - const: microchip,sparx5
>> +
>> + axi@600000000:
>> + type: object
>> + description: the root node in the Sparx5 platforms must contain
>> + an axi bus child node. They are always at physical address
>> + 0x600000000 in all the Sparx5 variants.
>> + properties:
>> + compatible:
>> + items:
>> + - const: simple-bus
>> + reg:
>> + maxItems: 1
>
> simple-bus doesn't have 'reg'. If there's bus registers, then it's not
> simple.
>
Ooops, that's a leftover. I'll remove.
>> +
>> + required:
>> + - compatible
>> + - reg
>> +
>> +patternProperties:
>> + "^syscon@[0-9a-f]+$":
>
> This should be under a bus node.
I thought it was? But anyway, with the change below I guess the entire
block goes away.
>
>> + description: All Sparx5 boards must provide a system controller,
>> + typically under the axi bus node. It contain reset registers and
>> + other system control.
>> + type: object
>> + properties:
>> + compatible:
>> + items:
>> + - const: microchip,sparx5-cpu-syscon
>> + - const: syscon
>
> This probably should be in its own document. If really this simple,
> there's already syscon.yaml you can add to.
Good suggestion, I'll add it to mfd/syscon.yaml then.
>
>> + reg:
>> + maxItems: 1
>> +
>> + required:
>> + - compatible
>> + - reg
>> +
>> +required:
>> + - compatible
>> + - axi@600000000
>> + - syscon@600000000
>> +
>> +...
>> --
>> 2.26.2
--
Lars Povlsen,
Microchip