00:05.0 VGA compatible controller: Texas Instruments TVP4020 [Permedia 2] (rev 01)
00:07.0 SCSI storage controller: Adaptec AHA-2940U/UW/D / AIC-7881U (rev 01)
00:08.0 ISA bridge: Contaq Microsystems 82c693
00:08.1 IDE interface: Contaq Microsystems 82c693
00:08.2 IDE interface: Contaq Microsystems 82c693
00:08.3 USB Controller: Contaq Microsystems 82c693
00:09.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 30)
00:05.0 VGA compatible controller: Texas Instruments TVP4020 [Permedia 2] (rev 01) (prog-if 00 [VGA])
Subsystem: Diamond Multimedia Systems FIRE GL 1000 PRO
Flags: bus master, medium devsel, latency 32, IRQ 25
Memory at 000000000a000000 (32-bit, non-prefetchable) [size=128K]
Memory at 0000000009000000 (32-bit, non-prefetchable) [size=8M]
Memory at 0000000009800000 (32-bit, non-prefetchable) [size=8M]
Expansion ROM at 000000000a040000 [disabled] [size=64K]
00:07.0 SCSI storage controller: Adaptec AHA-2940U/UW/D / AIC-7881U (rev 01)
Subsystem: Adaptec AHA-2940UW SCSI Host Adapter
Flags: bus master, medium devsel, latency 32, IRQ 26
I/O ports at 8000 [size=256]
Memory at 000000000a060000 (32-bit, non-prefetchable) [disabled] [size=4K]
Expansion ROM at 000000000a050000 [disabled] [size=64K]
Capabilities: [dc] Power Management version 1
00:08.0 ISA bridge: Contaq Microsystems 82c693
Flags: bus master, medium devsel, latency 0
00:08.1 IDE interface: Contaq Microsystems 82c693 (prog-if 80 [Master])
Flags: bus master, medium devsel, latency 0
I/O ports at 01f0 [size=8]
I/O ports at 03f4 [size=4]
I/O ports at 8480 [size=16]
00:08.2 IDE interface: Contaq Microsystems 82c693 (prog-if 00 [])
Flags: bus master, medium devsel, latency 0
I/O ports at 0170 [size=8]
I/O ports at 0374 [size=4]
00:08.3 USB Controller: Contaq Microsystems 82c693 (prog-if 10 [OHCI])
Flags: bus master, medium devsel, latency 32
Memory at 000000000a061000 (32-bit, non-prefetchable) [size=4K]
00:09.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 30)
Subsystem: 3Com Corporation 3C905B Fast Etherlink XL 10/100
Flags: bus master, medium devsel, latency 32, IRQ 24
I/O ports at 8400 [size=128]
Memory at 000000000a062000 (32-bit, non-prefetchable) [size=128]
Expansion ROM at 000000000a020000 [disabled] [size=128K]
Capabilities: [dc] Power Management version 1
00:05.0 VGA compatible controller: Texas Instruments TVP4020 [Permedia 2] (rev 01) (prog-if 00 [VGA])
Subsystem: Diamond Multimedia Systems FIRE GL 1000 PRO
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (48000ns min, 48000ns max)
Interrupt: pin A routed to IRQ 25
Region 0: Memory at 000000000a000000 (32-bit, non-prefetchable) [size=128K]
Region 1: Memory at 0000000009000000 (32-bit, non-prefetchable) [size=8M]
Region 2: Memory at 0000000009800000 (32-bit, non-prefetchable) [size=8M]
Expansion ROM at 000000000a040000 [disabled] [size=64K]
00:07.0 SCSI storage controller: Adaptec AHA-2940U/UW/D / AIC-7881U (rev 01)
Subsystem: Adaptec AHA-2940UW SCSI Host Adapter
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2000ns min, 2000ns max), cache line size 08
Interrupt: pin A routed to IRQ 26
Region 0: I/O ports at 8000 [size=256]
Region 1: Memory at 000000000a060000 (32-bit, non-prefetchable) [disabled] [size=4K]
Expansion ROM at 000000000a050000 [disabled] [size=64K]
Capabilities: [dc] Power Management version 1
Flags: PMEClk- DSI+ D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
00:08.0 ISA bridge: Contaq Microsystems 82c693
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
00:08.1 IDE interface: Contaq Microsystems 82c693 (prog-if 80 [Master])
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Interrupt: pin A routed to IRQ 0
Region 0: I/O ports at 01f0 [size=8]
Region 1: I/O ports at 03f4 [size=4]
Region 4: I/O ports at 8480 [size=16]
00:08.2 IDE interface: Contaq Microsystems 82c693 (prog-if 00 [])
Control: I/O+ Mem- BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR- FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 0
Interrupt: pin B routed to IRQ 0
Region 0: I/O ports at 0170 [size=8]
Region 1: I/O ports at 0374 [size=4]
00:08.3 USB Controller: Contaq Microsystems 82c693 (prog-if 10 [OHCI])
Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: Cap- 66Mhz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32, cache line size 08
Interrupt: pin A routed to IRQ 0
Region 0: Memory at 000000000a061000 (32-bit, non-prefetchable) [size=4K]
00:09.0 Ethernet controller: 3Com Corporation 3c905B 100BaseTX [Cyclone] (rev 30)
Subsystem: 3Com Corporation 3C905B Fast Etherlink XL 10/100
Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV+ VGASnoop- ParErr+ Stepping- SERR+ FastB2B-
Status: Cap+ 66Mhz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
Latency: 32 (2500ns min, 2500ns max), cache line size 08
Interrupt: pin A routed to IRQ 24
Region 0: I/O ports at 8400 [size=128]
Region 1: Memory at 000000000a062000 (32-bit, non-prefetchable) [size=128]
Expansion ROM at 000000000a020000 [disabled] [size=128K]
Capabilities: [dc] Power Management version 1
Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1+,D2+,D3hot+,D3cold-)
Status: D0 PME-Enable- DSel=0 DScale=0 PME-
Thomas Steudten <[email protected]> wrote:
>
> In ./drivers/block/ll_rw_blk.c __make_request:2021
> 2021 spin_lock_prefetch(q->queue_lock);
> 2022
> 2023 barrier = test_bit(BIO_RW_BARRIER, &bio->bi_rw);
> 2024
> 2025 ra = bio->bi_rw & (1 << BIO_RW_AHEAD);
>
>
> 3338: 00 00 e3 8b lds $f31,0(t2)
>
> processor.h:94
> extern inline void spin_lock_prefetch(const void *ptr)
> {
> __builtin_prefetch(ptr, 1, 3);
> }
>
> So q->queue_lock isn?t aligned for alpha - or q isn?t valid.
The spinlock is aligned OK. Could you add this patch so we can see
a bit more context?
diff -puN arch/alpha/kernel/traps.c~alpha-stack-dump arch/alpha/kernel/traps.c
--- 25/arch/alpha/kernel/traps.c~alpha-stack-dump Mon Nov 17 13:10:21 2003
+++ 25-akpm/arch/alpha/kernel/traps.c Mon Nov 17 13:10:30 2003
@@ -636,6 +636,7 @@ do_entUna(void * va, unsigned long opcod
lock_kernel();
printk("Bad unaligned kernel access at %016lx: %p %lx %ld\n",
pc, va, opcode, reg);
+ dump_stack();
do_exit(SIGSEGV);
got_exception:
_
Thomas Steudten <[email protected]> writes:
> -> 0xfffffc0000476cb8 <__make_request+152>: lds $f31,0(t2)
The kernel is stupid, this is a prefetch, it should be totally ignored
if it is faulty. This is already handled for userspace accesses
IIRC... (I wonder why the PALcode doesn't already do that. Oh well.)
--
Falk
On http://steudten.com/alpha/perf.php4 you can read:
See prefetch section:
The Alpha 21264 initiates a prefetch operation by executing one of the load
instructions as summarized in the table below. Note that the destination
register is R31 or F31. When used as a source register, R31 and F31 return
integer zero and floating point zero, respectively. When used as a
destination register as shown below, R31 and F31 denote the purpose of
these instructions as a prefetch operation. Earlier Alpha implementations
ignore these instructions. Some care must be taken as a prefetch with an
invalid address must be dismissed by firmware and a prefetch can cause an
alignment trap.
Tom
Falk Hueffner wrote:
> Thomas Steudten <[email protected]> writes:
>
>
>>-> 0xfffffc0000476cb8 <__make_request+152>: lds $f31,0(t2)
>
>
> The kernel is stupid, this is a prefetch, it should be totally ignored
> if it is faulty. This is already handled for userspace accesses
> IIRC... (I wonder why the PALcode doesn't already do that. Oh well.)
>
--
Tom
LINUX user since kernel 0.99.x 1994.
RPM Alpha packages at http://alpha.steudten.com/packages
Want to know what S.u.S.E 1995 cdrom-set contains?
Thomas Steudten <[email protected]> writes:
> On http://steudten.com/alpha/perf.php4 you can read:
> See prefetch section:
> The Alpha 21264 initiates a prefetch operation by executing one of the
> load instructions as summarized in the table below. Note that the
> destination register is R31 or F31. When used as a source register,
> R31 and F31 return integer zero and floating point zero,
> respectively. When used as a destination register as shown below, R31
> and F31 denote the purpose of these instructions as a prefetch
> operation. Earlier Alpha implementations ignore these
> instructions. Some care must be taken as a prefetch with an invalid
> address must be dismissed by firmware and a prefetch can cause an
> alignment trap.
Well, the architecture manual requires these instructions have no
visible effect whatsoever, i. e. they never trap. It seems sensible to
me to enforce this also in kernel space, since this is what gcc
assumes.
--
Falk
On Mon, Nov 17, 2003 at 10:48:49PM +0100, Falk Hueffner wrote:
> Well, the architecture manual requires these instructions have no
> visible effect whatsoever, i. e. they never trap.
No. Unaligned != invalid.
We shouldn't prefetch the spinlocks on UP.
Ivan.
--- 2.6/include/asm-alpha/processor.h Sat Oct 25 22:44:54 2003
+++ linux/include/asm-alpha/processor.h Tue Nov 18 01:48:39 2003
@@ -78,6 +78,11 @@ unsigned long get_wchan(struct task_stru
#define ARCH_HAS_PREFETCHW
#define ARCH_HAS_SPINLOCK_PREFETCH
+#ifndef CONFIG_SMP
+/* Nothing to prefetch. */
+#define spin_lock_prefetch(lock) do { } while (0)
+#endif
+
#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)
extern inline void prefetch(const void *ptr)
{
@@ -89,10 +94,13 @@ extern inline void prefetchw(const void
__builtin_prefetch(ptr, 1, 3);
}
+#ifdef CONFIG_SMP
extern inline void spin_lock_prefetch(const void *ptr)
{
__builtin_prefetch(ptr, 1, 3);
}
+#endif
+
#else
extern inline void prefetch(const void *ptr)
{
@@ -104,10 +112,13 @@ extern inline void prefetchw(const void
__asm__ ("ldq $31,%0" : : "m"(*(char *)ptr));
}
+#ifdef CONFIG_SMP
extern inline void spin_lock_prefetch(const void *ptr)
{
__asm__ ("ldq $31,%0" : : "m"(*(char *)ptr));
}
+#endif
+
#endif /* GCC 3.1 */
#endif /* __ASM_ALPHA_PROCESSOR_H */
Hi
With the patch from Ivan, the prefetch problem is gone.
Please add this patch to the mainline for 2.6.0 for alpha.
Regards
Tom
> We shouldn't prefetch the spinlocks on UP.
>
> Ivan.
>
> --- 2.6/include/asm-alpha/processor.h Sat Oct 25 22:44:54 2003
> +++ linux/include/asm-alpha/processor.h Tue Nov 18 01:48:39 2003
> @@ -78,6 +78,11 @@ unsigned long get_wchan(struct task_stru
> #define ARCH_HAS_PREFETCHW
> #define ARCH_HAS_SPINLOCK_PREFETCH
>
> +#ifndef CONFIG_SMP
> +/* Nothing to prefetch. */
> +#define spin_lock_prefetch(lock) do { } while (0)
> +#endif
> +
> #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)
> extern inline void prefetch(const void *ptr)
> {
> @@ -89,10 +94,13 @@ extern inline void prefetchw(const void
> __builtin_prefetch(ptr, 1, 3);
> }
>
> +#ifdef CONFIG_SMP
> extern inline void spin_lock_prefetch(const void *ptr)
> {
> __builtin_prefetch(ptr, 1, 3);
> }
> +#endif
> +
> #else
> extern inline void prefetch(const void *ptr)
> {
> @@ -104,10 +112,13 @@ extern inline void prefetchw(const void
> __asm__ ("ldq $31,%0" : : "m"(*(char *)ptr));
> }
>
> +#ifdef CONFIG_SMP
> extern inline void spin_lock_prefetch(const void *ptr)
> {
> __asm__ ("ldq $31,%0" : : "m"(*(char *)ptr));
> }
> +#endif
> +
> #endif /* GCC 3.1 */
>
> #endif /* __ASM_ALPHA_PROCESSOR_H */
--
Tom
LINUX user since kernel 0.99.x 1994.
RPM Alpha packages at http://alpha.steudten.com/packages
Want to know what S.u.S.E 1995 cdrom-set contains?
Hello
I test the new 2.6.1 kernel and run in the same problem as before.
The reason is, that the patch from Ivan isn?t there in the kernel
source tree.
Please add the patch to the mainline.
Tom
Thomas Steudten wrote:
> Hi
>
> With the patch from Ivan, the prefetch problem is gone.
> Please add this patch to the mainline for 2.6.0 for alpha.
>
> Regards
> Tom
>
>> We shouldn't prefetch the spinlocks on UP.
>>
>> Ivan.
>>
>> --- 2.6/include/asm-alpha/processor.h Sat Oct 25 22:44:54 2003
>> +++ linux/include/asm-alpha/processor.h Tue Nov 18 01:48:39 2003
>> @@ -78,6 +78,11 @@ unsigned long get_wchan(struct task_stru
>> #define ARCH_HAS_PREFETCHW
>> #define ARCH_HAS_SPINLOCK_PREFETCH
>>
>> +#ifndef CONFIG_SMP
>> +/* Nothing to prefetch. */
>> +#define spin_lock_prefetch(lock) do { } while (0)
>> +#endif
>> +
>> #if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 1)
>> extern inline void prefetch(const void *ptr) { @@ -89,10 +94,13 @@
>> extern inline void prefetchw(const void __builtin_prefetch(ptr,
>> 1, 3);
>> }
>>
>> +#ifdef CONFIG_SMP
>> extern inline void spin_lock_prefetch(const void *ptr) {
>> __builtin_prefetch(ptr, 1, 3);
>> }
>> +#endif
>> +
>> #else
>> extern inline void prefetch(const void *ptr) { @@ -104,10 +112,13
>> @@ extern inline void prefetchw(const void __asm__ ("ldq $31,%0"
>> : : "m"(*(char *)ptr)); }
>>
>> +#ifdef CONFIG_SMP
>> extern inline void spin_lock_prefetch(const void *ptr) {
>> __asm__ ("ldq $31,%0" : : "m"(*(char *)ptr)); }
>> +#endif
>> +
>> #endif /* GCC 3.1 */
>>
>> #endif /* __ASM_ALPHA_PROCESSOR_H */
>
>
--
Tom
LINUX user since kernel 0.99.x 1994.
RPM Alpha packages at http://alpha.steudten.com/packages
Want to know what S.u.S.E 1995 cdrom-set contains?
> I test the new 2.6.1 kernel and run in the same problem as
> before. The reason is, that the patch from Ivan isn?t there
> in the kernel source tree.
>
> Please add the patch to the mainline.
For me it works without patching anything. I still use my Digital Alpha AS
1000A for testing new kernels. I currently have no Compaq DS10 available,
else I would try this as well :-(
Best regards,
Oliver