From: Guo Ren <[email protected]>
Add the compatible string "thead,c900-plic" to the riscv plic
bindings to support allwinner d1 SOC which contains c906 core.
Signed-off-by: Guo Ren <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: Palmer Dabbelt <[email protected]>
Cc: Anup Patel <[email protected]>
Cc: Atish Patra <[email protected]>
---
Changes since V4:
- Update description in errata style
- Update enum suggested by Anup, Heiko, Samuel
Changes since V3:
- Rename "c9xx" to "c900"
- Add thead,c900-plic in the description section
---
.../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 08d5a57ce00f..272f29540135 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -35,6 +35,12 @@ description:
contains a specific memory layout, which is documented in chapter 8 of the
SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
+ The C9xx PLIC does not comply with the interrupt claim/completion process defined
+ by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
+ claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
+ completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
+ of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
+
maintainers:
- Sagar Kadam <[email protected]>
- Paul Walmsley <[email protected]>
@@ -46,7 +52,10 @@ properties:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
- - const: sifive,plic-1.0.0
+ - enmu:
+ - sifive,plic-1.0.0
+ - thead,c900-plic
+ - allwinner,sun20i-d1-plic
reg:
maxItems: 1
--
2.25.1
On Okt 16 2021, [email protected] wrote:
> + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
Missing close paren in both parenthetical remarks above.
Andreas.
--
Andreas Schwab, [email protected]
GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
"And now for something completely different."
On Sat, Oct 16, 2021 at 3:17 PM Andreas Schwab <[email protected]> wrote:
>
> On Okt 16 2021, [email protected] wrote:
>
> > + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
>
> Missing close paren in both parenthetical remarks above.
Opps, thx. I'll fix it.
>
> Andreas.
>
> --
> Andreas Schwab, [email protected]
> GPG Key fingerprint = 7578 EB47 D4E5 4D69 2510 2552 DF73 E780 A9DA AEC1
> "And now for something completely different."
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Hi Guo,
Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb [email protected]:
> From: Guo Ren <[email protected]>
>
> Add the compatible string "thead,c900-plic" to the riscv plic
> bindings to support allwinner d1 SOC which contains c906 core.
The compatible strings sound good now, but some things below
>
> Signed-off-by: Guo Ren <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Anup Patel <[email protected]>
> Cc: Atish Patra <[email protected]>
>
> ---
>
> Changes since V4:
> - Update description in errata style
> - Update enum suggested by Anup, Heiko, Samuel
>
> Changes since V3:
> - Rename "c9xx" to "c900"
> - Add thead,c900-plic in the description section
> ---
> .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
> 1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> index 08d5a57ce00f..272f29540135 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> @@ -35,6 +35,12 @@ description:
> contains a specific memory layout, which is documented in chapter 8 of the
> SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
>
> + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> +
> maintainers:
> - Sagar Kadam <[email protected]>
> - Paul Walmsley <[email protected]>
> @@ -46,7 +52,10 @@ properties:
> - enum:
> - sifive,fu540-c000-plic
> - canaan,k210-plic
> - - const: sifive,plic-1.0.0
> + - enmu:
^ spelling enum
> + - sifive,plic-1.0.0
> + - thead,c900-plic
> + - allwinner,sun20i-d1-plic
but in general I'd think that you want something like
compatible:
oneOf:
- items:
- enum:
- sifive,fu540-c000-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
- enum:
- allwinner,sun20i-d1-plic
- const: thead,c900-plic
Having only one item list would allow as valid combinations like
"sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
With the oneOf and separate lists we can make sure that such
"illegal" combinations get flagged by the dtbs_check
[the enum with the single allwinner entry already leaves
room for later addition to the c900-plic variant]
Heiko
On Sat, Oct 16, 2021 at 6:35 PM Heiko Stuebner <[email protected]> wrote:
>
> Hi Guo,
>
> Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb [email protected]:
> > From: Guo Ren <[email protected]>
> >
> > Add the compatible string "thead,c900-plic" to the riscv plic
> > bindings to support allwinner d1 SOC which contains c906 core.
>
> The compatible strings sound good now, but some things below
>
> >
> > Signed-off-by: Guo Ren <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Cc: Palmer Dabbelt <[email protected]>
> > Cc: Anup Patel <[email protected]>
> > Cc: Atish Patra <[email protected]>
> >
> > ---
> >
> > Changes since V4:
> > - Update description in errata style
> > - Update enum suggested by Anup, Heiko, Samuel
> >
> > Changes since V3:
> > - Rename "c9xx" to "c900"
> > - Add thead,c900-plic in the description section
> > ---
> > .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
> > 1 file changed, 10 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > index 08d5a57ce00f..272f29540135 100644
> > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > @@ -35,6 +35,12 @@ description:
> > contains a specific memory layout, which is documented in chapter 8 of the
> > SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> >
> > + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> > + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> > +
> > maintainers:
> > - Sagar Kadam <[email protected]>
> > - Paul Walmsley <[email protected]>
> > @@ -46,7 +52,10 @@ properties:
> > - enum:
> > - sifive,fu540-c000-plic
> > - canaan,k210-plic
> > - - const: sifive,plic-1.0.0
> > + - enmu:
>
> ^ spelling enum
>
> > + - sifive,plic-1.0.0
> > + - thead,c900-plic
> > + - allwinner,sun20i-d1-plic
>
> but in general I'd think that you want something like
>
> compatible:
> oneOf:
> - items:
> - enum:
> - sifive,fu540-c000-plic
> - canaan,k210-plic
> - const: sifive,plic-1.0.0
> - items:
> - enum:
> - allwinner,sun20i-d1-plic
> - const: thead,c900-plic
>
> Having only one item list would allow as valid combinations like
> "sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
>
> With the oneOf and separate lists we can make sure that such
> "illegal" combinations get flagged by the dtbs_check
>
> [the enum with the single allwinner entry already leaves
> room for later addition to the c900-plic variant]
Thx, I'll fix it in the next version.
another question: Is the allwinner_sun20i_d1_plic needed to IRQCHIP_DECLARE?
+IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
+IRQCHIP_DECLARE(allwinner_sun20i_d1_plic, "allwinner,sun20i-d1-plic",
thead_c900_plic_init);
>
> Heiko
>
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
Am Samstag, 16. Oktober 2021, 14:56:51 CEST schrieb Guo Ren:
> On Sat, Oct 16, 2021 at 6:35 PM Heiko Stuebner <[email protected]> wrote:
> >
> > Hi Guo,
> >
> > Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb [email protected]:
> > > From: Guo Ren <[email protected]>
> > >
> > > Add the compatible string "thead,c900-plic" to the riscv plic
> > > bindings to support allwinner d1 SOC which contains c906 core.
> >
> > The compatible strings sound good now, but some things below
> >
> > >
> > > Signed-off-by: Guo Ren <[email protected]>
> > > Cc: Rob Herring <[email protected]>
> > > Cc: Palmer Dabbelt <[email protected]>
> > > Cc: Anup Patel <[email protected]>
> > > Cc: Atish Patra <[email protected]>
> > >
> > > ---
> > >
> > > Changes since V4:
> > > - Update description in errata style
> > > - Update enum suggested by Anup, Heiko, Samuel
> > >
> > > Changes since V3:
> > > - Rename "c9xx" to "c900"
> > > - Add thead,c900-plic in the description section
> > > ---
> > > .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
> > > 1 file changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > index 08d5a57ce00f..272f29540135 100644
> > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > @@ -35,6 +35,12 @@ description:
> > > contains a specific memory layout, which is documented in chapter 8 of the
> > > SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> > >
> > > + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > > + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > > + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > > + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> > > + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> > > +
> > > maintainers:
> > > - Sagar Kadam <[email protected]>
> > > - Paul Walmsley <[email protected]>
> > > @@ -46,7 +52,10 @@ properties:
> > > - enum:
> > > - sifive,fu540-c000-plic
> > > - canaan,k210-plic
> > > - - const: sifive,plic-1.0.0
> > > + - enmu:
> >
> > ^ spelling enum
> >
> > > + - sifive,plic-1.0.0
> > > + - thead,c900-plic
> > > + - allwinner,sun20i-d1-plic
> >
> > but in general I'd think that you want something like
> >
> > compatible:
> > oneOf:
> > - items:
> > - enum:
> > - sifive,fu540-c000-plic
> > - canaan,k210-plic
> > - const: sifive,plic-1.0.0
> > - items:
> > - enum:
> > - allwinner,sun20i-d1-plic
> > - const: thead,c900-plic
> >
> > Having only one item list would allow as valid combinations like
> > "sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
> >
> > With the oneOf and separate lists we can make sure that such
> > "illegal" combinations get flagged by the dtbs_check
> >
> > [the enum with the single allwinner entry already leaves
> > room for later addition to the c900-plic variant]
> Thx, I'll fix it in the next version.
>
> another question: Is the allwinner_sun20i_d1_plic needed to IRQCHIP_DECLARE?
>
> +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
> +IRQCHIP_DECLARE(allwinner_sun20i_d1_plic, "allwinner,sun20i-d1-plic",
> thead_c900_plic_init);
Doing
IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
should be enough for now.
Compatible-parsing happens from left to right, from most-specific to
most-generic. So having the allwinner-d1 compatible in there is sort of a
safeguard.
If at some _later point in time_ , some specific new quirk of the D1
implementation comes to light, we can _then_ just add a
IRQCHIP_DECLARE(allwinner_d1_plic, "allwinner,sun20i-d1-plic", allwinner_d1_plic_init);
Devicetrees should be stable and newer kernels should work with old
devicetrees, so having the soc-specific compatible in there just makes it
future proof :-)
Heiko
On Fri, Oct 15, 2021 at 10:22 PM <[email protected]> wrote:
>
> From: Guo Ren <[email protected]>
>
> Add the compatible string "thead,c900-plic" to the riscv plic
> bindings to support allwinner d1 SOC which contains c906 core.
>
> Signed-off-by: Guo Ren <[email protected]>
> Cc: Rob Herring <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Anup Patel <[email protected]>
> Cc: Atish Patra <[email protected]>
Please send to the DT list so that checks run and it's in my review
queue (IOW, use get_maintainers.pl). And run 'make dt_binding_check'
so reviewers don't have to find your typos and other errors for you.
Rob
On Mon, Oct 18, 2021 at 8:02 PM Rob Herring <[email protected]> wrote:
>
> On Fri, Oct 15, 2021 at 10:22 PM <[email protected]> wrote:
> >
> > From: Guo Ren <[email protected]>
> >
> > Add the compatible string "thead,c900-plic" to the riscv plic
> > bindings to support allwinner d1 SOC which contains c906 core.
> >
> > Signed-off-by: Guo Ren <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > Cc: Palmer Dabbelt <[email protected]>
> > Cc: Anup Patel <[email protected]>
> > Cc: Atish Patra <[email protected]>
>
> Please send to the DT list so that checks run and it's in my review
> queue (IOW, use get_maintainers.pl). And run 'make dt_binding_check'
> so reviewers don't have to find your typos and other errors for you.
Thx for the tip, I would follow that in next version.
>
> Rob
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Sun, Oct 17, 2021 at 12:31 AM Heiko Stuebner <[email protected]> wrote:
>
> Am Samstag, 16. Oktober 2021, 14:56:51 CEST schrieb Guo Ren:
> > On Sat, Oct 16, 2021 at 6:35 PM Heiko Stuebner <[email protected]> wrote:
> > >
> > > Hi Guo,
> > >
> > > Am Samstag, 16. Oktober 2021, 05:21:59 CEST schrieb [email protected]:
> > > > From: Guo Ren <[email protected]>
> > > >
> > > > Add the compatible string "thead,c900-plic" to the riscv plic
> > > > bindings to support allwinner d1 SOC which contains c906 core.
> > >
> > > The compatible strings sound good now, but some things below
> > >
> > > >
> > > > Signed-off-by: Guo Ren <[email protected]>
> > > > Cc: Rob Herring <[email protected]>
> > > > Cc: Palmer Dabbelt <[email protected]>
> > > > Cc: Anup Patel <[email protected]>
> > > > Cc: Atish Patra <[email protected]>
> > > >
> > > > ---
> > > >
> > > > Changes since V4:
> > > > - Update description in errata style
> > > > - Update enum suggested by Anup, Heiko, Samuel
> > > >
> > > > Changes since V3:
> > > > - Rename "c9xx" to "c900"
> > > > - Add thead,c900-plic in the description section
> > > > ---
> > > > .../interrupt-controller/sifive,plic-1.0.0.yaml | 11 ++++++++++-
> > > > 1 file changed, 10 insertions(+), 1 deletion(-)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > index 08d5a57ce00f..272f29540135 100644
> > > > --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
> > > > @@ -35,6 +35,12 @@ description:
> > > > contains a specific memory layout, which is documented in chapter 8 of the
> > > > SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
> > > >
> > > > + The C9xx PLIC does not comply with the interrupt claim/completion process defined
> > > > + by the RISC-V PLIC specification because C9xx PLIC will mask an IRQ when it is
> > > > + claimed by PLIC driver (i.e. readl(claim) and the IRQ will be unmasked upon
> > > > + completion by PLIC driver (i.e. writel(claim). This behaviour breaks the handling
> > > > + of IRQS_ONESHOT by the generic handle_fasteoi_irq() used in the PLIC driver.
> > > > +
> > > > maintainers:
> > > > - Sagar Kadam <[email protected]>
> > > > - Paul Walmsley <[email protected]>
> > > > @@ -46,7 +52,10 @@ properties:
> > > > - enum:
> > > > - sifive,fu540-c000-plic
> > > > - canaan,k210-plic
> > > > - - const: sifive,plic-1.0.0
> > > > + - enmu:
> > >
> > > ^ spelling enum
> > >
> > > > + - sifive,plic-1.0.0
> > > > + - thead,c900-plic
> > > > + - allwinner,sun20i-d1-plic
> > >
> > > but in general I'd think that you want something like
> > >
> > > compatible:
> > > oneOf:
> > > - items:
> > > - enum:
> > > - sifive,fu540-c000-plic
> > > - canaan,k210-plic
> > > - const: sifive,plic-1.0.0
> > > - items:
> > > - enum:
> > > - allwinner,sun20i-d1-plic
> > > - const: thead,c900-plic
> > >
> > > Having only one item list would allow as valid combinations like
> > > "sifive,fu540-c000-plic", "thead,c900-plic" when checking the schema.
> > >
> > > With the oneOf and separate lists we can make sure that such
> > > "illegal" combinations get flagged by the dtbs_check
> > >
> > > [the enum with the single allwinner entry already leaves
> > > room for later addition to the c900-plic variant]
> > Thx, I'll fix it in the next version.
> >
> > another question: Is the allwinner_sun20i_d1_plic needed to IRQCHIP_DECLARE?
> >
> > +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
> > +IRQCHIP_DECLARE(allwinner_sun20i_d1_plic, "allwinner,sun20i-d1-plic",
> > thead_c900_plic_init);
>
> Doing
> IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", thead_c900_plic_init);
> should be enough for now.
>
> Compatible-parsing happens from left to right, from most-specific to
> most-generic. So having the allwinner-d1 compatible in there is sort of a
> safeguard.
>
> If at some _later point in time_ , some specific new quirk of the D1
> implementation comes to light, we can _then_ just add a
> IRQCHIP_DECLARE(allwinner_d1_plic, "allwinner,sun20i-d1-plic", allwinner_d1_plic_init);
>
> Devicetrees should be stable and newer kernels should work with old
> devicetrees, so having the soc-specific compatible in there just makes it
> future proof :-)
Nice tip, thx.
>
>
> Heiko
>
>
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/