This patchset add support for GPIO interrupt controller of Meson-S4 SoC
Which has somethings different with current other meson chips. To
support the new chips, current gpio irqchip driver need to rework as
below:
1. support more than 8 gpio irq line.
2. add a set trigger type callback function.
With above work, add support for S4 gpio irqchip
Qianggui Song (4):
dt-bindings: interrupt-controller: New binding for Meson-S4 SoCs
irqchip/meson-gpio: support more than 8 channels gpio irq line
irqchip/meson-gpio: add select trigger type callback
irqchip/meson-gpio: Add support for meson s4 SoCs
.../amlogic,meson-gpio-intc.txt | 1 +
drivers/irqchip/irq-meson-gpio.c | 97 ++++++++++++++++---
2 files changed, 86 insertions(+), 12 deletions(-)
--
2.34.1
Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
Signed-off-by: Qianggui Song <[email protected]>
---
.../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
index 23b18b92c558..9300736bf1ed 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
@@ -18,6 +18,7 @@ Required properties:
"amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
"amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
"amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
+ "amlogic,meson-a1-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
- reg : Specifies base physical address and size of the registers.
- interrupt-controller : Identifies the node as an interrupt controller.
- #interrupt-cells : Specifies the number of cells needed to encode an
--
2.34.1
Current meson gpio irqchip driver only support 8 channels for gpio irq
line, later chips may have more then 8 channels, so need to modify code
to support more.
Signed-off-by: Qianggui Song <[email protected]>
---
drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
1 file changed, 24 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index d90ff0b92480..6a7b4fb13452 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -16,7 +16,6 @@
#include <linux/of.h>
#include <linux/of_address.h>
-#define NUM_CHANNEL 8
#define MAX_INPUT_MUX 256
#define REG_EDGE_POL 0x00
@@ -60,6 +59,7 @@ struct irq_ctl_ops {
struct meson_gpio_irq_params {
unsigned int nr_hwirq;
+ unsigned int channel_num;
bool support_edge_both;
unsigned int edge_both_offset;
unsigned int edge_single_offset;
@@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 0, \
.pol_low_offset = 16, \
.pin_sel_mask = 0xff, \
+ .channel_num = 8, \
#define INIT_MESON_A1_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
@@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
.edge_single_offset = 8, \
.pol_low_offset = 0, \
.pin_sel_mask = 0x7f, \
+ .channel_num = 8, \
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
@@ -136,8 +138,9 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
struct meson_gpio_irq_controller {
const struct meson_gpio_irq_params *params;
void __iomem *base;
- u32 channel_irqs[NUM_CHANNEL];
- DECLARE_BITMAP(channel_map, NUM_CHANNEL);
+ u32 *channel_irqs;
+ unsigned long *channel_map;
+ u8 channel_num;
spinlock_t lock;
};
@@ -207,8 +210,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
spin_lock_irqsave(&ctl->lock, flags);
/* Find a free channel */
- idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
- if (idx >= NUM_CHANNEL) {
+ idx = find_first_zero_bit(ctl->channel_map, ctl->channel_num);
+ if (idx >= ctl->channel_num) {
spin_unlock_irqrestore(&ctl->lock, flags);
pr_err("No channel available\n");
return -ENOSPC;
@@ -447,13 +450,25 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
ctl->params = match->data;
+ ctl->channel_num = ctl->params->channel_num;
+ ctl->channel_irqs = kcalloc(ctl->channel_num,
+ sizeof(*ctl->channel_irqs), GFP_KERNEL);
+ if (!ctl->channel_irqs)
+ return -ENOMEM;
+
+ ctl->channel_map = bitmap_zalloc(ctl->params->channel_num, GFP_KERNEL);
+ if (!ctl->channel_map) {
+ kfree(ctl->channel_irqs);
+ return -ENOMEM;
+ }
+
ret = of_property_read_variable_u32_array(node,
"amlogic,channel-interrupts",
ctl->channel_irqs,
- NUM_CHANNEL,
- NUM_CHANNEL);
+ ctl->channel_num,
+ ctl->channel_num);
if (ret < 0) {
- pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
+ pr_err("can't get %d channel interrupts\n", ctl->channel_num);
return ret;
}
@@ -507,7 +522,7 @@ static int meson_gpio_irq_of_init(struct device_node *node, struct device_node *
}
pr_info("%d to %d gpio interrupt mux initialized\n",
- ctl->params->nr_hwirq, NUM_CHANNEL);
+ ctl->params->nr_hwirq, ctl->channel_num);
return 0;
--
2.34.1
Due to some chips may use different registers and offset, provide
a set trigger type call back.
Signed-off-by: Qianggui Song <[email protected]>
---
drivers/irqchip/irq-meson-gpio.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 6a7b4fb13452..98419428fcbd 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -55,6 +55,8 @@ struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
+ unsigned int (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
};
struct meson_gpio_irq_params {
@@ -68,16 +70,17 @@ struct meson_gpio_irq_params {
struct irq_ctl_ops ops;
};
-#define INIT_MESON_COMMON(irqs, init, sel) \
+#define INIT_MESON_COMMON(irqs, init, sel, type) \
.nr_hwirq = irqs, \
.ops = { \
.gpio_irq_init = init, \
.gpio_irq_sel_pin = sel, \
+ .gpio_irq_sel_type = type, \
},
#define INIT_MESON8_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
- meson8_gpio_irq_sel_pin) \
+ meson8_gpio_irq_sel_pin, NULL) \
.edge_single_offset = 0, \
.pol_low_offset = 16, \
.pin_sel_mask = 0xff, \
@@ -85,7 +88,7 @@ struct meson_gpio_irq_params {
#define INIT_MESON_A1_COMMON_DATA(irqs) \
INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
- meson_a1_gpio_irq_sel_pin) \
+ meson_a1_gpio_irq_sel_pin, NULL) \
.support_edge_both = true, \
.edge_both_offset = 16, \
.edge_single_offset = 8, \
@@ -279,6 +282,10 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
*/
type &= IRQ_TYPE_SENSE_MASK;
+ /* Some controllers may have different calculation method*/
+ if (params->ops.gpio_irq_sel_type)
+ return params->ops.gpio_irq_sel_type(ctl, idx, type);
+
/*
* New controller support EDGE_BOTH trigger. This setting takes
* precedence over the other edge/polarity settings
--
2.34.1
The meson s4 SoCs support 12 gpio irq lines compared with previous
serial chips and have something different, details are as below.
IRQ Number:
- 80:68 13 pins on bank Z
- 67:48 20 pins on bank X
- 47:36 12 pins on bank H
- 35:24 12 pins on bank D
- 23:22 2 pins on bank E
- 21:14 8 pins on bank C
- 13:0 13 pins on bank B
- PADCTRL_GPIO_IRQ_CTRL0
bit[31]: enable/disable the whole irq lines
bit[12-23]: single edge trigger
bit[0-11]: poll trigger
- PADCTRL_GPIO_IRQ_CTRL[X]
- bit[0-16]: 7 bits to chooge gpio source for irq line 2*[X] - 2
- bit[16-22]:7 bits to chooge gpio source for irq line 2*[X] - 1
where X = 1-6
- PADCTRL_GPIO_IRQ_CTRL[7]
bit[0-11]: both edge trigger
Signed-off-by: Qianggui Song <[email protected]>
---
drivers/irqchip/irq-meson-gpio.c | 51 ++++++++++++++++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
index 98419428fcbd..c5d20a866c37 100644
--- a/drivers/irqchip/irq-meson-gpio.c
+++ b/drivers/irqchip/irq-meson-gpio.c
@@ -42,6 +42,11 @@
#define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
#define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
+/* use for s4 chips */
+#define REG_EDGE_POL_S4 0x1c
+#define REG_EDGE_POL_MASK_S4(x) \
+ ({typeof(x) _x = (x); BIT(_x) | BIT(12 + (_x)); })
+
struct meson_gpio_irq_controller;
static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel, unsigned long hwirq);
@@ -50,6 +55,9 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
unsigned int channel,
unsigned long hwirq);
static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
+static unsigned int
+meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, u32 val);
struct irq_ctl_ops {
void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
@@ -96,6 +104,17 @@ struct meson_gpio_irq_params {
.pin_sel_mask = 0x7f, \
.channel_num = 8, \
+#define INIT_MESON_S4_COMMON_DATA(irqs) \
+ INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
+ meson_a1_gpio_irq_sel_pin, \
+ meson_s4_gpio_irq_sel_type) \
+ .support_edge_both = true, \
+ .edge_both_offset = 0, \
+ .edge_single_offset = 12, \
+ .pol_low_offset = 0, \
+ .pin_sel_mask = 0xff, \
+ .channel_num = 12, \
+
static const struct meson_gpio_irq_params meson8_params = {
INIT_MESON8_COMMON_DATA(134)
};
@@ -126,6 +145,10 @@ static const struct meson_gpio_irq_params a1_params = {
INIT_MESON_A1_COMMON_DATA(62)
};
+static const struct meson_gpio_irq_params s4_params = {
+ INIT_MESON_S4_COMMON_DATA(82)
+};
+
static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
@@ -135,6 +158,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
+ { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
{ }
};
@@ -202,6 +226,33 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
}
+static unsigned int
+meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
+ unsigned int idx, unsigned int type)
+{
+ unsigned int val = 0;
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(0 + (idx)), 0);
+
+ if (type == IRQ_TYPE_EDGE_BOTH) {
+ val |= BIT(ctl->params->edge_both_offset + (idx));
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
+ BIT(ctl->params->edge_both_offset + (idx)), val);
+ return 0;
+ }
+
+ if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->pol_low_offset + (idx));
+
+ if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
+ val |= BIT(ctl->params->edge_single_offset + (idx));
+
+ meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
+ REG_EDGE_POL_MASK_S4(idx), val);
+
+ return 0;
+};
+
static int
meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
unsigned long hwirq,
--
2.34.1
On Sat, 08 Jan 2022 08:42:16 +0000,
Qianggui Song <[email protected]> wrote:
>
> Current meson gpio irqchip driver only support 8 channels for gpio irq
> line, later chips may have more then 8 channels, so need to modify code
> to support more.
>
> Signed-off-by: Qianggui Song <[email protected]>
> ---
> drivers/irqchip/irq-meson-gpio.c | 33 +++++++++++++++++++++++---------
> 1 file changed, 24 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index d90ff0b92480..6a7b4fb13452 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -16,7 +16,6 @@
> #include <linux/of.h>
> #include <linux/of_address.h>
>
> -#define NUM_CHANNEL 8
> #define MAX_INPUT_MUX 256
>
> #define REG_EDGE_POL 0x00
> @@ -60,6 +59,7 @@ struct irq_ctl_ops {
>
> struct meson_gpio_irq_params {
> unsigned int nr_hwirq;
> + unsigned int channel_num;
For consistency, please name this nr_channels.
> bool support_edge_both;
> unsigned int edge_both_offset;
> unsigned int edge_single_offset;
> @@ -81,6 +81,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> + .channel_num = 8, \
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> @@ -90,6 +91,7 @@ struct meson_gpio_irq_params {
> .edge_single_offset = 8, \
> .pol_low_offset = 0, \
> .pin_sel_mask = 0x7f, \
> + .channel_num = 8, \
>
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> @@ -136,8 +138,9 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> struct meson_gpio_irq_controller {
> const struct meson_gpio_irq_params *params;
> void __iomem *base;
> - u32 channel_irqs[NUM_CHANNEL];
> - DECLARE_BITMAP(channel_map, NUM_CHANNEL);
> + u32 *channel_irqs;
> + unsigned long *channel_map;
> + u8 channel_num;
Same thing. Though this is completely superfluous, see below.
> spinlock_t lock;
> };
>
> @@ -207,8 +210,8 @@ meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
> spin_lock_irqsave(&ctl->lock, flags);
>
> /* Find a free channel */
> - idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
> - if (idx >= NUM_CHANNEL) {
> + idx = find_first_zero_bit(ctl->channel_map, ctl->channel_num);
> + if (idx >= ctl->channel_num) {
> spin_unlock_irqrestore(&ctl->lock, flags);
> pr_err("No channel available\n");
> return -ENOSPC;
> @@ -447,13 +450,25 @@ static int meson_gpio_irq_parse_dt(struct device_node *node, struct meson_gpio_i
>
> ctl->params = match->data;
>
> + ctl->channel_num = ctl->params->channel_num;
Since you already have a pointer to params, why do you need to
duplicate this information?
> + ctl->channel_irqs = kcalloc(ctl->channel_num,
> + sizeof(*ctl->channel_irqs), GFP_KERNEL);
> + if (!ctl->channel_irqs)
> + return -ENOMEM;
> +
> + ctl->channel_map = bitmap_zalloc(ctl->params->channel_num, GFP_KERNEL);
> + if (!ctl->channel_map) {
> + kfree(ctl->channel_irqs);
> + return -ENOMEM;
> + }
> +
> ret = of_property_read_variable_u32_array(node,
> "amlogic,channel-interrupts",
> ctl->channel_irqs,
> - NUM_CHANNEL,
> - NUM_CHANNEL);
> + ctl->channel_num,
> + ctl->channel_num);
> if (ret < 0) {
> - pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
> + pr_err("can't get %d channel interrupts\n", ctl->channel_num);
> return ret;
You are now leaking the bitmap and channel_map allocations.
M.
--
Without deviation from the norm, progress is not possible.
On Sat, 08 Jan 2022 08:42:17 +0000,
Qianggui Song <[email protected]> wrote:
>
> Due to some chips may use different registers and offset, provide
> a set trigger type call back.
>
> Signed-off-by: Qianggui Song <[email protected]>
> ---
> drivers/irqchip/irq-meson-gpio.c | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index 6a7b4fb13452..98419428fcbd 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -55,6 +55,8 @@ struct irq_ctl_ops {
> void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
> unsigned int channel, unsigned long hwirq);
> void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
> + unsigned int (*gpio_irq_sel_type)(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, u32 val);
> };
>
> struct meson_gpio_irq_params {
> @@ -68,16 +70,17 @@ struct meson_gpio_irq_params {
> struct irq_ctl_ops ops;
> };
>
> -#define INIT_MESON_COMMON(irqs, init, sel) \
> +#define INIT_MESON_COMMON(irqs, init, sel, type) \
> .nr_hwirq = irqs, \
> .ops = { \
> .gpio_irq_init = init, \
> .gpio_irq_sel_pin = sel, \
> + .gpio_irq_sel_type = type, \
> },
>
> #define INIT_MESON8_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy, \
> - meson8_gpio_irq_sel_pin) \
> + meson8_gpio_irq_sel_pin, NULL) \
> .edge_single_offset = 0, \
> .pol_low_offset = 16, \
> .pin_sel_mask = 0xff, \
> @@ -85,7 +88,7 @@ struct meson_gpio_irq_params {
>
> #define INIT_MESON_A1_COMMON_DATA(irqs) \
> INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> - meson_a1_gpio_irq_sel_pin) \
> + meson_a1_gpio_irq_sel_pin, NULL) \
> .support_edge_both = true, \
> .edge_both_offset = 16, \
> .edge_single_offset = 8, \
> @@ -279,6 +282,10 @@ static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
> */
> type &= IRQ_TYPE_SENSE_MASK;
>
> + /* Some controllers may have different calculation method*/
> + if (params->ops.gpio_irq_sel_type)
> + return params->ops.gpio_irq_sel_type(ctl, idx, type);
> +
No. If you are going to indirect these things, indirect them for all
implementations and keep the code clean.
M.
--
Without deviation from the norm, progress is not possible.
On Sat, 08 Jan 2022 08:42:18 +0000,
Qianggui Song <[email protected]> wrote:
>
> The meson s4 SoCs support 12 gpio irq lines compared with previous
> serial chips and have something different, details are as below.
>
> IRQ Number:
> - 80:68 13 pins on bank Z
> - 67:48 20 pins on bank X
> - 47:36 12 pins on bank H
> - 35:24 12 pins on bank D
> - 23:22 2 pins on bank E
> - 21:14 8 pins on bank C
> - 13:0 13 pins on bank B
>
> - PADCTRL_GPIO_IRQ_CTRL0
> bit[31]: enable/disable the whole irq lines
s/the whole/all the/
> bit[12-23]: single edge trigger
> bit[0-11]: poll trigger
>
> - PADCTRL_GPIO_IRQ_CTRL[X]
> - bit[0-16]: 7 bits to chooge gpio source for irq line 2*[X] - 2
choose?
> - bit[16-22]:7 bits to chooge gpio source for irq line 2*[X] - 1
> where X = 1-6
>
> - PADCTRL_GPIO_IRQ_CTRL[7]
> bit[0-11]: both edge trigger
This information would fit better in the code than in the commit
message.
>
> Signed-off-by: Qianggui Song <[email protected]>
> ---
> drivers/irqchip/irq-meson-gpio.c | 51 ++++++++++++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
>
> diff --git a/drivers/irqchip/irq-meson-gpio.c b/drivers/irqchip/irq-meson-gpio.c
> index 98419428fcbd..c5d20a866c37 100644
> --- a/drivers/irqchip/irq-meson-gpio.c
> +++ b/drivers/irqchip/irq-meson-gpio.c
> @@ -42,6 +42,11 @@
> #define REG_PIN_SEL_SHIFT(x) (((x) % 4) * 8)
> #define REG_FILTER_SEL_SHIFT(x) ((x) * 4)
>
> +/* use for s4 chips */
s/use/Used/
> +#define REG_EDGE_POL_S4 0x1c
> +#define REG_EDGE_POL_MASK_S4(x) \
> + ({typeof(x) _x = (x); BIT(_x) | BIT(12 + (_x)); })
Why on Earth should this macro handle multiple types?
> +
> struct meson_gpio_irq_controller;
> static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
> unsigned int channel, unsigned long hwirq);
> @@ -50,6 +55,9 @@ static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
> unsigned int channel,
> unsigned long hwirq);
> static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
> +static unsigned int
> +meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, u32 val);
>
> struct irq_ctl_ops {
> void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
> @@ -96,6 +104,17 @@ struct meson_gpio_irq_params {
> .pin_sel_mask = 0x7f, \
> .channel_num = 8, \
>
> +#define INIT_MESON_S4_COMMON_DATA(irqs) \
> + INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init, \
> + meson_a1_gpio_irq_sel_pin, \
> + meson_s4_gpio_irq_sel_type) \
> + .support_edge_both = true, \
> + .edge_both_offset = 0, \
> + .edge_single_offset = 12, \
> + .pol_low_offset = 0, \
> + .pin_sel_mask = 0xff, \
> + .channel_num = 12, \
> +
> static const struct meson_gpio_irq_params meson8_params = {
> INIT_MESON8_COMMON_DATA(134)
> };
> @@ -126,6 +145,10 @@ static const struct meson_gpio_irq_params a1_params = {
> INIT_MESON_A1_COMMON_DATA(62)
> };
>
> +static const struct meson_gpio_irq_params s4_params = {
> + INIT_MESON_S4_COMMON_DATA(82)
> +};
> +
> static const struct of_device_id meson_irq_gpio_matches[] = {
> { .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
> { .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
> @@ -135,6 +158,7 @@ static const struct of_device_id meson_irq_gpio_matches[] = {
> { .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
> { .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
> { .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
> + { .compatible = "amlogic,meson-s4-gpio-intc", .data = &s4_params },
> { }
> };
>
> @@ -202,6 +226,33 @@ static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
> meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
> }
>
> +static unsigned int
> +meson_s4_gpio_irq_sel_type(struct meson_gpio_irq_controller *ctl,
> + unsigned int idx, unsigned int type)
An 'unsigned int' return type, directly returned by a caller that
has 'int' as its return type. What could possibly go wrong?
> +{
> + unsigned int val = 0;
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4, BIT(0 + (idx)), 0);
Drop the 0 + as well as the useless bracketing all over this function.
> +
> + if (type == IRQ_TYPE_EDGE_BOTH) {
> + val |= BIT(ctl->params->edge_both_offset + (idx));
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL_S4,
> + BIT(ctl->params->edge_both_offset + (idx)), val);
> + return 0;
> + }
> +
> + if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->pol_low_offset + (idx));
> +
> + if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
> + val |= BIT(ctl->params->edge_single_offset + (idx));
> +
> + meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
> + REG_EDGE_POL_MASK_S4(idx), val);
> +
> + return 0;
> +};
> +
> static int
> meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
> unsigned long hwirq,
M.
--
Without deviation from the norm, progress is not possible.
> On 8 Jan 2022, at 12:42 pm, Qianggui Song <[email protected]> wrote:
>
> Update dt-binding document for GPIO interrupt controller of Meson-S4 SoCs
>
> Signed-off-by: Qianggui Song <[email protected]>
> ---
> .../bindings/interrupt-controller/amlogic,meson-gpio-intc.txt | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
> index 23b18b92c558..9300736bf1ed 100644
> --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
> +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.txt
> @@ -18,6 +18,7 @@ Required properties:
> "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
> "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
> "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
> + "amlogic,meson-a1-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
^ should be "amlogic,meson-s4-gpio-intc” ?
Christian
> - reg : Specifies base physical address and size of the registers.
> - interrupt-controller : Identifies the node as an interrupt controller.
> - #interrupt-cells : Specifies the number of cells needed to encode an
> --
> 2.34.1
>
>
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