Hello all,
Same story as for AM64x[0], AM62x[1], and J7x[2].
Last round for AM65x, but there are some boards that I do not have
(Simatic IOT2050), so testing very welcome!
Thanks,
Andrew
[0] https://www.spinics.net/lists/arm-kernel/msg1018532.html
[1] https://www.spinics.net/lists/arm-kernel/msg1018864.html
[2] https://www.spinics.net/lists/arm-kernel/msg1019544.html
Andrew Davis (11):
arm64: dts: ti: k3-am65: Enable UART nodes at the board level
arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level
arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
.../boot/dts/ti/k3-am65-iot2050-common.dtsi | 101 ++--------------
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 41 +++++++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 18 ++-
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 +
.../ti/k3-am6528-iot2050-basic-common.dtsi | 1 +
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 113 ++++--------------
.../ti/k3-am6548-iot2050-advanced-common.dtsi | 4 -
7 files changed, 94 insertions(+), 186 deletions(-)
--
2.37.3
MDIO nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with a pinmux.
As the attached PHY is only known about at the board integration level,
these nodes should only be enabled when provided with this information.
Disable the MDIO nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ------------
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 13 +------------
4 files changed, 5 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 56562081a8e52..35af8798f208e 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -732,18 +732,6 @@ &mcu_r5fss0_core1 {
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
-
&mcasp0 {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index fbb631c7664d2..9cdde6e25e7de 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -1078,6 +1078,7 @@ icssg0_mdio: mdio@32400 {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1219,6 +1220,7 @@ icssg1_mdio: mdio@32400 {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
@@ -1360,6 +1362,7 @@ icssg2_mdio: mdio@32400 {
#address-cells = <1>;
#size-cells = <0>;
bus_freq = <1000000>;
+ status = "disabled";
};
};
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 7a11501bad0bc..22f30174621e2 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -278,6 +278,7 @@ davinci_mdio: mdio@f00 {
clocks = <&k3_clks 5 10>;
clock-names = "fck";
bus_freq = <1000000>;
+ status = "disabled";
};
cpts@3d000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 0c63c24941061..beac2c563e831 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -533,6 +533,7 @@ &mcu_cpsw {
};
&davinci_mdio {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_mdio_pins_default>;
@@ -563,15 +564,3 @@ &mcasp2 {
&dss {
status = "disabled";
};
-
-&icssg0_mdio {
- status = "disabled";
-};
-
-&icssg1_mdio {
- status = "disabled";
-};
-
-&icssg2_mdio {
- status = "disabled";
-};
--
2.37.3
EPWM nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the EPWM nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 74fd807d47396..49287f8493aea 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -886,6 +886,7 @@ ehrpwm0: pwm@3000000 {
power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm1: pwm@3010000 {
@@ -895,6 +896,7 @@ ehrpwm1: pwm@3010000 {
power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm2: pwm@3020000 {
@@ -904,6 +906,7 @@ ehrpwm2: pwm@3020000 {
power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm3: pwm@3030000 {
@@ -913,6 +916,7 @@ ehrpwm3: pwm@3030000 {
power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm4: pwm@3040000 {
@@ -922,6 +926,7 @@ ehrpwm4: pwm@3040000 {
power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
ehrpwm5: pwm@3050000 {
@@ -931,6 +936,7 @@ ehrpwm5: pwm@3050000 {
power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
clock-names = "tbclk", "fck";
+ status = "disabled";
};
icssg0: icssg@b000000 {
--
2.37.3
Mailbox nodes defined in the top-level AM65x SoC dtsi files are incomplete
and may not be functional unless they are extended with a chosen interrupt
and connection to a remote processor.
As the remote processors depend on memory nodes which are only known at
the board integration level, these nodes should only be enabled when
provided with the above information.
Disable the Mailbox nodes in the dtsi files and only enable the ones that
are actually used on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
.../boot/dts/ti/k3-am65-iot2050-common.dtsi | 42 +------------------
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 12 ++++++
.../arm64/boot/dts/ti/k3-am654-base-board.dts | 42 +------------------
3 files changed, 16 insertions(+), 80 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index dd7c6aee8c613..c6c79dde79c52 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -644,6 +644,7 @@ &pcie1_rc {
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -653,6 +654,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -661,46 +663,6 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 9081c791a3123..3dc624a379c5f 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -514,6 +514,7 @@ mailbox0_cluster0: mailbox@31f80000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster1: mailbox@31f81000 {
@@ -523,6 +524,7 @@ mailbox0_cluster1: mailbox@31f81000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster2: mailbox@31f82000 {
@@ -532,6 +534,7 @@ mailbox0_cluster2: mailbox@31f82000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster3: mailbox@31f83000 {
@@ -541,6 +544,7 @@ mailbox0_cluster3: mailbox@31f83000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster4: mailbox@31f84000 {
@@ -550,6 +554,7 @@ mailbox0_cluster4: mailbox@31f84000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster5: mailbox@31f85000 {
@@ -559,6 +564,7 @@ mailbox0_cluster5: mailbox@31f85000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster6: mailbox@31f86000 {
@@ -568,6 +574,7 @@ mailbox0_cluster6: mailbox@31f86000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster7: mailbox@31f87000 {
@@ -577,6 +584,7 @@ mailbox0_cluster7: mailbox@31f87000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster8: mailbox@31f88000 {
@@ -586,6 +594,7 @@ mailbox0_cluster8: mailbox@31f88000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster9: mailbox@31f89000 {
@@ -595,6 +604,7 @@ mailbox0_cluster9: mailbox@31f89000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster10: mailbox@31f8a000 {
@@ -604,6 +614,7 @@ mailbox0_cluster10: mailbox@31f8a000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
mailbox0_cluster11: mailbox@31f8b000 {
@@ -613,6 +624,7 @@ mailbox0_cluster11: mailbox@31f8b000 {
ti,mbox-num-users = <4>;
ti,mbox-num-fifos = <16>;
interrupt-parent = <&intr_main_navss>;
+ status = "disabled";
};
ringacc: ringacc@3c000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index a61060c6bc198..d1c8047d96726 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -416,6 +416,7 @@ &serdes1 {
};
&mailbox0_cluster0 {
+ status = "okay";
interrupts = <436>;
mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
@@ -425,6 +426,7 @@ mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
};
&mailbox0_cluster1 {
+ status = "okay";
interrupts = <432>;
mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
@@ -433,46 +435,6 @@ mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 {
};
};
-&mailbox0_cluster2 {
- status = "disabled";
-};
-
-&mailbox0_cluster3 {
- status = "disabled";
-};
-
-&mailbox0_cluster4 {
- status = "disabled";
-};
-
-&mailbox0_cluster5 {
- status = "disabled";
-};
-
-&mailbox0_cluster6 {
- status = "disabled";
-};
-
-&mailbox0_cluster7 {
- status = "disabled";
-};
-
-&mailbox0_cluster8 {
- status = "disabled";
-};
-
-&mailbox0_cluster9 {
- status = "disabled";
-};
-
-&mailbox0_cluster10 {
- status = "disabled";
-};
-
-&mailbox0_cluster11 {
- status = "disabled";
-};
-
&mcu_r5fss0_core0 {
memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
<&mcu_r5fss0_core0_memory_region>;
--
2.37.3
SPI nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the SPI nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 5 +++++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
4 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 945a8a70332e9..fa4b6eb02fa57 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -574,6 +574,7 @@ &usb1 {
};
&mcu_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_spi0_pins_default>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index feef5fdb46886..74fd807d47396 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -217,6 +217,7 @@ main_spi0: spi@2100000 {
#size-cells = <0>;
dmas = <&main_udmap 0xc500>, <&main_udmap 0x4500>;
dma-names = "tx0", "rx0";
+ status = "disabled";
};
main_spi1: spi@2110000 {
@@ -229,6 +230,7 @@ main_spi1: spi@2110000 {
#size-cells = <0>;
assigned-clocks = <&k3_clks 137 1>;
assigned-clock-rates = <48000000>;
+ status = "disabled";
};
main_spi2: spi@2120000 {
@@ -239,6 +241,7 @@ main_spi2: spi@2120000 {
power-domains = <&k3_pds 139 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi3: spi@2130000 {
@@ -249,6 +252,7 @@ main_spi3: spi@2130000 {
power-domains = <&k3_pds 140 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
main_spi4: spi@2140000 {
@@ -259,6 +263,7 @@ main_spi4: spi@2140000 {
power-domains = <&k3_pds 141 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
sdhci0: mmc@4f80000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index dc0f439d2dacb..7a11501bad0bc 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -58,6 +58,7 @@ mcu_spi0: spi@40300000 {
power-domains = <&k3_pds 142 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi1: spi@40310000 {
@@ -68,6 +69,7 @@ mcu_spi1: spi@40310000 {
power-domains = <&k3_pds 143 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
mcu_spi2: spi@40320000 {
@@ -78,6 +80,7 @@ mcu_spi2: spi@40320000 {
power-domains = <&k3_pds 144 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
+ status = "disabled";
};
tscadc0: tscadc@40200000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 991a8559b4c3b..3f5a5ebfc8f3c 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -342,6 +342,7 @@ &ecap0 {
};
&main_spi0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_spi0_pins_default>;
#address-cells = <1>;
--
2.37.3
Although usually integrated as a child of an Ethernet controller, MDIO
IP has an independent pinout. This pinout should be controlled by
the MDIO node (so if it was to be disabled for instance, the pinmux
state would reflect that).
Move the MDIO pins pinmux to the MIDO nodes.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index f4b8747ebaef6..0c63c24941061 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -529,10 +529,13 @@ flash@0 {
&mcu_cpsw {
pinctrl-names = "default";
- pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
+ pinctrl-0 = <&mcu_cpsw_pins_default>;
};
&davinci_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mcu_mdio_pins_default>;
+
phy0: ethernet-phy@0 {
reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
--
2.37.3
McASP nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the McASP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 12 ------------
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 12 ------------
3 files changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index c6c79dde79c52..3cced26b520a1 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -674,15 +674,3 @@ &mcu_r5fss0_core1 {
<&mcu_r5fss0_core1_memory_region>;
mboxes = <&mailbox0_cluster1 &mbox_mcu_r5fss0_core1>;
};
-
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 3dc624a379c5f..1930da25d2821 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -799,6 +799,7 @@ mcasp0: mcasp@2b00000 {
clocks = <&k3_clks 104 0>;
clock-names = "fck";
power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp1: mcasp@2b10000 {
@@ -816,6 +817,7 @@ mcasp1: mcasp@2b10000 {
clocks = <&k3_clks 105 0>;
clock-names = "fck";
power-domains = <&k3_pds 105 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcasp2: mcasp@2b20000 {
@@ -833,6 +835,7 @@ mcasp2: mcasp@2b20000 {
clocks = <&k3_clks 106 0>;
clock-names = "fck";
power-domains = <&k3_pds 106 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
cal: cal@6f03000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index d1c8047d96726..592ab2b54cb3d 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -487,18 +487,6 @@ &cpsw_port1 {
phy-handle = <&phy0>;
};
-&mcasp0 {
- status = "disabled";
-};
-
-&mcasp1 {
- status = "disabled";
-};
-
-&mcasp2 {
- status = "disabled";
-};
-
&dss {
status = "disabled";
};
--
2.37.3
UART nodes defined in the top-level AM65x SoC dtsi files are incomplete
and may not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the UART nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++----
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 3 +++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 11 ++++++-----
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 +
.../boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 6 ++++++
.../dts/ti/k3-am6548-iot2050-advanced-common.dtsi | 4 ----
7 files changed, 19 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 32b7972375811..7b3087c19141c 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -360,15 +360,13 @@ &wkup_uart0 {
};
&main_uart1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart1_pins_default>;
};
-&main_uart2 {
- status = "disabled";
-};
-
&mcu_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&arduino_uart_pins_default>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 4005a73cfea99..ae414f5d83822 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -91,6 +91,7 @@ main_uart0: serial@2800000 {
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart1: serial@2810000 {
@@ -99,6 +100,7 @@ main_uart1: serial@2810000 {
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_uart2: serial@2820000 {
@@ -107,6 +109,7 @@ main_uart2: serial@2820000 {
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <48000000>;
power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
crypto: crypto@4e00000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 8d592bf41d6f1..bb70097693802 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -22,11 +22,12 @@ phy_gmii_sel: phy@4040 {
mcu_uart0: serial@40a00000 {
compatible = "ti,am654-uart";
- reg = <0x00 0x40a00000 0x00 0x100>;
- interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <96000000>;
- current-speed = <115200>;
- power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ reg = <0x00 0x40a00000 0x00 0x100>;
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <96000000>;
+ current-speed = <115200>;
+ power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_ram: sram@41c00000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index fa11d7142006a..bbe31532f984b 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -54,6 +54,7 @@ wkup_uart0: serial@42300000 {
clock-frequency = <48000000>;
current-speed = <115200>;
power-domains = <&k3_pds 150 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
wkup_i2c0: i2c@42120000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
index 4a9bf7d7c07dc..cd43fd11a5c2c 100644
--- a/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am6528-iot2050-basic-common.dtsi
@@ -50,6 +50,7 @@ AM65X_IOPAD(0x0194, PIN_INPUT, 1) /* (E24) UART0_RIN */
};
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 5850582dd4edf..956e9bc946b5f 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -271,7 +271,13 @@ &wkup_uart0 {
status = "reserved";
};
+&mcu_uart0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_uart0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_uart0_pins_default>;
power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
diff --git a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
index d25e8b26187f9..0f67e1ec0fb86 100644
--- a/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am6548-iot2050-advanced-common.dtsi
@@ -50,7 +50,3 @@ &sdhci0 {
ti,driver-strength-ohm = <50>;
disable-wp;
};
-
-&main_uart0 {
- status = "disabled";
-};
--
2.37.3
MCAN nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the MCAN nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 8 --------
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 8 --------
3 files changed, 2 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 35af8798f208e..c431d670757ba 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -650,14 +650,6 @@ &pcie1_rc {
reset-gpios = <&wkup_gpio0 27 GPIO_ACTIVE_HIGH>;
};
-&m_can0 {
- status = "disabled";
-};
-
-&m_can1 {
- status = "disabled";
-};
-
&pcie1_ep {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index 22f30174621e2..9ceae8a5b7e2d 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -177,6 +177,7 @@ m_can0: mcan@40528000 {
<GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
m_can1: mcan@40568000 {
@@ -192,6 +193,7 @@ m_can1: mcan@40568000 {
<GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
+ status = "disabled";
};
fss: fss@47000000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index beac2c563e831..bf6a6fe3d7ba3 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -431,14 +431,6 @@ &pcie1_ep {
status = "disabled";
};
-&m_can0 {
- status = "disabled";
-};
-
-&m_can1 {
- status = "disabled";
-};
-
&mailbox0_cluster0 {
interrupts = <436>;
--
2.37.3
ECAP nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information. (These and the EPWM nodes could be used to trigger internal
actions but they are not used like that currently)
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the ECAP nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 +
3 files changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index fa4b6eb02fa57..56562081a8e52 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -550,6 +550,7 @@ &mcu_cpsw {
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 49287f8493aea..fbb631c7664d2 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -205,6 +205,7 @@ ecap0: pwm@3100000 {
power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 39 0>;
clock-names = "fck";
+ status = "disabled";
};
main_spi0: spi@2100000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 3f5a5ebfc8f3c..f4b8747ebaef6 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -337,6 +337,7 @@ &main_i2c2 {
};
&ecap0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&ecap0_pins_default>;
};
--
2.37.3
I2C nodes defined in the top-level AM65x SoC dtsi files are incomplete
and will not be functional unless they are extended with pinmux
information.
As the pinmux is only known at the board integration level, these
nodes should only be enabled when provided with this information.
Disable the I2C nodes in the dtsi files and only enable the ones that
are actually pinned out on a given board.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 6 ++++++
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++++
arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 1 +
arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 9 +++++++++
5 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
index 7b3087c19141c..945a8a70332e9 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi
@@ -411,12 +411,14 @@ &db9_com_mode_pins_default
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
};
&mcu_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mcu_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -476,6 +478,7 @@ pcal9535_3: gpio@25 {
};
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -493,18 +496,21 @@ eeprom: eeprom@54 {
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
};
&main_i2c3 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c3_pins_default>;
clock-frequency = <400000>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index ae414f5d83822..feef5fdb46886 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -159,6 +159,7 @@ main_i2c0: i2c@2000000 {
clock-names = "fck";
clocks = <&k3_clks 110 1>;
power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c1: i2c@2010000 {
@@ -170,6 +171,7 @@ main_i2c1: i2c@2010000 {
clock-names = "fck";
clocks = <&k3_clks 111 1>;
power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c2: i2c@2020000 {
@@ -181,6 +183,7 @@ main_i2c2: i2c@2020000 {
clock-names = "fck";
clocks = <&k3_clks 112 1>;
power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
main_i2c3: i2c@2030000 {
@@ -192,6 +195,7 @@ main_i2c3: i2c@2030000 {
clock-names = "fck";
clocks = <&k3_clks 113 1>;
power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
ecap0: pwm@3100000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
index bb70097693802..dc0f439d2dacb 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -47,6 +47,7 @@ mcu_i2c0: i2c@40b00000 {
clock-names = "fck";
clocks = <&k3_clks 114 1>;
power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
mcu_spi0: spi@40300000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
index bbe31532f984b..fd2b998ebddc4 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi
@@ -66,6 +66,7 @@ wkup_i2c0: i2c@42120000 {
clock-names = "fck";
clocks = <&k3_clks 115 1>;
power-domains = <&k3_pds 115 TI_SCI_PD_EXCLUSIVE>;
+ status = "disabled";
};
intr_wkup_gpio: interrupt-controller@42200000 {
diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
index 956e9bc946b5f..991a8559b4c3b 100644
--- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts
@@ -284,6 +284,7 @@ &main_uart0 {
};
&wkup_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -302,7 +303,13 @@ pca9554: gpio@39 {
};
};
+&mcu_i2c0 {
+ status = "okay";
+ /* Default pinmux */
+};
+
&main_i2c0 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c0_pins_default>;
clock-frequency = <400000>;
@@ -316,12 +323,14 @@ pca9555: gpio@21 {
};
&main_i2c1 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c1_pins_default>;
clock-frequency = <400000>;
};
&main_i2c2 {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c2_pins_default>;
clock-frequency = <400000>;
--
2.37.3
On October 28, 2022 thus sayeth Andrew Davis:
> Hello all,
>
> Same story as for AM64x[0], AM62x[1], and J7x[2].
>
> Last round for AM65x, but there are some boards that I do not have
> (Simatic IOT2050), so testing very welcome!
>
> Thanks,
> Andrew
>
> [0] https://www.spinics.net/lists/arm-kernel/msg1018532.html
> [1] https://www.spinics.net/lists/arm-kernel/msg1018864.html
> [2] https://www.spinics.net/lists/arm-kernel/msg1019544.html
>
> Andrew Davis (11):
> arm64: dts: ti: k3-am65: Enable UART nodes at the board level
> arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
> arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
> arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level
> arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
> arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
> arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
> arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
> arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
> arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
> arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
LGTM! Thanks Andrew!
Reviewed-by: Bryan Brattlof <[email protected]>
~Bryan
On 28.10.22 16:24, Andrew Davis wrote:
> Hello all,
>
> Same story as for AM64x[0], AM62x[1], and J7x[2].
>
> Last round for AM65x, but there are some boards that I do not have
> (Simatic IOT2050), so testing very welcome!
>
> Thanks,
> Andrew
>
> [0] https://www.spinics.net/lists/arm-kernel/msg1018532.html
> [1] https://www.spinics.net/lists/arm-kernel/msg1018864.html
> [2] https://www.spinics.net/lists/arm-kernel/msg1019544.html
>
> Andrew Davis (11):
> arm64: dts: ti: k3-am65: Enable UART nodes at the board level
> arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
> arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
> arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level
> arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
> arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
> arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
> arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
> arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
> arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
> arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
>
> .../boot/dts/ti/k3-am65-iot2050-common.dtsi | 101 ++--------------
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 41 +++++++
> arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 18 ++-
> arch/arm64/boot/dts/ti/k3-am65-wakeup.dtsi | 2 +
> .../ti/k3-am6528-iot2050-basic-common.dtsi | 1 +
> .../arm64/boot/dts/ti/k3-am654-base-board.dts | 113 ++++--------------
> .../ti/k3-am6548-iot2050-advanced-common.dtsi | 4 -
> 7 files changed, 94 insertions(+), 186 deletions(-)
>
(widely)
Tested-by: Jan Kiszka <[email protected]>
We are still seeing some likely unrelated issue on our latest board with
mainline. Not all aspects could be tested for that reason, but I
strongly suspect that this series won't break those.
Jan
--
Siemens AG, Technology
Competence Center Embedded Linux
Hi Andrew Davis,
On Fri, 28 Oct 2022 09:24:06 -0500, Andrew Davis wrote:
> Same story as for AM64x[0], AM62x[1], and J7x[2].
>
> Last round for AM65x, but there are some boards that I do not have
> (Simatic IOT2050), so testing very welcome!
>
> Thanks,
> Andrew
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[01/11] arm64: dts: ti: k3-am65: Enable UART nodes at the board level
commit: 65e8781ac90e74242ebb1a98bf415809e8387aaf
[02/11] arm64: dts: ti: k3-am65: Enable I2C nodes at the board level
commit: c0a5ba87af56f073145dd026280454aec4a44db0
[03/11] arm64: dts: ti: k3-am65: Enable SPI nodes at the board level
commit: 1c49cbb19b1f2c61168741f987e65b50dd2f97de
[04/11] arm64: dts: ti: k3-am65: Enable EPWM nodes at the board level
commit: 5780cf09409551c67112127b90786e553c8f9a25
[05/11] arm64: dts: ti: k3-am65: Enable ECAP nodes at the board level
commit: c1d1189eafb27fa5c0cb0b92a4e81c155709068b
[06/11] arm64: dts: ti: k3-am65: MDIO pinmux should belong to the MDIO node
commit: 0edd6d7ed646a53b41d09f7aa1d8c01d23bd7b73
[07/11] arm64: dts: ti: k3-am65: Enable MDIO nodes at the board level
commit: c75c5c0bba500b1e454dc2591acdd6596fe64ce2
[08/11] arm64: dts: ti: k3-am65: Enable MCAN nodes at the board level
commit: b08bf4a5c0ed0a6b8472ca78ccf416d73d2609aa
[09/11] arm64: dts: ti: k3-am65: Enable PCIe nodes at the board level
commit: 7ff8432c272e3556461b7c9daad8156ae446e812
[10/11] arm64: dts: ti: k3-am65: Enable Mailbox nodes at the board level
commit: 3f9089ea008c195b6cf449735c5a3a5fcac1a382
[11/11] arm64: dts: ti: k3-am65: Enable McASP nodes at the board level
commit: fdb02688f22b397c811328bf826b5b110d5cdc41
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D