From: Xinlei Lee <[email protected]>
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Mainly add the following two flag:
1.The audio packet arrangement function is to only arrange audio
packets into the Hblanking area. In order to align with the HW
default setting of g1200, this function needs to be turned off.
2.Due to the difference of HW, different dividers need to be set.
Base on the branch of linus/master v6.3.
Xinlei Lee (2):
dt-bindings: display: mediatek: dp: Add compatible for MediaTek MT8188
drm/mediatek: dp: Add the audio control to mtk_dp_data struct
.../display/mediatek/mediatek,dp.yaml | 1 +
drivers/gpu/drm/mediatek/mtk_dp.c | 32 ++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 5 +++
3 files changed, 37 insertions(+), 1 deletion(-)
--
2.18.0
From: Xinlei Lee <[email protected]>
Mainly add the following two flag:
1.The audio packet arrangement function is to only arrange audio
packets into the Hblanking area. In order to align with the HW
default setting of g1200, this function needs to be turned off.
2.Due to the difference of HW, different dividers need to be set.
Signed-off-by: Xinlei Lee <[email protected]>
Signed-off-by: Jitao Shi <[email protected]>
---
drivers/gpu/drm/mediatek/mtk_dp.c | 32 ++++++++++++++++++++++++++-
drivers/gpu/drm/mediatek/mtk_dp_reg.h | 5 +++++
2 files changed, 36 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
index 767b71da31a4..65a9984eac81 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp.c
+++ b/drivers/gpu/drm/mediatek/mtk_dp.c
@@ -139,6 +139,8 @@ struct mtk_dp_data {
unsigned int smc_cmd;
const struct mtk_dp_efuse_fmt *efuse_fmt;
bool audio_supported;
+ const bool arrange;
+ const u8 audio_m_div2;
};
static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
@@ -646,8 +648,10 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)
{
+ u8 div2_id = mtk_dp->data->audio_m_div2;
+
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
- AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
+ div2_id << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT,
AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
}
@@ -1362,6 +1366,14 @@ static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
}
+static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp)
+{
+ if (mtk_dp->data->arrange) {
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, BIT(12));
+ mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, 0xFFF);
+ }
+}
+
static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
{
u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,
@@ -1371,6 +1383,7 @@ static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
MTK_DP_PIX_PER_ADDR);
mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
mtk_dp_setup_encoder(mtk_dp);
+ mtk_dp_audio_sample_arrange(mtk_dp);
mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
}
@@ -2615,11 +2628,22 @@ static int mtk_dp_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);
+static const struct mtk_dp_data mt8188_dp_data = {
+ .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
+ .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
+ .efuse_fmt = mt8195_dp_efuse_fmt,
+ .audio_supported = true,
+ .arrange = true,
+ .audio_m_div2 = 4,
+};
+
static const struct mtk_dp_data mt8195_edp_data = {
.bridge_type = DRM_MODE_CONNECTOR_eDP,
.smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
.efuse_fmt = mt8195_edp_efuse_fmt,
.audio_supported = false,
+ .arrange = false,
+ .audio_m_div2 = 5,
};
static const struct mtk_dp_data mt8195_dp_data = {
@@ -2627,9 +2651,15 @@ static const struct mtk_dp_data mt8195_dp_data = {
.smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
.efuse_fmt = mt8195_dp_efuse_fmt,
.audio_supported = true,
+ .arrange = false,
+ .audio_m_div2 = 5,
};
static const struct of_device_id mtk_dp_of_match[] = {
+ {
+ .compatible = "mediatek,mt8188-dp-tx",
+ .data = &mt8188_dp_data,
+ },
{
.compatible = "mediatek,mt8195-edp-tx",
.data = &mt8195_edp_data,
diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
index 84e38cef03c2..4dc4f7cd0ef2 100644
--- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
+++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
@@ -158,6 +158,7 @@
#define MTK_DP_ENC0_P0_30A8 0x30a8
#define MTK_DP_ENC0_P0_30BC 0x30bc
#define ISRC_CONT_DP_ENC0_P0 BIT(0)
+#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT 8
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
@@ -228,6 +229,10 @@
VIDEO_STABLE_CNT_THRD_DP_ENC1_P0 | \
SDP_DP13_EN_DP_ENC1_P0 | \
BS2BS_MODE_DP_ENC1_P0)
+
+#define MTK_DP_ENC1_P0_3374 0x3374
+#define AU_ASP_PACKET_ONLY_IN_HBLANK_ENABLE_MASK 0x1000
+
#define MTK_DP_ENC1_P0_33F4 0x33f4
#define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
#define DP_ENC_DUMMY_RW_1 BIT(9)
--
2.18.0
From: Xinlei Lee <[email protected]>
Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
Signed-off-by: Xinlei Lee <[email protected]>
Signed-off-by: Jitao Shi <[email protected]>
---
.../devicetree/bindings/display/mediatek/mediatek,dp.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
index ff781f2174a0..d1b8259b79a8 100644
--- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
+++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dp.yaml
@@ -21,6 +21,7 @@ description: |
properties:
compatible:
enum:
+ - mediatek,mt8188-dp-tx
- mediatek,mt8195-dp-tx
- mediatek,mt8195-edp-tx
--
2.18.0
Hello Xinlei,
My comments below:
On Thu, 2023-04-13 at 12:06 +0800, [email protected] wrote:
> From: Xinlei Lee <[email protected]>
>
> Mainly add the following two flag:
>
> 1.The audio packet arrangement function is to only arrange audio
> packets into the Hblanking area. In order to align with the HW
> default setting of g1200, this function needs to be turned off.
>
what is g1200?
> 2.Due to the difference of HW, different dividers need to be set.
>
> Signed-off-by: Xinlei Lee <[email protected]>
> Signed-off-by: Jitao Shi <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_dp.c | 32
> ++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 5 +++++
> 2 files changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c
> b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 767b71da31a4..65a9984eac81 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -139,6 +139,8 @@ struct mtk_dp_data {
> unsigned int smc_cmd;
> const struct mtk_dp_efuse_fmt *efuse_fmt;
> bool audio_supported;
> + const bool arrange;
> + const u8 audio_m_div2;
> };
>
> static const struct mtk_dp_efuse_fmt
> mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
> @@ -646,8 +648,10 @@ static void
> mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
>
> static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)
> {
> + u8 div2_id = mtk_dp->data->audio_m_div2;
> +
> mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
> - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> + div2_id <<
> AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT,
> AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
> }
>
> @@ -1362,6 +1366,14 @@ static void
> mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
> SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK)
> ;
> }
>
> +static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp)
> +{
> + if (mtk_dp->data->arrange) {
> + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
> BIT(12));
> + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0,
> 0xFFF);
> + }
> +}
> +
Remove "if (mtk_dp->data->arrange)" and add them ouside this function.
> static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
> {
> u32 sram_read_start = min_t(u32,
> MTK_DP_TBC_BUF_READ_START_ADDR,
> @@ -1371,6 +1383,7 @@ static void mtk_dp_setup_tu(struct mtk_dp
> *mtk_dp)
> MTK_DP_PIX_PER_ADDR);
> mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
> mtk_dp_setup_encoder(mtk_dp);
> + mtk_dp_audio_sample_arrange(mtk_dp);
if (mtk_dp->data->arrange)
mtk_dp_audio_sample_arrange(mtk_dp);
BRs,
Bo-Chen
> mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
> mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
> }
> @@ -2615,11 +2628,22 @@ static int mtk_dp_resume(struct device *dev)
>
> static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend,
> mtk_dp_resume);
>
> +static const struct mtk_dp_data mt8188_dp_data = {
> + .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
> + .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> + .efuse_fmt = mt8195_dp_efuse_fmt,
> + .audio_supported = true,
> + .arrange = true,
> + .audio_m_div2 = 4,
> +};
> +
> static const struct mtk_dp_data mt8195_edp_data = {
> .bridge_type = DRM_MODE_CONNECTOR_eDP,
> .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
> .efuse_fmt = mt8195_edp_efuse_fmt,
> .audio_supported = false,
> + .arrange = false,
> + .audio_m_div2 = 5,
> };
>
> static const struct mtk_dp_data mt8195_dp_data = {
> @@ -2627,9 +2651,15 @@ static const struct mtk_dp_data mt8195_dp_data
> = {
> .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> .efuse_fmt = mt8195_dp_efuse_fmt,
> .audio_supported = true,
> + .arrange = false,
> + .audio_m_div2 = 5,
> };
>
> static const struct of_device_id mtk_dp_of_match[] = {
> + {
> + .compatible = "mediatek,mt8188-dp-tx",
> + .data = &mt8188_dp_data,
> + },
> {
> .compatible = "mediatek,mt8195-edp-tx",
> .data = &mt8195_edp_data,
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 84e38cef03c2..4dc4f7cd0ef2 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -158,6 +158,7 @@
> #define MTK_DP_ENC0_P0_30A8 0x30a8
> #define MTK_DP_ENC0_P0_30BC 0x30bc
> #define ISRC_CONT_DP_ENC0_P0 BIT(0)
> +#define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT 8
> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK GENMASK(10, 8)
> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_2 (1 << 8)
> #define AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MUL_4 (2 << 8)
> @@ -228,6 +229,10 @@
> VIDEO_STABLE_C
> NT_THRD_DP_ENC1_P0 | \
> SDP_DP13_EN_DP
> _ENC1_P0 | \
> BS2BS_MODE_DP_
> ENC1_P0)
> +
> +#define MTK_DP_ENC1_P0_3374 0x3374
> +#define AU_ASP_PACKET_ONLY_IN_HBLANK_ENABLE_MASK 0x1000
> +
> #define MTK_DP_ENC1_P0_33F4 0x33f4
> #define DP_ENC_DUMMY_RW_1_AUDIO_RST_EN BIT(0)
> #define DP_ENC_DUMMY_RW_1 BIT(9)
On 13/04/2023 06:06, [email protected] wrote:
> From: Xinlei Lee <[email protected]>
>
> Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
>
> Signed-off-by: Xinlei Lee <[email protected]>
> Signed-off-by: Jitao Shi <[email protected]>
> ---
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
Il 13/04/23 06:06, [email protected] ha scritto:
> From: Xinlei Lee <[email protected]>
>
> Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
>
> Signed-off-by: Xinlei Lee <[email protected]>
> Signed-off-by: Jitao Shi <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Are you sure that there's no eDP support planned for this SoC?
...because in that case you should also add a mediatek,mt8188-edp-tx compatible.
P.S.: Resent because the first one went out from the wrong email address. Sorry.
Il 13/04/23 06:06, [email protected] ha scritto:
> From: Xinlei Lee <[email protected]>
>
> Mainly add the following two flag:
>
> 1.The audio packet arrangement function is to only arrange audio
> packets into the Hblanking area. In order to align with the HW
> default setting of g1200, this function needs to be turned off.
>
> 2.Due to the difference of HW, different dividers need to be set.
>
> Signed-off-by: Xinlei Lee <[email protected]>
> Signed-off-by: Jitao Shi <[email protected]>
> ---
> drivers/gpu/drm/mediatek/mtk_dp.c | 32 ++++++++++++++++++++++++++-
> drivers/gpu/drm/mediatek/mtk_dp_reg.h | 5 +++++
> 2 files changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp.c b/drivers/gpu/drm/mediatek/mtk_dp.c
> index 767b71da31a4..65a9984eac81 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp.c
> +++ b/drivers/gpu/drm/mediatek/mtk_dp.c
> @@ -139,6 +139,8 @@ struct mtk_dp_data {
> unsigned int smc_cmd;
> const struct mtk_dp_efuse_fmt *efuse_fmt;
> bool audio_supported;
> + const bool arrange;
bool audio_pkt_in_hblank_area
> + const u8 audio_m_div2;
u16 audio_m_div2_bit would be more descriptive, and would allow you to store
the bit for later use as-it-is.
P.S.: This structure is always declared as const, so it's useless to declare
each of its members as const.
> };
>
> static const struct mtk_dp_efuse_fmt mt8195_edp_efuse_fmt[MTK_DP_CAL_MAX] = {
> @@ -646,8 +648,10 @@ static void mtk_dp_audio_sdp_asp_set_channels(struct mtk_dp *mtk_dp,
>
> static void mtk_dp_audio_set_divider(struct mtk_dp *mtk_dp)
> {
> + u8 div2_id = mtk_dp->data->audio_m_div2;
> +
> mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC,
> - AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> + div2_id << AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_SHIFT,
So, if you do it like I've suggested, this becomes
mtk_dp_update_bits(mtk_dp, MTK_DP_ENC0_P0_30BC
mtk_dp->data->audio_m_div2_bit,
AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
> AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_MASK);
> }
>
> @@ -1362,6 +1366,14 @@ static void mtk_dp_sdp_set_down_cnt_init_in_hblank(struct mtk_dp *mtk_dp)
> SDP_DOWN_CNT_INIT_IN_HBLANK_DP_ENC1_P0_MASK);
> }
>
> +static void mtk_dp_audio_sample_arrange(struct mtk_dp *mtk_dp)
Since your register names are not human readable (I know that this is not your
fault, don't worry), please add a comment that describes this function, saying
that this arranges the audio packets into the Hblank area, similarly to how you
described the same into the commit description.
This would otherwise be a nightmare to understand for the "random reader" :-)
> +{
> + if (mtk_dp->data->arrange) {
You can reduce indentation, if you need to do so (after adding the definitions)
with doing the inverse check like so:
if (!mtk_dp->data->audio_pkt_in_hblank_area)
return;
> + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, BIT(12));
Add a definition for this bit....
> + mtk_dp_update_bits(mtk_dp, MTK_DP_ENC1_P0_3374, 0, 0xFFF);
....and for this mask; please define this one as GENMASK(11, 0).
> + }
> +}
> +
> static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
> {
> u32 sram_read_start = min_t(u32, MTK_DP_TBC_BUF_READ_START_ADDR,
> @@ -1371,6 +1383,7 @@ static void mtk_dp_setup_tu(struct mtk_dp *mtk_dp)
> MTK_DP_PIX_PER_ADDR);
> mtk_dp_set_sram_read_start(mtk_dp, sram_read_start);
> mtk_dp_setup_encoder(mtk_dp);
> + mtk_dp_audio_sample_arrange(mtk_dp);
> mtk_dp_sdp_set_down_cnt_init_in_hblank(mtk_dp);
> mtk_dp_sdp_set_down_cnt_init(mtk_dp, sram_read_start);
> }
> @@ -2615,11 +2628,22 @@ static int mtk_dp_resume(struct device *dev)
>
> static SIMPLE_DEV_PM_OPS(mtk_dp_pm_ops, mtk_dp_suspend, mtk_dp_resume);
>
> +static const struct mtk_dp_data mt8188_dp_data = {
> + .bridge_type = DRM_MODE_CONNECTOR_DisplayPort,
> + .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> + .efuse_fmt = mt8195_dp_efuse_fmt,
> + .audio_supported = true,
> + .arrange = true,
> + .audio_m_div2 = 4,
.audio_m_div2_bit = MT8188_AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> +};
> +
> static const struct mtk_dp_data mt8195_edp_data = {
> .bridge_type = DRM_MODE_CONNECTOR_eDP,
> .smc_cmd = MTK_DP_SIP_ATF_EDP_VIDEO_UNMUTE,
> .efuse_fmt = mt8195_edp_efuse_fmt,
> .audio_supported = false,
> + .arrange = false,
> + .audio_m_div2 = 5,
.audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> };
>
> static const struct mtk_dp_data mt8195_dp_data = {
> @@ -2627,9 +2651,15 @@ static const struct mtk_dp_data mt8195_dp_data = {
> .smc_cmd = MTK_DP_SIP_ATF_VIDEO_UNMUTE,
> .efuse_fmt = mt8195_dp_efuse_fmt,
> .audio_supported = true,
> + .arrange = false,
> + .audio_m_div2 = 5,
.audio_m_div2_bit = AUDIO_M_CODE_MULT_DIV_SEL_DP_ENC0_P0_DIV_2,
> };
>
> static const struct of_device_id mtk_dp_of_match[] = {
> + {
> + .compatible = "mediatek,mt8188-dp-tx",
> + .data = &mt8188_dp_data,
> + },
Please also add support for mediatek,mt8188-edp-tx.
Regards,
Angelo
Il 13/04/23 06:06, [email protected] ha scritto:
> From: Xinlei Lee <[email protected]>
>
> Add dt-binding documentation of dp-tx for MediaTek MT8188 SoC.
>
> Signed-off-by: Xinlei Lee <[email protected]>
> Signed-off-by: Jitao Shi <[email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
Are you sure that there's no eDP support planned for this SoC?
...because in that case you should also add a mediatek,mt8188-edp-tx compatible.