This series adds support for PCIe to the SC8280XP and SA840P platforms
and specifically enables the NVMe SSD, modem and WiFi controller on the
SC8280XP-CRD and Lenovo Thinkpad X13s.
Note that these patches depend on the PCIe QMP PHY support that was
merged this morning:
https://lore.kernel.org/lkml/[email protected]/
as well as the PCIe interconnect support:
https://lore.kernel.org/all/[email protected]/
where the binding has been acked by the DT maintainer but support has
not yet been merged.
Johan
Johan Hovold (9):
arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
arm64: dts: qcom: sa8295p-adp: enable PCIe
arm64: dts: qcom: sc8280xp-crd: rename backlight and misc regulators
arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD
arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem
arm64: dts: qcom: sc8280xp-crd: enable WiFi controller
arm64: dts: qcom: sc8280xp-x13s: enable NVMe SSD
arm64: dts: qcom: sc8280xp-x13s: enable modem
arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller
arch/arm64/boot/dts/qcom/sa8295p-adp.dts | 171 ++++++
arch/arm64/boot/dts/qcom/sa8540p.dtsi | 59 +++
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 197 ++++++-
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 202 +++++++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 493 +++++++++++++++++-
5 files changed, 1115 insertions(+), 7 deletions(-)
--
2.37.4
The SC8280XP platform has seven PCIe controllers:
PCIe0 USB4
PCIe1 USB4
PCIe2A 4-lane
PCIe2B 2-lane
PCIe3A 4-lane
PCIe3B 2-lane
PCIe4 1-lane
while SA8540P only has five (PCIe2-4).
Add devicetree nodes for the PCIe2-4 controllers and their PHYs.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sa8540p.dtsi | 59 +++
arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 493 ++++++++++++++++++++++++-
2 files changed, 547 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
index 8ea2886fbab2..01a24b6a5e6d 100644
--- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
@@ -128,6 +128,65 @@ opp-2592000000 {
};
};
+&pcie2a {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <0>;
+
+ interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie2b {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <1>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie3a {
+ compatible = "qcom,pcie-sa8540p";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x40000000 0x0 0xf1d>,
+ <0x0 0x40000f20 0x0 0xa8>,
+ <0x0 0x40001000 0x0 0x1000>,
+ <0x0 0x40100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+
+ ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
+
+ linux,pci-domain = <2>;
+
+ interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+};
+
+&pcie3b {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <3>;
+
+ interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
+&pcie4 {
+ compatible = "qcom,pcie-sa8540p";
+
+ linux,pci-domain = <4>;
+
+ interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+};
+
&rpmhpd {
compatible = "qcom,sa8540p-rpmhpd";
};
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
index 6bc12e507d21..27f5c2f82338 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
@@ -729,11 +729,11 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>,
- <0>,
- <0>,
+ <&pcie2a_phy>,
+ <&pcie2b_phy>,
+ <&pcie3a_phy>,
+ <&pcie3b_phy>,
+ <&pcie4_phy>,
<0>,
<0>;
power-domains = <&rpmhpd SC8280XP_CX>;
@@ -839,6 +839,489 @@ qup1: geniqup@ac0000 {
status = "disabled";
};
+ pcie4: pcie@1c00000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c00000 0x0 0x3000>,
+ <0x0 0x30000000 0x0 0xf1d>,
+ <0x0 0x30000f20 0x0 0xa8>,
+ <0x0 0x30001000 0x0 0x1000>,
+ <0x0 0x30100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
+ <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <6>;
+ num-lanes = <1>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
+ <&gcc GCC_CNOC_PCIE4_QX_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf",
+ "cnoc_qx";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_4_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_4_GDSC>;
+
+ phys = <&pcie4_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie4_phy: phy@1c06000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
+ reg = <0x0 0x01c06000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_CLKREF_CLK>,
+ <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_4_PIPE_CLK>,
+ <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_4_GDSC>;
+
+ resets = <&gcc GCC_PCIE_4_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_4_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie3b: pcie@1c08000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c08000 0x0 0x3000>,
+ <0x0 0x32000000 0x0 0xf1d>,
+ <0x0 0x32000f20 0x0 0xa8>,
+ <0x0 0x32001000 0x0 0x1000>,
+ <0x0 0x32100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
+ <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <5>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
+ <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3B_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_3B_GDSC>;
+
+ phys = <&pcie3b_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie3b_phy: phy@1c0e000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c0e000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
+ <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+ <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3B_PIPE_CLK>,
+ <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_3B_GDSC>;
+
+ resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3b_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie3a: pcie@1c10000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c10000 0x0 0x3000>,
+ <0x0 0x34000000 0x0 0xf1d>,
+ <0x0 0x34000f20 0x0 0xa8>,
+ <0x0 0x34001000 0x0 0x1000>,
+ <0x0 0x34100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
+ <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <4>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
+ <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_3A_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_3A_GDSC>;
+
+ phys = <&pcie3a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie3a_phy: phy@1c14000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
+ reg = <0x0 0x01c14000 0x0 0x2000>,
+ <0x0 0x01c16000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
+ <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
+ <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_3A_PIPE_CLK>,
+ <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_3A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
+ reset-names = "phy";
+
+ qcom,4ln-config-sel = <&tcsr 0xa044 1>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_3a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie2b: pcie@1c18000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c18000 0x0 0x3000>,
+ <0x0 0x38000000 0x0 0xf1d>,
+ <0x0 0x38000f20 0x0 0xa8>,
+ <0x0 0x38001000 0x0 0x1000>,
+ <0x0 0x38100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
+ <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <3>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
+ <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_2B_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_2B_GDSC>;
+
+ phys = <&pcie2b_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie2b_phy: phy@1c1e000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
+ reg = <0x0 0x01c1e000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
+ <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+ <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_2B_PIPE_CLK>,
+ <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_2B_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
+ reset-names = "phy";
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2b_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie2a: pcie@1c20000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-sc8280xp";
+ reg = <0x0 0x01c20000 0x0 0x3000>,
+ <0x0 0x3c000000 0x0 0xf1d>,
+ <0x0 0x3c000f20 0x0 0xa8>,
+ <0x0 0x3c001000 0x0 0x1000>,
+ <0x0 0x3c100000 0x0 0x100000>;
+ reg-names = "parf", "dbi", "elbi", "atu", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
+ <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
+ bus-range = <0x00 0xff>;
+
+ linux,pci-domain = <2>;
+ num-lanes = <4>;
+
+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0", "msi1", "msi2", "msi3";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "ddrss_sf_tbu",
+ "noc_aggr_4",
+ "noc_aggr_south_sf";
+
+ assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
+ <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
+ interconnect-names = "pcie-mem", "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_2A_BCR>;
+ reset-names = "pci";
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ phys = <&pcie2a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie2a_phy: phy@1c24000 {
+ compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
+ reg = <0x0 0x01c24000 0x0 0x2000>,
+ <0x0 0x01c26000 0x0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
+ <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
+ <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_2A_PIPE_CLK>,
+ <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "rchng",
+ "pipe", "pipediv2";
+
+ assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc PCIE_2A_GDSC>;
+
+ resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
+ reset-names = "phy";
+
+ qcom,4ln-config-sel = <&tcsr 0xa044 0>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie_2a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
ufs_mem_hc: ufs@1d84000 {
compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
"jedec,ufs-2.0";
--
2.37.4
On 10/11/2022 11:35, Johan Hovold wrote:
> The SC8280XP platform has seven PCIe controllers:
>
> PCIe0 USB4
> PCIe1 USB4
> PCIe2A 4-lane
> PCIe2B 2-lane
> PCIe3A 4-lane
> PCIe3B 2-lane
> PCIe4 1-lane
>
> while SA8540P only has five (PCIe2-4).
>
> Add devicetree nodes for the PCIe2-4 controllers and their PHYs.
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
Reviewed-by: Konrad Dybcio <[email protected]>
Konrad
> arch/arm64/boot/dts/qcom/sa8540p.dtsi | 59 +++
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 493 ++++++++++++++++++++++++-
> 2 files changed, 547 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sa8540p.dtsi b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> index 8ea2886fbab2..01a24b6a5e6d 100644
> --- a/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sa8540p.dtsi
> @@ -128,6 +128,65 @@ opp-2592000000 {
> };
> };
>
> +&pcie2a {
> + compatible = "qcom,pcie-sa8540p";
> +
> + linux,pci-domain = <0>;
> +
> + interrupts = <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +};
> +
> +&pcie2b {
> + compatible = "qcom,pcie-sa8540p";
> +
> + linux,pci-domain = <1>;
> +
> + interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +};
> +
> +&pcie3a {
> + compatible = "qcom,pcie-sa8540p";
> + reg = <0x0 0x01c10000 0x0 0x3000>,
> + <0x0 0x40000000 0x0 0xf1d>,
> + <0x0 0x40000f20 0x0 0xa8>,
> + <0x0 0x40001000 0x0 0x1000>,
> + <0x0 0x40100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> +
> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1d00000>;
> +
> + linux,pci-domain = <2>;
> +
> + interrupts = <GIC_SPI 567 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
> +};
> +
> +&pcie3b {
> + compatible = "qcom,pcie-sa8540p";
> +
> + linux,pci-domain = <3>;
> +
> + interrupts = <GIC_SPI 565 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +};
> +
> +&pcie4 {
> + compatible = "qcom,pcie-sa8540p";
> +
> + linux,pci-domain = <4>;
> +
> + interrupts = <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi";
> +};
> +
> &rpmhpd {
> compatible = "qcom,sa8540p-rpmhpd";
> };
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 6bc12e507d21..27f5c2f82338 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -729,11 +729,11 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&pcie2a_phy>,
> + <&pcie2b_phy>,
> + <&pcie3a_phy>,
> + <&pcie3b_phy>,
> + <&pcie4_phy>,
> <0>,
> <0>;
> power-domains = <&rpmhpd SC8280XP_CX>;
> @@ -839,6 +839,489 @@ qup1: geniqup@ac0000 {
> status = "disabled";
> };
>
> + pcie4: pcie@1c00000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc8280xp";
> + reg = <0x0 0x01c00000 0x0 0x3000>,
> + <0x0 0x30000000 0x0 0xf1d>,
> + <0x0 0x30000f20 0x0 0xa8>,
> + <0x0 0x30001000 0x0 0x1000>,
> + <0x0 0x30100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x30200000 0x0 0x30200000 0x0 0x100000>,
> + <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <6>;
> + num-lanes = <1>;
> +
> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
> + <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>,
> + <&gcc GCC_CNOC_PCIE4_QX_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr_4",
> + "noc_aggr_south_sf",
> + "cnoc_qx";
> +
> + assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_4_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_4_GDSC>;
> +
> + phys = <&pcie4_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> + pcie4_phy: phy@1c06000 {
> + compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy";
> + reg = <0x0 0x01c06000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
> + <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_4_CLKREF_CLK>,
> + <&gcc GCC_PCIE4_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_4_PIPE_CLK>,
> + <&gcc GCC_PCIE_4_PIPEDIV2_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "rchng",
> + "pipe", "pipediv2";
> +
> + assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_4_GDSC>;
> +
> + resets = <&gcc GCC_PCIE_4_PHY_BCR>;
> + reset-names = "phy";
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_4_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + pcie3b: pcie@1c08000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc8280xp";
> + reg = <0x0 0x01c08000 0x0 0x3000>,
> + <0x0 0x32000000 0x0 0xf1d>,
> + <0x0 0x32000f20 0x0 0xa8>,
> + <0x0 0x32001000 0x0 0x1000>,
> + <0x0 0x32100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x32200000 0x0 0x32200000 0x0 0x100000>,
> + <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <5>;
> + num-lanes = <2>;
> +
> + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
> + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_3B_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr_4",
> + "noc_aggr_south_sf";
> +
> + assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_3B_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_3B_GDSC>;
> +
> + phys = <&pcie3b_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> + pcie3b_phy: phy@1c0e000 {
> + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
> + reg = <0x0 0x01c0e000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_3B_AUX_CLK>,
> + <&gcc GCC_PCIE_3B_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
> + <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3B_PIPE_CLK>,
> + <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "rchng",
> + "pipe", "pipediv2";
> +
> + assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_3B_GDSC>;
> +
> + resets = <&gcc GCC_PCIE_3B_PHY_BCR>;
> + reset-names = "phy";
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_3b_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + pcie3a: pcie@1c10000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc8280xp";
> + reg = <0x0 0x01c10000 0x0 0x3000>,
> + <0x0 0x34000000 0x0 0xf1d>,
> + <0x0 0x34000f20 0x0 0xa8>,
> + <0x0 0x34001000 0x0 0x1000>,
> + <0x0 0x34100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x34200000 0x0 0x34200000 0x0 0x100000>,
> + <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <4>;
> + num-lanes = <4>;
> +
> + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_3A_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr_4",
> + "noc_aggr_south_sf";
> +
> + assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_3A_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_3A_GDSC>;
> +
> + phys = <&pcie3a_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> + pcie3a_phy: phy@1c14000 {
> + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
> + reg = <0x0 0x01c14000 0x0 0x2000>,
> + <0x0 0x01c16000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_3A_AUX_CLK>,
> + <&gcc GCC_PCIE_3A_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_3A3B_CLKREF_CLK>,
> + <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_3A_PIPE_CLK>,
> + <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "rchng",
> + "pipe", "pipediv2";
> +
> + assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_3A_GDSC>;
> +
> + resets = <&gcc GCC_PCIE_3A_PHY_BCR>;
> + reset-names = "phy";
> +
> + qcom,4ln-config-sel = <&tcsr 0xa044 1>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_3a_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + pcie2b: pcie@1c18000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc8280xp";
> + reg = <0x0 0x01c18000 0x0 0x3000>,
> + <0x0 0x38000000 0x0 0xf1d>,
> + <0x0 0x38000f20 0x0 0xa8>,
> + <0x0 0x38001000 0x0 0x1000>,
> + <0x0 0x38100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x38200000 0x0 0x38200000 0x0 0x100000>,
> + <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <3>;
> + num-lanes = <2>;
> +
> + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
> + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_2B_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr_4",
> + "noc_aggr_south_sf";
> +
> + assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_2B_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_2B_GDSC>;
> +
> + phys = <&pcie2b_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> + pcie2b_phy: phy@1c1e000 {
> + compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy";
> + reg = <0x0 0x01c1e000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_2B_AUX_CLK>,
> + <&gcc GCC_PCIE_2B_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
> + <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_2B_PIPE_CLK>,
> + <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "rchng",
> + "pipe", "pipediv2";
> +
> + assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_2B_GDSC>;
> +
> + resets = <&gcc GCC_PCIE_2B_PHY_BCR>;
> + reset-names = "phy";
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_2b_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> + pcie2a: pcie@1c20000 {
> + device_type = "pci";
> + compatible = "qcom,pcie-sc8280xp";
> + reg = <0x0 0x01c20000 0x0 0x3000>,
> + <0x0 0x3c000000 0x0 0xf1d>,
> + <0x0 0x3c000f20 0x0 0xa8>,
> + <0x0 0x3c001000 0x0 0x1000>,
> + <0x0 0x3c100000 0x0 0x100000>;
> + reg-names = "parf", "dbi", "elbi", "atu", "config";
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges = <0x01000000 0x0 0x3c200000 0x0 0x3c200000 0x0 0x100000>,
> + <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>;
> + bus-range = <0x00 0xff>;
> +
> + linux,pci-domain = <2>;
> + num-lanes = <4>;
> +
> + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "msi0", "msi1", "msi2", "msi3";
> +
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0x7>;
> + interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>,
> + <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
> + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>,
> + <&gcc GCC_PCIE_2A_SLV_AXI_CLK>,
> + <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>,
> + <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>,
> + <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>;
> + clock-names = "aux",
> + "cfg",
> + "bus_master",
> + "bus_slave",
> + "slave_q2a",
> + "ddrss_sf_tbu",
> + "noc_aggr_4",
> + "noc_aggr_south_sf";
> +
> + assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>;
> + assigned-clock-rates = <19200000>;
> +
> + interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>;
> + interconnect-names = "pcie-mem", "cpu-pcie";
> +
> + resets = <&gcc GCC_PCIE_2A_BCR>;
> + reset-names = "pci";
> +
> + power-domains = <&gcc PCIE_2A_GDSC>;
> +
> + phys = <&pcie2a_phy>;
> + phy-names = "pciephy";
> +
> + status = "disabled";
> + };
> +
> + pcie2a_phy: phy@1c24000 {
> + compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy";
> + reg = <0x0 0x01c24000 0x0 0x2000>,
> + <0x0 0x01c26000 0x0 0x2000>;
> +
> + clocks = <&gcc GCC_PCIE_2A_AUX_CLK>,
> + <&gcc GCC_PCIE_2A_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_2A2B_CLKREF_CLK>,
> + <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>,
> + <&gcc GCC_PCIE_2A_PIPE_CLK>,
> + <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "rchng",
> + "pipe", "pipediv2";
> +
> + assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>;
> + assigned-clock-rates = <100000000>;
> +
> + power-domains = <&gcc PCIE_2A_GDSC>;
> +
> + resets = <&gcc GCC_PCIE_2A_PHY_BCR>;
> + reset-names = "phy";
> +
> + qcom,4ln-config-sel = <&tcsr 0xa044 0>;
> +
> + #clock-cells = <0>;
> + clock-output-names = "pcie_2a_pipe_clk";
> +
> + #phy-cells = <0>;
> +
> + status = "disabled";
> + };
> +
> ufs_mem_hc: ufs@1d84000 {
> compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc",
> "jedec,ufs-2.0";
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
PCIe4.
Signed-off-by: Johan Hovold <[email protected]>
---
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 2285c8311f0f..e8963a51e189 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -141,6 +141,22 @@ vreg_nvme: regulator-nvme {
regulator-boot-on;
};
+ vreg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC_WLAN_3R9";
+ regulator-min-microvolt = <3900000>;
+ regulator-max-microvolt = <3900000>;
+
+ gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hastings_reg_en>;
+
+ regulator-boot-on;
+ };
+
vreg_wwan: regulator-wwan {
compatible = "regulator-fixed";
@@ -304,6 +320,25 @@ &pcie3a_phy {
status = "okay";
};
+&pcie4 {
+ perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wlan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_default>;
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -646,6 +681,13 @@ edp_bl_pwm: edp-bl-pwm-state {
};
};
+&pmr735a_gpios {
+ hastings_reg_en: hastings-reg-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <70 2>, <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
@@ -729,6 +771,29 @@ wake-n-pins {
};
};
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio141";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio139";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
--
2.37.4
Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
PCIe4.
Signed-off-by: Johan Hovold <[email protected]>
---
arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
index 5b9e37a16f9f..ab5b0aadeead 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
@@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
regulator-always-on;
};
+ vreg_wlan: regulator-wlan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC_WLAN_3R9";
+ regulator-min-microvolt = <3900000>;
+ regulator-max-microvolt = <3900000>;
+
+ gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&hastings_reg_en>;
+
+ regulator-boot-on;
+ };
+
vreg_wwan: regulator-wwan {
compatible = "regulator-fixed";
@@ -246,6 +262,25 @@ &pcie3a_phy {
status = "okay";
};
+&pcie4 {
+ perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wlan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie4_default>;
+
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -445,6 +480,13 @@ edp_bl_pwm: edp-bl-pwm-state {
};
};
+&pmr735a_gpios {
+ hastings_reg_en: hastings-reg-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&tlmm {
gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
@@ -521,6 +563,29 @@ wake-n-pins {
};
};
+ pcie4_default: pcie4-default-state {
+ clkreq-n-pins {
+ pins = "gpio140";
+ function = "pcie4_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio141";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio139";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
--
2.37.4
Enable the NVMe SSD connected to PCIe2.
Signed-off-by: Johan Hovold <[email protected]>
---
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 4424d5b2c578..8fce60b0d16c 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -124,6 +124,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
regulator-boot-on;
regulator-always-on;
};
+
+ vreg_nvme: regulator-nvme {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3_SSD";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 135 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&nvme_reg_en>;
+
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -211,6 +227,13 @@ vreg_l4d: ldo4 {
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
};
+ vreg_l6d: ldo6 {
+ regulator-name = "vreg_l6d";
+ regulator-min-microvolt = <880000>;
+ regulator-max-microvolt = <880000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
vreg_l7d: ldo7 {
regulator-name = "vreg_l7d";
regulator-min-microvolt = <3072000>;
@@ -227,6 +250,25 @@ vreg_l9d: ldo9 {
};
};
+&pcie2a {
+ perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_nvme>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2a_default>;
+
+ status = "okay";
+};
+
+&pcie2a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -592,6 +634,36 @@ hall_int_state: hall-int-state {
bias-disable;
};
+ nvme_reg_en: nvme-reg-en-state {
+ pins = "gpio135";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ pcie2a_default: pcie2a-default-state {
+ clkreq-n-pins {
+ pins = "gpio142";
+ function = "pcie2a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio143";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio145";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
--
2.37.4
Enable the modem connected to the PCIe3a M.2 connector.
Signed-off-by: Johan Hovold <[email protected]>
---
.../qcom/sc8280xp-lenovo-thinkpad-x13s.dts | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
index 8fce60b0d16c..2285c8311f0f 100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-lenovo-thinkpad-x13s.dts
@@ -140,6 +140,22 @@ vreg_nvme: regulator-nvme {
regulator-boot-on;
};
+
+ vreg_wwan: regulator-wwan {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VCC3B_WAN";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&pmc8280_2_gpios 1 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&wwan_sw_en>;
+
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -269,6 +285,25 @@ &pcie2a_phy {
status = "okay";
};
+&pcie3a {
+ perst-gpios = <&tlmm 151 GPIO_ACTIVE_LOW>;
+ wake-gpios = <&tlmm 148 GPIO_ACTIVE_LOW>;
+
+ vddpe-3v3-supply = <&vreg_wwan>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie3a_default>;
+
+ status = "okay";
+};
+
+&pcie3a_phy {
+ vdda-phy-supply = <&vreg_l6d>;
+ vdda-pll-supply = <&vreg_l4d>;
+
+ status = "okay";
+};
+
&pmc8280c_lpg {
status = "okay";
};
@@ -597,6 +632,13 @@ misc_3p3_reg_en: misc-3p3-reg-en-state {
};
};
+&pmc8280_2_gpios {
+ wwan_sw_en: wwan-sw-en-state {
+ pins = "gpio1";
+ function = "normal";
+ };
+};
+
&pmc8280c_gpios {
edp_bl_pwm: edp-bl-pwm-state {
pins = "gpio8";
@@ -664,6 +706,29 @@ wake-n-pins {
};
};
+ pcie3a_default: pcie3a-default-state {
+ clkreq-n-pins {
+ pins = "gpio150";
+ function = "pcie3a_clkreq";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ perst-n-pins {
+ pins = "gpio151";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ wake-n-pins {
+ pins = "gpio148";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
qup0_i2c4_default: qup0-i2c4-default-state {
pins = "gpio171", "gpio172";
function = "qup4";
--
2.37.4
On Thu, Nov 10, 2022 at 11:35:55AM +0100, Johan Hovold wrote:
> Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
> PCIe4.
>
> Signed-off-by: Johan Hovold <[email protected]>
> ---
> arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> index 5b9e37a16f9f..ab5b0aadeead 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> @@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
> regulator-always-on;
> };
>
> + vreg_wlan: regulator-wlan {
> + compatible = "regulator-fixed";
> +
> + regulator-name = "VCC_WLAN_3R9";
> + regulator-min-microvolt = <3900000>;
> + regulator-max-microvolt = <3900000>;
> +
> + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&hastings_reg_en>;
Hastings is the family name of QCA639x WLAN chipsets. I don't think it would be
applicable here. Please use "wlan_reg_en" as that matches the convention used
throughout this file.
Thanks,
Mani
> +
> + regulator-boot-on;
> + };
> +
> vreg_wwan: regulator-wwan {
> compatible = "regulator-fixed";
>
> @@ -246,6 +262,25 @@ &pcie3a_phy {
> status = "okay";
> };
>
> +&pcie4 {
> + perst-gpios = <&tlmm 141 GPIO_ACTIVE_LOW>;
> + wake-gpios = <&tlmm 139 GPIO_ACTIVE_LOW>;
> +
> + vddpe-3v3-supply = <&vreg_wlan>;
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pcie4_default>;
> +
> + status = "okay";
> +};
> +
> +&pcie4_phy {
> + vdda-phy-supply = <&vreg_l6d>;
> + vdda-pll-supply = <&vreg_l4d>;
> +
> + status = "okay";
> +};
> +
> &pmc8280c_lpg {
> status = "okay";
> };
> @@ -445,6 +480,13 @@ edp_bl_pwm: edp-bl-pwm-state {
> };
> };
>
> +&pmr735a_gpios {
> + hastings_reg_en: hastings-reg-en-state {
> + pins = "gpio1";
> + function = "normal";
> + };
> +};
> +
> &tlmm {
> gpio-reserved-ranges = <74 6>, <83 4>, <125 2>, <128 2>, <154 7>;
>
> @@ -521,6 +563,29 @@ wake-n-pins {
> };
> };
>
> + pcie4_default: pcie4-default-state {
> + clkreq-n-pins {
> + pins = "gpio140";
> + function = "pcie4_clkreq";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> +
> + perst-n-pins {
> + pins = "gpio141";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + wake-n-pins {
> + pins = "gpio139";
> + function = "gpio";
> + drive-strength = <2>;
> + bias-pull-up;
> + };
> + };
> +
> qup0_i2c4_default: qup0-i2c4-default-state {
> pins = "gpio171", "gpio172";
> function = "qup4";
> --
> 2.37.4
>
--
மணிவண்ணன் சதாசிவம்
On Thu, Nov 10, 2022 at 05:05:13PM +0530, Manivannan Sadhasivam wrote:
> On Thu, Nov 10, 2022 at 11:35:55AM +0100, Johan Hovold wrote:
> > Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
> > PCIe4.
> >
> > Signed-off-by: Johan Hovold <[email protected]>
> > ---
> > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++
> > 1 file changed, 65 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > index 5b9e37a16f9f..ab5b0aadeead 100644
> > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > @@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
> > regulator-always-on;
> > };
> >
> > + vreg_wlan: regulator-wlan {
> > + compatible = "regulator-fixed";
> > +
> > + regulator-name = "VCC_WLAN_3R9";
> > + regulator-min-microvolt = <3900000>;
> > + regulator-max-microvolt = <3900000>;
> > +
> > + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
> > + enable-active-high;
> > +
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&hastings_reg_en>;
>
> Hastings is the family name of QCA639x WLAN chipsets. I don't think it would be
> applicable here. Please use "wlan_reg_en" as that matches the convention used
> throughout this file.
The pin name here comes from the schematics, which is what we should use
for naming when we can.
Johan
On Fri, Nov 11, 2022 at 05:27:46PM +0100, Johan Hovold wrote:
> On Thu, Nov 10, 2022 at 05:05:13PM +0530, Manivannan Sadhasivam wrote:
> > On Thu, Nov 10, 2022 at 11:35:55AM +0100, Johan Hovold wrote:
> > > Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
> > > PCIe4.
> > >
> > > Signed-off-by: Johan Hovold <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++
> > > 1 file changed, 65 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > index 5b9e37a16f9f..ab5b0aadeead 100644
> > > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > @@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
> > > regulator-always-on;
> > > };
> > >
> > > + vreg_wlan: regulator-wlan {
> > > + compatible = "regulator-fixed";
> > > +
> > > + regulator-name = "VCC_WLAN_3R9";
> > > + regulator-min-microvolt = <3900000>;
> > > + regulator-max-microvolt = <3900000>;
> > > +
> > > + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
> > > + enable-active-high;
> > > +
> > > + pinctrl-names = "default";
> > > + pinctrl-0 = <&hastings_reg_en>;
> >
> > Hastings is the family name of QCA639x WLAN chipsets. I don't think it would be
> > applicable here. Please use "wlan_reg_en" as that matches the convention used
> > throughout this file.
>
> The pin name here comes from the schematics, which is what we should use
> for naming when we can.
>
Following the naming in the schematics is the right thing to do.
Regards,
Bjorn
On Thu, 10 Nov 2022 11:35:49 +0100, Johan Hovold wrote:
> This series adds support for PCIe to the SC8280XP and SA840P platforms
> and specifically enables the NVMe SSD, modem and WiFi controller on the
> SC8280XP-CRD and Lenovo Thinkpad X13s.
>
> Note that these patches depend on the PCIe QMP PHY support that was
> merged this morning:
>
> [...]
Applied, thanks!
[1/9] arm64: dts: qcom: sc8280xp/sa8540p: add PCIe2-4 nodes
commit: 813e831570017bfbab8ccb898a46349c2df3f0f1
[2/9] arm64: dts: qcom: sa8295p-adp: enable PCIe
commit: c35d4d7128726e7c8160bedd9ed5b309978bdeb3
[3/9] arm64: dts: qcom: sc8280xp-crd: rename backlight and misc regulators
commit: 5634c6d9771df48838384b14592a00a1e7da8fdf
[4/9] arm64: dts: qcom: sc8280xp-crd: enable NVMe SSD
commit: 6a1ec5eca73c0ca8cdefd13426bf812c65a1e510
[5/9] arm64: dts: qcom: sc8280xp-crd: enable SDX55 modem
commit: 17e2ccaf65d16848b27793853af8f42ae524219f
[6/9] arm64: dts: qcom: sc8280xp-crd: enable WiFi controller
commit: d907fe5acbf1061f86936485d604c229e68ae312
[7/9] arm64: dts: qcom: sc8280xp-x13s: enable NVMe SSD
commit: b4bb952e6cfc13f86b4b52c3039b199dd3f16020
[8/9] arm64: dts: qcom: sc8280xp-x13s: enable modem
commit: 176d54acd5d9c79bb6b51dbe2550a3b0441353bf
[9/9] arm64: dts: qcom: sc8280xp-x13s: enable WiFi controller
commit: 123b30a75623f7131af0f0fa2bee330be65f1ead
Best regards,
--
Bjorn Andersson <[email protected]>
On Fri, Nov 11, 2022 at 02:40:21PM -0600, Bjorn Andersson wrote:
> On Fri, Nov 11, 2022 at 05:27:46PM +0100, Johan Hovold wrote:
> > On Thu, Nov 10, 2022 at 05:05:13PM +0530, Manivannan Sadhasivam wrote:
> > > On Thu, Nov 10, 2022 at 11:35:55AM +0100, Johan Hovold wrote:
> > > > Enable the Qualcomm QCNFA765 Wireless Network Adapter connected to
> > > > PCIe4.
> > > >
> > > > Signed-off-by: Johan Hovold <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/qcom/sc8280xp-crd.dts | 65 +++++++++++++++++++++++
> > > > 1 file changed, 65 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > > index 5b9e37a16f9f..ab5b0aadeead 100644
> > > > --- a/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > > +++ b/arch/arm64/boot/dts/qcom/sc8280xp-crd.dts
> > > > @@ -81,6 +81,22 @@ vreg_misc_3p3: regulator-misc-3p3 {
> > > > regulator-always-on;
> > > > };
> > > >
> > > > + vreg_wlan: regulator-wlan {
> > > > + compatible = "regulator-fixed";
> > > > +
> > > > + regulator-name = "VCC_WLAN_3R9";
> > > > + regulator-min-microvolt = <3900000>;
> > > > + regulator-max-microvolt = <3900000>;
> > > > +
> > > > + gpio = <&pmr735a_gpios 1 GPIO_ACTIVE_HIGH>;
> > > > + enable-active-high;
> > > > +
> > > > + pinctrl-names = "default";
> > > > + pinctrl-0 = <&hastings_reg_en>;
> > >
> > > Hastings is the family name of QCA639x WLAN chipsets. I don't think it would be
> > > applicable here. Please use "wlan_reg_en" as that matches the convention used
> > > throughout this file.
> >
> > The pin name here comes from the schematics, which is what we should use
> > for naming when we can.
If hastings is what mentioned in the schematics then it is fine (I can see that
now). For a moment I thought it came from downstream...
Thanks,
Mani
> >
>
> Following the naming in the schematics is the right thing to do.
>
> Regards,
> Bjorn
--
மணிவண்ணன் சதாசிவம்