Hi,
On J721e platform, the 2 lanes of SERDES PHY are used to achieve
USB Type-C plug flip support without any additional MUX component
by using a lane swap feature.
However, the driver needs to know the Type-C plug orientation before
it can decide whether to swap the lanes or not. This is achieved via a
GPIO named DIR.
Another constraint is that the lane swap must happen only when the PHY
is in inactive state. This is achieved by sampling the GPIO and
programming the lane swap before bringing the PHY out of reset.
This series adds support to read the GPIO and accordingly program
the Lane swap for Type-C plug flip support.
Series must be applied on top of
https://lkml.org/lkml/2019/10/16/517
cheers,
-roger
Changelog:
v2
- revise commit log of patch 1
- use regmap_field in patch 3
Roger Quadros (3):
phy: cadence: Sierra: add phy_reset hook
dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
phy: ti: j721e-wiz: Manage typec-gpio-dir
.../bindings/phy/ti,phy-j721e-wiz.txt | 9 ++++
drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++
drivers/phy/ti/phy-j721e-wiz.c | 48 +++++++++++++++++++
3 files changed, 67 insertions(+)
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Based on this GPIO state we need to configure LN10
bit to swap lane0 and lane1 if required (flipped connector).
Type-C companions typically need some time after the cable is
plugged before and before they reflect the correct status of
Type-C plug orientation on the DIR line.
Type-C Spec specifies CC attachment debounce time (tCCDebounce)
of 100 ms (min) to 200 ms (max).
Use the DT property to figure out if we need to add delay
or not before sampling the Type-C DIR line.
Signed-off-by: Roger Quadros <[email protected]>
Signed-off-by: Sekhar Nori <[email protected]>
---
drivers/phy/ti/phy-j721e-wiz.c | 48 ++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 2a95da843e9f..02b949406b7b 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -9,6 +9,8 @@
#include <dt-bindings/phy/phy.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
+#include <linux/gpio.h>
+#include <linux/gpio/consumer.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/mux/consumer.h>
@@ -22,6 +24,7 @@
#define WIZ_SERDES_CTRL 0x404
#define WIZ_SERDES_TOP_CTRL 0x408
#define WIZ_SERDES_RST 0x40c
+#define WIZ_SERDES_TYPEC 0x410
#define WIZ_LANECTL(n) (0x480 + (0x40 * (n)))
#define WIZ_MAX_LANES 4
@@ -29,6 +32,8 @@
#define WIZ_DIV_NUM_CLOCKS_16G 2
#define WIZ_DIV_NUM_CLOCKS_10G 1
+#define WIZ_SERDES_TYPEC_LN10_SWAP BIT(30)
+
enum wiz_lane_standard_mode {
LANE_MODE_GEN1,
LANE_MODE_GEN2,
@@ -94,6 +99,9 @@ static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
REG_FIELD(WIZ_LANECTL(3), 24, 25),
};
+static const struct reg_field typec_ln10_swap =
+ REG_FIELD(WIZ_SERDES_TYPEC, 30, 30);
+
struct wiz_clk_mux {
struct clk_hw hw;
struct regmap_field *field;
@@ -201,11 +209,14 @@ struct wiz {
struct regmap_field *pma_cmn_refclk_mode;
struct regmap_field *pma_cmn_refclk_dig_div;
struct regmap_field *pma_cmn_refclk1_dig_div;
+ struct regmap_field *typec_ln10_swap;
struct device *dev;
u32 num_lanes;
struct platform_device *serdes_pdev;
struct reset_controller_dev wiz_phy_reset_dev;
+ struct gpio_desc *gpio_typec_dir;
+ int typec_dir_delay;
};
static int wiz_reset(struct wiz *wiz)
@@ -404,6 +415,13 @@ static int wiz_regfield_init(struct wiz *wiz)
}
}
+ wiz->typec_ln10_swap = devm_regmap_field_alloc(dev, regmap,
+ typec_ln10_swap);
+ if (IS_ERR(wiz->typec_ln10_swap)) {
+ dev_err(dev, "LN10_SWAP reg field init failed\n");
+ return PTR_ERR(wiz->typec_ln10_swap);
+ }
+
return 0;
}
@@ -703,6 +721,17 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,
struct wiz *wiz = dev_get_drvdata(dev);
int ret;
+ /* if typec-dir gpio was specified, set LN10 SWAP bit based on that */
+ if (id == 0 && wiz->gpio_typec_dir) {
+ if (wiz->typec_dir_delay)
+ msleep_interruptible(wiz->typec_dir_delay);
+
+ if (gpiod_get_value_cansleep(wiz->gpio_typec_dir))
+ regmap_field_write(wiz->typec_ln10_swap, 1);
+ else
+ regmap_field_write(wiz->typec_ln10_swap, 0);
+ }
+
if (id == 0) {
ret = regmap_field_write(wiz->phy_reset_n, true);
return ret;
@@ -789,6 +818,25 @@ static int wiz_probe(struct platform_device *pdev)
goto err_addr_to_resource;
}
+ wiz->gpio_typec_dir = devm_gpiod_get_optional(dev, "typec-dir",
+ GPIOD_IN);
+ if (IS_ERR(wiz->gpio_typec_dir)) {
+ ret = PTR_ERR(wiz->gpio_typec_dir);
+ if (ret != -EPROBE_DEFER)
+ dev_err(dev, "Failed to request typec-dir gpio: %d\n",
+ ret);
+ goto err_addr_to_resource;
+ }
+
+ if (wiz->gpio_typec_dir) {
+ ret = of_property_read_u32(node, "typec-dir-debounce",
+ &wiz->typec_dir_delay);
+ if (ret && ret != -EINVAL) {
+ dev_err(dev, "Invalid typec-dir-debounce property\n");
+ goto err_addr_to_resource;
+ }
+ }
+
wiz->dev = dev;
wiz->regmap = regmap;
wiz->num_lanes = num_lanes;
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
On 23/10/2019 11:49, Roger Quadros wrote:
> Hi,
>
> On J721e platform, the 2 lanes of SERDES PHY are used to achieve
> USB Type-C plug flip support without any additional MUX component
> by using a lane swap feature.
>
> However, the driver needs to know the Type-C plug orientation before
> it can decide whether to swap the lanes or not. This is achieved via a
> GPIO named DIR.
>
> Another constraint is that the lane swap must happen only when the PHY
> is in inactive state. This is achieved by sampling the GPIO and
> programming the lane swap before bringing the PHY out of reset.
>
> This series adds support to read the GPIO and accordingly program
> the Lane swap for Type-C plug flip support.
>
> Series must be applied on top of
> https://lkml.org/lkml/2019/10/16/517
>
> cheers,
> -roger
>
> Changelog:
> v2
> - revise commit log of patch 1
> - use regmap_field in patch 3
>
Reviewed-by: Jyri Sarha <[email protected]>
For the whole series.
> Roger Quadros (3):
> phy: cadence: Sierra: add phy_reset hook
> dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO
> phy: ti: j721e-wiz: Manage typec-gpio-dir
>
> .../bindings/phy/ti,phy-j721e-wiz.txt | 9 ++++
> drivers/phy/cadence/phy-cadence-sierra.c | 10 ++++
> drivers/phy/ti/phy-j721e-wiz.c | 48 +++++++++++++++++++
> 3 files changed, 67 insertions(+)
>
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki.
Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki