Hi,
This series contains patches related to the support of mt8365 iommu.
Thanks for your feedback so far.
Regards,
Alex
Changes in v4:
- Typo
- Rebase
- Link to v3: https://lore.kernel.org/r/[email protected]
Changes in v3:
- Rename "mt8365-larb-port.h" to "mediatek,mt8365-larb-port.h"
- Rework the macros which retrieve larb/port ID to improve human readability
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
- Rebase.
- Change M4U_PORT_APU_READ & M4U_PORT_APU_WRITE port to avoid display
conflict in larb0. These definitions are used for vpu0 device node.
- Add dual license.
- Retitle commit.
- Rename to int_id_port_width for more detail.
- Fix typo.
- Set banks_enable and banks_num in mt8365_data to fix kernel panic at boot.
- Link to v1 - https://lore.kernel.org/lkml/[email protected]/
To: Yong Wu <[email protected]>
To: Joerg Roedel <[email protected]>
To: Will Deacon <[email protected]>
To: Robin Murphy <[email protected]>
To: Rob Herring <[email protected]>
To: Krzysztof Kozlowski <[email protected]>
To: Matthias Brugger <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Fabien Parent <[email protected]>
Cc: Markus Schneider-Pargmann <[email protected]>
Cc: Amjad Ouled-Ameur <[email protected]>
Cc: AngeloGioacchino Del Regno <[email protected]>
Cc: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
Fabien Parent (3):
dt-bindings: iommu: mediatek: add binding documentation for MT8365 SoC
iommu/mediatek: add support for 6-bit encoded port IDs
iommu/mediatek: add support for MT8365 SoC
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
drivers/iommu/mtk_iommu.c | 30 +++++++-
.../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
3 files changed, 120 insertions(+), 2 deletions(-)
---
base-commit: 11082343e3bf2953a937509f0316cabf69dbf908
change-id: 20221001-iommu-support-f409c7e094e6
Best regards,
--
Alexandre Mergnat <[email protected]>
From: Fabien Parent <[email protected]>
Until now the port ID was always encoded as a 5-bit data. On MT8365,
the port ID is encoded as a 6-bit data. This requires to add extra
macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
to support 6-bit encoded port IDs.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/iommu/mtk_iommu.c | 17 +++++++++++++++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 5a4e00e4bbbc..50195a900611 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -108,8 +108,12 @@
#define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
#define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
#define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) & 0x7)
+/* Macro for 5 bits length port ID field (default) */
#define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) & 0x7)
#define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) & 0x1f)
+/* Macro for 6 bits length port ID field */
+#define F_MMU_INT_ID_LARB_ID_EXT(a) (((a) >> 8) & 0x7)
+#define F_MMU_INT_ID_PORT_ID_EXT(a) (((a) >> 2) & 0x3f)
#define MTK_PROTECT_PA_ALIGN 256
#define MTK_IOMMU_BANK_SZ 0x1000
@@ -139,6 +143,7 @@
#define IFA_IOMMU_PCIE_SUPPORT BIT(16)
#define PGTABLE_PA_35_EN BIT(17)
#define TF_PORT_TO_ADDR_MT8173 BIT(18)
+#define HAS_INT_ID_PORT_WIDTH_6 BIT(19)
#define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
((((pdata)->flags) & (mask)) == (_x))
@@ -441,7 +446,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_pa |= (u64)pa34_32 << 32;
if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
- fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) {
+ fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
+ } else {
+ fault_port = F_MMU_INT_ID_PORT_ID(regval);
+ }
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
fault_larb = F_MMU_INT_ID_COMM_ID(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
@@ -449,7 +458,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void *dev_id)
fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
sub_comm = F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
} else {
- fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) {
+ fault_larb = F_MMU_INT_ID_LARB_ID_EXT(regval);
+ } else {
+ fault_larb = F_MMU_INT_ID_LARB_ID(regval);
+ }
}
fault_larb = data->plat_data->larbid_remap[fault_larb][sub_comm];
}
--
b4 0.10.1
From: Fabien Parent <[email protected]>
Add IOMMU binding documentation for the MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
.../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
.../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90 ++++++++++++++++++++++
2 files changed, 92 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b5098..4b8cf3ce6963 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -81,6 +81,7 @@ properties:
- mediatek,mt8195-iommu-vdo # generation two
- mediatek,mt8195-iommu-vpp # generation two
- mediatek,mt8195-iommu-infra # generation two
+ - mediatek,mt8365-m4u # generation two
- description: mt7623 generation one
items:
@@ -130,6 +131,7 @@ properties:
dt-binding/memory/mt8186-memory-port.h for mt8186,
dt-binding/memory/mt8192-larb-port.h for mt8192.
dt-binding/memory/mt8195-memory-port.h for mt8195.
+ dt-binding/memory/mt8365-larb-port.h for mt8365.
power-domains:
maxItems: 1
diff --git a/include/dt-bindings/memory/mediatek,mt8365-larb-port.h b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
new file mode 100644
index 000000000000..56d5a5dd519e
--- /dev/null
+++ b/include/dt-bindings/memory/mediatek,mt8365-larb-port.h
@@ -0,0 +1,90 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2022 MediaTek Inc.
+ * Author: Yong Wu <[email protected]>
+ */
+#ifndef _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+#define _DT_BINDINGS_MEMORY_MT8365_LARB_PORT_H_
+
+#include <dt-bindings/memory/mtk-memory-port.h>
+
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
+#define M4U_LARB3_ID 3
+
+/* larb0 */
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_OVL0_2L MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WROT1 MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_MDP_WROT0 MTK_M4U_ID(M4U_LARB0_ID, 7)
+#define M4U_PORT_MDP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 8)
+#define M4U_PORT_DISP_FAKE0 MTK_M4U_ID(M4U_LARB0_ID, 9)
+#define M4U_PORT_APU_READ MTK_M4U_ID(M4U_LARB0_ID, 10)
+#define M4U_PORT_APU_WRITE MTK_M4U_ID(M4U_LARB0_ID, 11)
+
+/* larb1 */
+#define M4U_PORT_VENC_RCPU MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_VENC_SV_COMV MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_VENC_NBM_RDMA MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_VENC_NBM_RDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_JPGENC_Y_RDMA MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_JPGENC_C_RDMA MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_JPGENC_Q_TABLE MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_JPGENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_JPGDEC_WDMA MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_JPGDEC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 12)
+#define M4U_PORT_VENC_NBM_WDMA MTK_M4U_ID(M4U_LARB1_ID, 13)
+#define M4U_PORT_VENC_NBM_WDMA_LITE MTK_M4U_ID(M4U_LARB1_ID, 14)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 15)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 16)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 17)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 18)
+
+/* larb2 */
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_CAM_RRZO MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_CAM_LCS MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_CAM_CAM_SV0 MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_CAM_CAM_SV1 MTK_M4U_ID(M4U_LARB2_ID, 6)
+#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB2_ID, 7)
+#define M4U_PORT_CAM_LSCI_D MTK_M4U_ID(M4U_LARB2_ID, 8)
+#define M4U_PORT_CAM_AFO MTK_M4U_ID(M4U_LARB2_ID, 9)
+#define M4U_PORT_CAM_SPARE MTK_M4U_ID(M4U_LARB2_ID, 10)
+#define M4U_PORT_CAM_BPCI MTK_M4U_ID(M4U_LARB2_ID, 11)
+#define M4U_PORT_CAM_BPCI_D MTK_M4U_ID(M4U_LARB2_ID, 12)
+#define M4U_PORT_CAM_UFDI MTK_M4U_ID(M4U_LARB2_ID, 13)
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB2_ID, 14)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB2_ID, 15)
+#define M4U_PORT_CAM_IMG3O MTK_M4U_ID(M4U_LARB2_ID, 16)
+#define M4U_PORT_CAM_WPE0_I MTK_M4U_ID(M4U_LARB2_ID, 17)
+#define M4U_PORT_CAM_WPE1_I MTK_M4U_ID(M4U_LARB2_ID, 18)
+#define M4U_PORT_CAM_WPE_O MTK_M4U_ID(M4U_LARB2_ID, 19)
+#define M4U_PORT_CAM_FD0_I MTK_M4U_ID(M4U_LARB2_ID, 20)
+#define M4U_PORT_CAM_FD1_I MTK_M4U_ID(M4U_LARB2_ID, 21)
+#define M4U_PORT_CAM_FD0_O MTK_M4U_ID(M4U_LARB2_ID, 22)
+#define M4U_PORT_CAM_FD1_O MTK_M4U_ID(M4U_LARB2_ID, 23)
+
+/* larb3 */
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB3_ID, 0)
+#define M4U_PORT_HW_VDEC_UFO_EXT MTK_M4U_ID(M4U_LARB3_ID, 1)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB3_ID, 2)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB3_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB3_ID, 4)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB3_ID, 5)
+#define M4U_PORT_HW_VDEC_TILE_EXT MTK_M4U_ID(M4U_LARB3_ID, 6)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB3_ID, 7)
+#define M4U_PORT_HW_VDEC_VLD2_EXT MTK_M4U_ID(M4U_LARB3_ID, 8)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB3_ID, 9)
+#define M4U_PORT_HW_VDEC_RG_CTRL_DMA_EXT MTK_M4U_ID(M4U_LARB3_ID, 10)
+
+#endif
--
b4 0.10.1
From: Fabien Parent <[email protected]>
Add IOMMU support for MT8365 SoC.
Signed-off-by: Fabien Parent <[email protected]>
Reviewed-by: Amjad Ouled-Ameur <[email protected]>
Tested-by: Amjad Ouled-Ameur <[email protected]>
Signed-off-by: Markus Schneider-Pargmann <[email protected]>
Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Alexandre Mergnat <[email protected]>
---
drivers/iommu/mtk_iommu.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index 50195a900611..051ed5234538 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -170,6 +170,7 @@ enum mtk_iommu_plat {
M4U_MT8186,
M4U_MT8192,
M4U_MT8195,
+ M4U_MT8365,
};
struct mtk_iommu_iova_region {
@@ -1528,6 +1529,17 @@ static const struct mtk_iommu_plat_data mt8195_data_vpp = {
{4, MTK_INVALID_LARBID, MTK_INVALID_LARBID, MTK_INVALID_LARBID, 6}},
};
+static const struct mtk_iommu_plat_data mt8365_data = {
+ .m4u_plat = M4U_MT8365,
+ .flags = RESET_AXI | HAS_INT_ID_PORT_WIDTH_6,
+ .inv_sel_reg = REG_MMU_INV_SEL_GEN1,
+ .banks_num = 1,
+ .banks_enable = {true},
+ .iova_region = single_domain,
+ .iova_region_nr = ARRAY_SIZE(single_domain),
+ .larbid_remap = {{0}, {1}, {2}, {3}, {4}, {5}}, /* Linear mapping. */
+};
+
static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1540,6 +1552,7 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
{ .compatible = "mediatek,mt8195-iommu-vdo", .data = &mt8195_data_vdo},
{ .compatible = "mediatek,mt8195-iommu-vpp", .data = &mt8195_data_vpp},
+ { .compatible = "mediatek,mt8365-m4u", .data = &mt8365_data},
{}
};
--
b4 0.10.1
On Fri, 2022-10-14 at 10:45 +0200, Alexandre Mergnat wrote:
> From: Fabien Parent <[email protected]>
>
> Add IOMMU binding documentation for the MT8365 SoC.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <
> [email protected]>
> Acked-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> .../devicetree/bindings/iommu/mediatek,iommu.yaml | 2 +
> .../dt-bindings/memory/mediatek,mt8365-larb-port.h | 90
> ++++++++++++++++++++++
> 2 files changed, 92 insertions(+)
>
> diff --git
> a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> index fee0241b5098..4b8cf3ce6963 100644
> --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
> @@ -81,6 +81,7 @@ properties:
> - mediatek,mt8195-iommu-vdo # generation two
> - mediatek,mt8195-iommu-vpp # generation two
> - mediatek,mt8195-iommu-infra # generation two
> + - mediatek,mt8365-m4u # generation two
>
> - description: mt7623 generation one
> items:
> @@ -130,6 +131,7 @@ properties:
> dt-binding/memory/mt8186-memory-port.h for mt8186,
> dt-binding/memory/mt8192-larb-port.h for mt8192.
> dt-binding/memory/mt8195-memory-port.h for mt8195.
> + dt-binding/memory/mt8365-larb-port.h for mt8365.
"mediatek," is needed here.
After this:
Reviewed-by: Yong Wu <[email protected]>
On Fri, 2022-10-14 at 10:45 +0200, Alexandre Mergnat wrote:
> From: Fabien Parent <[email protected]>
>
> Add IOMMU support for MT8365 SoC.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Reviewed-by: Amjad Ouled-Ameur <[email protected]>
> Tested-by: Amjad Ouled-Ameur <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <
> [email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
Reviewed-by: Yong Wu <[email protected]>
On Fri, 2022-10-14 at 10:45 +0200, Alexandre Mergnat wrote:
> From: Fabien Parent <[email protected]>
>
> Until now the port ID was always encoded as a 5-bit data. On MT8365,
> the port ID is encoded as a 6-bit data. This requires to add extra
> macro F_MMU_INT_ID_LARB_ID_EXT, and F_MMU_INT_ID_PORT_ID_EXT in order
> to support 6-bit encoded port IDs.
>
> Signed-off-by: Fabien Parent <[email protected]>
> Signed-off-by: Markus Schneider-Pargmann <[email protected]>
> Reviewed-by: AngeloGioacchino Del Regno <
> [email protected]>
> Signed-off-by: Alexandre Mergnat <[email protected]>
> ---
> drivers/iommu/mtk_iommu.c | 17 +++++++++++++++--
> 1 file changed, 15 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
> index 5a4e00e4bbbc..50195a900611 100644
> --- a/drivers/iommu/mtk_iommu.c
> +++ b/drivers/iommu/mtk_iommu.c
> @@ -108,8 +108,12 @@
> #define F_MMU_INT_ID_SUB_COMM_ID(a) (((a) >> 7) & 0x3)
> #define F_MMU_INT_ID_COMM_ID_EXT(a) (((a) >> 10) & 0x7)
> #define F_MMU_INT_ID_SUB_COMM_ID_EXT(a) (((a) >> 7) &
> 0x7)
> +/* Macro for 5 bits length port ID field (default) */
> #define F_MMU_INT_ID_LARB_ID(a) (((a) >> 7) &
> 0x7)
> #define F_MMU_INT_ID_PORT_ID(a) (((a) >> 2) &
> 0x1f)
> +/* Macro for 6 bits length port ID field */
> +#define F_MMU_INT_ID_LARB_ID_EXT(a) (((a) >> 8) & 0x7)
> +#define F_MMU_INT_ID_PORT_ID_EXT(a) (((a) >> 2) & 0x3f)
So far only mt8365 use 6 bits here. We could rename more detailly:
like F_MMU_INT_ID_PORT_ID_MT8365 or keep consistent with the below flag
name: F_MMU_INT_ID_PORT_ID_WID_6.
>
> #define MTK_PROTECT_PA_ALIGN 256
> #define MTK_IOMMU_BANK_SZ 0x1000
> @@ -139,6 +143,7 @@
> #define IFA_IOMMU_PCIE_SUPPORT BIT(16)
> #define PGTABLE_PA_35_EN BIT(17)
> #define TF_PORT_TO_ADDR_MT8173 BIT(18)
> +#define HAS_INT_ID_PORT_WIDTH_6 BIT(19)
HAS_SUB_COM means the SoC has SMI sub_common. this only indicate
port width is 6bits. No need "HAS_". I think INT_ID_PORT_WIDTH_6 is ok.
>
> #define MTK_IOMMU_HAS_FLAG_MASK(pdata, _x, mask) \
> ((((pdata)->flags) & (mask)) == (_x))
> @@ -441,7 +446,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void
> *dev_id)
> fault_pa |= (u64)pa34_32 << 32;
>
> if (MTK_IOMMU_IS_TYPE(plat_data, MTK_IOMMU_TYPE_MM)) {
> - fault_port = F_MMU_INT_ID_PORT_ID(regval);
> + if (MTK_IOMMU_HAS_FLAG(plat_data,
> HAS_INT_ID_PORT_WIDTH_6)) {
> + fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
> + } else {
> + fault_port = F_MMU_INT_ID_PORT_ID(regval);
> + }
> if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS))
> {
> fault_larb = F_MMU_INT_ID_COMM_ID(regval);
> sub_comm = F_MMU_INT_ID_SUB_COMM_ID(regval);
> @@ -449,7 +458,11 @@ static irqreturn_t mtk_iommu_isr(int irq, void
> *dev_id)
> fault_larb = F_MMU_INT_ID_COMM_ID_EXT(regval);
> sub_comm =
> F_MMU_INT_ID_SUB_COMM_ID_EXT(regval);
> } else {
> - fault_larb = F_MMU_INT_ID_LARB_ID(regval);
> + if (MTK_IOMMU_HAS_FLAG(plat_data,
> HAS_INT_ID_PORT_WIDTH_6)) {
> + fault_larb =
> F_MMU_INT_ID_LARB_ID_EXT(regval);
> + } else {
> + fault_larb =
> F_MMU_INT_ID_LARB_ID(regval);
> + }
> }
It has two checking about this new flag. How about this?
if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_2BITS)) {
fault_larb
= x
sub_com = x
fault_port = F_MMU_INT_ID_PORT_ID(regval); //New add
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_SUB_COMM_3BITS)) {
fault_larb = x
sub_com = x
fault_port= F_MMU_INT_ID_PORT_ID(regval); //New add
} else if (MTK_IOMMU_HAS_FLAG(plat_data, HAS_INT_ID_PORT_WIDTH_6)) { /*
mt8365 */
fault_port = F_MMU_INT_ID_PORT_ID_EXT(regval);
fault_larb =
F_MMU_INT_ID_LARB_ID_EXT(regval);
} else {
fault_larb = F_MMU_INT_ID_LARB_ID(regval);
fault_port = F_MMU_INT_ID_PORT_ID(regval);
}
> fault_larb = data->plat_data-
> >larbid_remap[fault_larb][sub_comm];
> }
>