Add a compatible for RPMCC on SM6375.
Signed-off-by: Konrad Dybcio <[email protected]>
---
Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
index 9d296b89a8d0..f22febdfdce7 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
@@ -43,6 +43,7 @@ properties:
- qcom,rpmcc-sdm660
- qcom,rpmcc-sm6115
- qcom,rpmcc-sm6125
+ - qcom,sm6375-rpmcc
- const: qcom,rpmcc
'#clock-cells':
--
2.37.0
Add support for controlling SMD RPM clocks on SM6375.
Signed-off-by: Konrad Dybcio <[email protected]>
---
drivers/clk/qcom/clk-smd-rpm.c | 46 ++++++++++++++++++++++++++++++--
include/linux/soc/qcom/smd-rpm.h | 1 +
2 files changed, 45 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index 10b4e6d8d10f..b221dd474218 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -1085,13 +1085,54 @@ static const struct rpm_smd_clk_desc rpm_clk_sm6115 = {
.num_clks = ARRAY_SIZE(sm6115_clks),
};
+/* SM6375 */
+DEFINE_CLK_SMD_RPM(sm6375, mmnrt_clk, mmnrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 0);
+DEFINE_CLK_SMD_RPM(sm6375, mmrt_clk, mmrt_a_clk, QCOM_SMD_RPM_MMXI_CLK, 1);
+DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
+DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
+DEFINE_CLK_SMD_RPM_BRANCH(sm6375, bimc_freq_log, bimc_freq_log_a, QCOM_SMD_RPM_MISC_CLK, 4, 1);
+static struct clk_smd_rpm *sm6375_clks[] = {
+ [RPM_SMD_XO_CLK_SRC] = &sdm660_bi_tcxo,
+ [RPM_SMD_XO_A_CLK_SRC] = &sdm660_bi_tcxo_a,
+ [RPM_SMD_SNOC_CLK] = &sm6125_snoc_clk,
+ [RPM_SMD_SNOC_A_CLK] = &sm6125_snoc_a_clk,
+ [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
+ [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
+ [RPM_SMD_QDSS_CLK] = &sm6125_qdss_clk,
+ [RPM_SMD_QDSS_A_CLK] = &sm6125_qdss_a_clk,
+ [RPM_SMD_CNOC_CLK] = &sm6125_cnoc_clk,
+ [RPM_SMD_CNOC_A_CLK] = &sm6125_cnoc_a_clk,
+ [RPM_SMD_IPA_CLK] = &msm8976_ipa_clk,
+ [RPM_SMD_IPA_A_CLK] = &msm8976_ipa_a_clk,
+ [RPM_SMD_QUP_CLK] = &sm6125_qup_clk,
+ [RPM_SMD_QUP_A_CLK] = &sm6125_qup_a_clk,
+ [RPM_SMD_MMRT_CLK] = &sm6375_mmrt_clk,
+ [RPM_SMD_MMRT_A_CLK] = &sm6375_mmrt_a_clk,
+ [RPM_SMD_MMNRT_CLK] = &sm6375_mmnrt_clk,
+ [RPM_SMD_MMNRT_A_CLK] = &sm6375_mmnrt_a_clk,
+ [RPM_SMD_SNOC_PERIPH_CLK] = &sm6125_snoc_periph_clk,
+ [RPM_SMD_SNOC_PERIPH_A_CLK] = &sm6125_snoc_periph_a_clk,
+ [RPM_SMD_SNOC_LPASS_CLK] = &sm6125_snoc_lpass_clk,
+ [RPM_SMD_SNOC_LPASS_A_CLK] = &sm6125_snoc_lpass_a_clk,
+ [RPM_SMD_CE1_CLK] = &msm8992_ce1_clk,
+ [RPM_SMD_CE1_A_CLK] = &msm8992_ce1_a_clk,
+ [RPM_SMD_HWKM_CLK] = &qcm2290_hwkm_clk,
+ [RPM_SMD_HWKM_A_CLK] = &qcm2290_hwkm_a_clk,
+ [RPM_SMD_PKA_CLK] = &qcm2290_pka_clk,
+ [RPM_SMD_PKA_A_CLK] = &qcm2290_pka_a_clk,
+ [RPM_SMD_BIMC_FREQ_LOG] = &sm6375_bimc_freq_log,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_sm6375 = {
+ .clks = sm6375_clks,
+ .num_clks = ARRAY_SIZE(sm6375_clks),
+};
+
/* QCM2290 */
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, ln_bb_clk2, ln_bb_clk2_a, 0x2, 19200000);
DEFINE_CLK_SMD_RPM_XO_BUFFER(qcm2290, rf_clk3, rf_clk3_a, 6, 38400000);
DEFINE_CLK_SMD_RPM(qcm2290, qpic_clk, qpic_a_clk, QCOM_SMD_RPM_QPIC_CLK, 0);
-DEFINE_CLK_SMD_RPM(qcm2290, hwkm_clk, hwkm_a_clk, QCOM_SMD_RPM_HWKM_CLK, 0);
-DEFINE_CLK_SMD_RPM(qcm2290, pka_clk, pka_a_clk, QCOM_SMD_RPM_PKA_CLK, 0);
DEFINE_CLK_SMD_RPM(qcm2290, cpuss_gnoc_clk, cpuss_gnoc_a_clk,
QCOM_SMD_RPM_MEM_CLK, 1);
DEFINE_CLK_SMD_RPM(qcm2290, bimc_gpu_clk, bimc_gpu_a_clk,
@@ -1160,6 +1201,7 @@ static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-sdm660", .data = &rpm_clk_sdm660 },
{ .compatible = "qcom,rpmcc-sm6115", .data = &rpm_clk_sm6115 },
{ .compatible = "qcom,rpmcc-sm6125", .data = &rpm_clk_sm6125 },
+ { .compatible = "qcom,sm6375-rpmcc", .data = &rpm_clk_sm6375 },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
diff --git a/include/linux/soc/qcom/smd-rpm.h b/include/linux/soc/qcom/smd-rpm.h
index 82c9d489833a..3ab8c07f71c0 100644
--- a/include/linux/soc/qcom/smd-rpm.h
+++ b/include/linux/soc/qcom/smd-rpm.h
@@ -41,6 +41,7 @@ struct qcom_smd_rpm;
#define QCOM_SMD_RPM_HWKM_CLK 0x6d6b7768
#define QCOM_SMD_RPM_PKA_CLK 0x616b70
#define QCOM_SMD_RPM_MCFG_CLK 0x6766636d
+#define QCOM_SMD_RPM_MMXI_CLK 0x69786d6d
int qcom_rpm_smd_write(struct qcom_smd_rpm *rpm,
int state,
--
2.37.0
Add the missing definition for the aforementioned clock.
Signed-off-by: Konrad Dybcio <[email protected]>
---
include/dt-bindings/clock/qcom,rpmcc.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 015db95303d1..c0ad624e930e 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -167,5 +167,6 @@
#define RPM_SMD_CPUSS_GNOC_A_CLK 121
#define RPM_SMD_MSS_CFG_AHB_CLK 122
#define RPM_SMD_MSS_CFG_AHB_A_CLK 123
+#define RPM_SMD_BIMC_FREQ_LOG 124
#endif
--
2.37.0
Quoting Konrad Dybcio (2022-07-16 12:27:13)
> Add the missing definition for the aforementioned clock.
>
What does the bimc freq log do?
On 19.07.2022 09:13, Stephen Boyd wrote:
> Quoting Konrad Dybcio (2022-07-16 12:27:13)
>> Add the missing definition for the aforementioned clock.
>>
>
> What does the bimc freq log do?
It does not seem used by any driver downstream, not from a quick glance at
least. It is however exposed on the downstream kernel and here's what
debugfs has to say about it on mainline:
clk_accuracy:0
clk_duty_cycle:1/2
clk_enable_count:0
clk_max_rate:18446744073709551615
clk_min_rate:0
clk_notifier_count:0
clk_parent:xo_board
clk_phase:0
clk_prepare_count:0
clk_protect_count:0
clk_rate:1
Konrad
On 16/07/2022 21:27, Konrad Dybcio wrote:
> Add a compatible for RPMCC on SM6375.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> index 9d296b89a8d0..f22febdfdce7 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> @@ -43,6 +43,7 @@ properties:
> - qcom,rpmcc-sdm660
> - qcom,rpmcc-sm6115
> - qcom,rpmcc-sm6125
> + - qcom,sm6375-rpmcc
I am fine with it, although this contradicts a bit
https://lore.kernel.org/all/[email protected]/
Would be nice to get Bjorn's opinion/preference on this.
Acked-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On Wed, Jul 20, 2022 at 08:30:13AM +0200, Krzysztof Kozlowski wrote:
> On 16/07/2022 21:27, Konrad Dybcio wrote:
> > Add a compatible for RPMCC on SM6375.
> >
> > Signed-off-by: Konrad Dybcio <[email protected]>
> > ---
> > Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml | 1 +
> > 1 file changed, 1 insertion(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> > index 9d296b89a8d0..f22febdfdce7 100644
> > --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> > +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.yaml
> > @@ -43,6 +43,7 @@ properties:
> > - qcom,rpmcc-sdm660
> > - qcom,rpmcc-sm6115
> > - qcom,rpmcc-sm6125
> > + - qcom,sm6375-rpmcc
>
> I am fine with it, although this contradicts a bit
> https://lore.kernel.org/all/[email protected]/
>
> Would be nice to get Bjorn's opinion/preference on this.
>
While global consistency is nice, I think we should just stick with
qcom,rpmcc-<soc>, to keep this binding nice and tidy.
Regards,
Bjorn
> Acked-by: Krzysztof Kozlowski <[email protected]>
>
>
> Best regards,
> Krzysztof