Fix the following coccicheck warning:
dcn20_clk_mgr.c:314:WARNING opportunity for max()
dcn20_clk_mgr.c:351:WARNING opportunity for max()
Signed-off-by: KaiLong Wang <[email protected]>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
index 650f3b4b562e..1aecdc5f73b6 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c
@@ -311,7 +311,7 @@ void dcn2_update_clocks(struct clk_mgr *clk_mgr_base,
new_clocks->disp_dpp_voltage_level_khz = new_clocks->dppclk_khz;
if (update_dispclk)
- new_clocks->disp_dpp_voltage_level_khz = new_clocks->dispclk_khz > new_clocks->dppclk_khz ? new_clocks->dispclk_khz : new_clocks->dppclk_khz;
+ new_clocks->disp_dpp_voltage_level_khz = max(new_clocks->dispclk_khz, new_clocks->dppclk_khz);
clk_mgr_base->clks.disp_dpp_voltage_level_khz = new_clocks->disp_dpp_voltage_level_khz;
if (pp_smu && pp_smu->set_voltage_by_freq)
@@ -348,7 +348,7 @@ void dcn2_update_clocks_fpga(struct clk_mgr *clk_mgr,
struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
/* Min fclk = 1.2GHz since all the extra scemi logic seems to run off of it */
- int fclk_adj = new_clocks->fclk_khz > 1200000 ? new_clocks->fclk_khz : 1200000;
+ int fclk_adj = max(new_clocks->fclk_khz, 1200000);
if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr->clks.phyclk_khz)) {
clk_mgr->clks.phyclk_khz = new_clocks->phyclk_khz;
--
2.25.1