2022-08-10 09:53:02

by Matt Ranostay

Subject: [PATCH RESEND 3/6] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

From: Aswath Govindraju <[email protected]>

Add support for two instance of OSPI in J721S2 SoC.

Cc: Vignesh Raghavendra <[email protected]>
Cc: Nishanth Menon <[email protected]>
Acked-by: Matt Ranostay <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 4d1bfabd1313..7bc268f27030 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -299,4 +299,44 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ fss: syscon@47000000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x0 0x47000000 0x0 0x100>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ ospi0: spi@47040000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47040000 0x00 0x100>,
+ <0x5 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 109 5>;
+ assigned-clocks = <&k3_clks 109 5>;
+ assigned-clock-parents = <&k3_clks 109 7>;
+ assigned-clock-rates = <166666666>;
+ power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ ospi1: spi@47050000 {
+ compatible = "ti,am654-ospi", "cdns,qspi-nor";
+ reg = <0x00 0x47050000 0x00 0x100>,
+ <0x7 0x0000000 0x1 0x0000000>;
+ interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x0>;
+ clocks = <&k3_clks 110 5>;
+ power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ };
};
--
2.36.1

2022-09-01 08:58:08

by Vignesh Raghavendra

Subject: Re: [PATCH RESEND 3/6] arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI

On 10/08/22 15:09, Matt Ranostay wrote:
> From: Aswath Govindraju <[email protected]>
>
> Add support for two instance of OSPI in J721S2 SoC.
>
> Cc: Vignesh Raghavendra <[email protected]>
> Cc: Nishanth Menon <[email protected]>
> Acked-by: Matt Ranostay <[email protected]>
> Signed-off-by: Aswath Govindraju <[email protected]>
> ---
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> index 4d1bfabd1313..7bc268f27030 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
> @@ -299,4 +299,44 @@ cpts@3d000 {
> ti,cpts-periodic-outputs = <2>;
> };
> };
> +
> + fss: syscon@47000000 {
> + compatible = "syscon", "simple-mfd";

please add "ti,j721e-system-controller"

> + reg = <0x0 0x47000000 0x0 0x100>;

s/0x0/0x00 to be consistent with file

> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ospi0: spi@47040000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47040000 0x00 0x100>,
> + <0x5 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 109 5>;
> + assigned-clocks = <&k3_clks 109 5>;
> + assigned-clock-parents = <&k3_clks 109 7>;
> + assigned-clock-rates = <166666666>;
> + power-domains = <&k3_pds 109 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + ospi1: spi@47050000 {
> + compatible = "ti,am654-ospi", "cdns,qspi-nor";
> + reg = <0x00 0x47050000 0x00 0x100>,
> + <0x7 0x0000000 0x1 0x0000000>;
> + interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
> + cdns,fifo-depth = <256>;
> + cdns,fifo-width = <4>;
> + cdns,trigger-address = <0x0>;
> + clocks = <&k3_clks 110 5>;
> + power-domains = <&k3_pds 110 TI_SCI_PD_EXCLUSIVE>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + };
> };

--
Regards
Vignesh