When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will turn on immediately on related Root Hub
ports. Then the VBUS will be de-asserted for a little while during xhci
reset (conducted by xhci driver) for a little while and back to normal.
This VBUS glitch might cause some USB devices emuration fail if kernel
boot with them connected. One SW workaround which can fix this is to
program all PORTSC[PP] to 0 to turn off VBUS immediately after setting
host mode in DWC3 driver(per signal measurement result, it will be too
late to do it in xhci-plat.c or xhci.c).
Signed-off-by: Ran Wang <[email protected]>
---
Changes in v2:
- Correct typos
- Shorten the name to snps,host-vbus-glitches
Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
index 8e5265e..453f562 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -106,6 +106,9 @@ Optional properties:
When just one value, which means INCRX burst mode enabled. When
more than one value, which means undefined length INCR burst type
enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256.
+ - snps,host-vbus-glitches: Power off all Root Hub ports immediately after
+ setting host mode to avoid vbus (negative) glitch happen in later
+ xhci reset. And the vbus will back to 5V automatically when reset done.
- in addition all properties from usb-xhci.txt from the current directory are
supported as well
--
1.7.1
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will be turned on immediately on related Root Hub
ports. Then, the VBUS is turned off for a little while(15us) when do xhci
reset (conducted by xhci driver) and back to normal finally, we can
observe a negative glitch of related signal happen.
This VBUS glitch might cause some USB devices enumeration fail if kernel
boot with them connected. Such as LS1012AFWRY/LS1043ARDB/LX2160AQDS
/LS1088ARDB with Kingston 16GB USB2.0/Kingston USB3.0/JetFlash Transcend
4GB USB2.0 drives. The fail cases include enumerated as full-speed device
or report wrong device descriptor, etc.
One SW workaround which can fix this is by programing all xhci PORTSC[PP]
to 0 to turn off VBUS immediately after setting host mode in DWC3 driver
(per signal measurement result, it will be too late to do it in
xhci-plat.c or xhci.c). Then, after xhci reset complete in xhci driver,
PORTSC[PP]s' value will back to 1 automatically and VBUS on at that time,
no glitch happen and normal enumeration process has no impact.
Signed-off-by: Ran Wang <[email protected]>
---
Changes in v2:
- Rename related property to 'snps,host-vbus-glitches'
- Rename related dwc member to 'host_vbus_glitches'
- Add member 'host_vbus_glitches' description in 'dwc3'
drivers/usb/dwc3/core.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
drivers/usb/dwc3/core.h | 12 +++++++++++-
2 files changed, 58 insertions(+), 1 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index a1b126f..02d11bc 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -100,6 +100,41 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
return 0;
}
+/*
+ * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
+ * @dwc3: Pointer to our controller context structure
+ */
+static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
+{
+ int i, port_num;
+ u32 reg, op_regs_base, offset;
+ void __iomem *xhci_regs;
+
+ /* xhci regs is not mapped yet, do it temperary here */
+ if (dwc->xhci_resources[0].start) {
+ xhci_regs = ioremap(dwc->xhci_resources[0].start,
+ DWC3_XHCI_REGS_END);
+ if (IS_ERR(xhci_regs)) {
+ dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
+ return;
+ }
+
+ op_regs_base = HC_LENGTH(readl(xhci_regs));
+ reg = readl(xhci_regs + XHCI_HCSPARAMS1);
+ port_num = HCS_MAX_PORTS(reg);
+
+ for (i = 1; i <= port_num; i++) {
+ offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
+ reg = readl(xhci_regs + offset);
+ reg &= ~PORT_POWER;
+ writel(reg, xhci_regs + offset);
+ }
+
+ iounmap(xhci_regs);
+ } else
+ dev_err(dwc->dev, "xhci base reg invalid\n");
+}
+
void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
{
u32 reg;
@@ -109,6 +144,15 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
reg |= DWC3_GCTL_PRTCAPDIR(mode);
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
+ /*
+ * We have to power off all Root hub ports immediately after DWC3 set
+ * to host mode to avoid VBUS glitch happen when xhci get reset later.
+ */
+ if (dwc->host_vbus_glitches) {
+ if (mode == DWC3_GCTL_PRTCAP_HOST)
+ dwc3_power_off_all_roothub_ports(dwc);
+ }
+
dwc->current_dr_role = mode;
}
@@ -1306,6 +1350,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
dwc->dis_metastability_quirk = device_property_read_bool(dev,
"snps,dis_metastability_quirk");
+ dwc->host_vbus_glitches = device_property_read_bool(dev,
+ "snps,host-vbus-glitches");
+
dwc->lpm_nyet_threshold = lpm_nyet_threshold;
dwc->tx_de_emphasis = tx_de_emphasis;
diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
index df87641..9b3a7ed 100644
--- a/drivers/usb/dwc3/core.h
+++ b/drivers/usb/dwc3/core.h
@@ -606,6 +606,14 @@
#define DWC3_OSTS_VBUSVLD BIT(1)
#define DWC3_OSTS_CONIDSTS BIT(0)
+/* Partial XHCI Register and Bit fields for quirk */
+#define XHCI_HCSPARAMS1 0x4
+#define XHCI_PORTSC_BASE 0x400
+#define PORT_POWER (1 << 9)
+#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
+#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
+#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
+
/* Structures */
struct dwc3_trb;
@@ -1024,6 +1032,8 @@ struct dwc3_scratchpad_array {
* 2 - No de-emphasis
* 3 - Reserved
* @dis_metastability_quirk: set to disable metastability quirk.
+ * @host-vbus-glitches: set to avoid vbus glitch during
+ * xhci reset.
* @imod_interval: set the interrupt moderation interval in 250ns
* increments or 0 to disable.
*/
@@ -1209,6 +1219,7 @@ struct dwc3 {
unsigned tx_de_emphasis:2;
unsigned dis_metastability_quirk:1;
+ unsigned host_vbus_glitches:1;
u16 imod_interval;
};
@@ -1217,7 +1228,6 @@ struct dwc3 {
#define INCRX_UNDEF_LENGTH_BURST_MODE 1
#define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
-
/* -------------------------------------------------------------------------- */
struct dwc3_event_type {
--
1.7.1
On Tue, 19 Feb 2019 07:23:14 +0000, Ran Wang wrote:
> When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
> (or its control signal) will turn on immediately on related Root Hub
> ports. Then the VBUS will be de-asserted for a little while during xhci
> reset (conducted by xhci driver) for a little while and back to normal.
>
> This VBUS glitch might cause some USB devices emuration fail if kernel
> boot with them connected. One SW workaround which can fix this is to
> program all PORTSC[PP] to 0 to turn off VBUS immediately after setting
> host mode in DWC3 driver(per signal measurement result, it will be too
> late to do it in xhci-plat.c or xhci.c).
>
> Signed-off-by: Ran Wang <[email protected]>
> ---
> Changes in v2:
> - Correct typos
> - Shorten the name to snps,host-vbus-glitches
>
> Documentation/devicetree/bindings/usb/dwc3.txt | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Tue, Feb 19, 2019 at 1:24 AM Ran Wang <[email protected]> wrote:
>
> When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
> (or its control signal) will be turned on immediately on related Root Hub
> ports. Then, the VBUS is turned off for a little while(15us) when do xhci
> reset (conducted by xhci driver) and back to normal finally, we can
> observe a negative glitch of related signal happen.
>
> This VBUS glitch might cause some USB devices enumeration fail if kernel
> boot with them connected. Such as LS1012AFWRY/LS1043ARDB/LX2160AQDS
> /LS1088ARDB with Kingston 16GB USB2.0/Kingston USB3.0/JetFlash Transcend
> 4GB USB2.0 drives. The fail cases include enumerated as full-speed device
> or report wrong device descriptor, etc.
>
> One SW workaround which can fix this is by programing all xhci PORTSC[PP]
> to 0 to turn off VBUS immediately after setting host mode in DWC3 driver
> (per signal measurement result, it will be too late to do it in
> xhci-plat.c or xhci.c). Then, after xhci reset complete in xhci driver,
> PORTSC[PP]s' value will back to 1 automatically and VBUS on at that time,
> no glitch happen and normal enumeration process has no impact.
>
> Signed-off-by: Ran Wang <[email protected]>
> ---
> Changes in v2:
> - Rename related property to 'snps,host-vbus-glitches'
> - Rename related dwc member to 'host_vbus_glitches'
> - Add member 'host_vbus_glitches' description in 'dwc3'
>
> drivers/usb/dwc3/core.c | 47 +++++++++++++++++++++++++++++++++++++++++++++++
> drivers/usb/dwc3/core.h | 12 +++++++++++-
> 2 files changed, 58 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> index a1b126f..02d11bc 100644
> --- a/drivers/usb/dwc3/core.c
> +++ b/drivers/usb/dwc3/core.c
> @@ -100,6 +100,41 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
> return 0;
> }
>
> +/*
> + * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
> + * @dwc3: Pointer to our controller context structure
> + */
> +static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
> +{
> + int i, port_num;
> + u32 reg, op_regs_base, offset;
> + void __iomem *xhci_regs;
> +
> + /* xhci regs is not mapped yet, do it temperary here */
> + if (dwc->xhci_resources[0].start) {
> + xhci_regs = ioremap(dwc->xhci_resources[0].start,
> + DWC3_XHCI_REGS_END);
> + if (IS_ERR(xhci_regs)) {
> + dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
> + return;
> + }
> +
> + op_regs_base = HC_LENGTH(readl(xhci_regs));
> + reg = readl(xhci_regs + XHCI_HCSPARAMS1);
> + port_num = HCS_MAX_PORTS(reg);
> +
> + for (i = 1; i <= port_num; i++) {
> + offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
Define the 0x10 as macro? And why don't you have the initial value of
i loop to be 0 to avoid the (i-1) here?
> + reg = readl(xhci_regs + offset);
> + reg &= ~PORT_POWER;
> + writel(reg, xhci_regs + offset);
> + }
> +
> + iounmap(xhci_regs);
> + } else
> + dev_err(dwc->dev, "xhci base reg invalid\n");
> +}
> +
> void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
> {
> u32 reg;
> @@ -109,6 +144,15 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
> reg |= DWC3_GCTL_PRTCAPDIR(mode);
> dwc3_writel(dwc->regs, DWC3_GCTL, reg);
>
> + /*
> + * We have to power off all Root hub ports immediately after DWC3 set
> + * to host mode to avoid VBUS glitch happen when xhci get reset later.
> + */
> + if (dwc->host_vbus_glitches) {
> + if (mode == DWC3_GCTL_PRTCAP_HOST)
> + dwc3_power_off_all_roothub_ports(dwc);
> + }
> +
> dwc->current_dr_role = mode;
> }
>
> @@ -1306,6 +1350,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> dwc->dis_metastability_quirk = device_property_read_bool(dev,
> "snps,dis_metastability_quirk");
>
> + dwc->host_vbus_glitches = device_property_read_bool(dev,
> + "snps,host-vbus-glitches");
> +
> dwc->lpm_nyet_threshold = lpm_nyet_threshold;
> dwc->tx_de_emphasis = tx_de_emphasis;
>
> diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h
> index df87641..9b3a7ed 100644
> --- a/drivers/usb/dwc3/core.h
> +++ b/drivers/usb/dwc3/core.h
> @@ -606,6 +606,14 @@
> #define DWC3_OSTS_VBUSVLD BIT(1)
> #define DWC3_OSTS_CONIDSTS BIT(0)
>
> +/* Partial XHCI Register and Bit fields for quirk */
> +#define XHCI_HCSPARAMS1 0x4
> +#define XHCI_PORTSC_BASE 0x400
> +#define PORT_POWER (1 << 9)
> +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
> +#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
> +#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
> +
> /* Structures */
>
> struct dwc3_trb;
> @@ -1024,6 +1032,8 @@ struct dwc3_scratchpad_array {
> * 2 - No de-emphasis
> * 3 - Reserved
> * @dis_metastability_quirk: set to disable metastability quirk.
> + * @host-vbus-glitches: set to avoid vbus glitch during
> + * xhci reset.
> * @imod_interval: set the interrupt moderation interval in 250ns
> * increments or 0 to disable.
> */
> @@ -1209,6 +1219,7 @@ struct dwc3 {
> unsigned tx_de_emphasis:2;
>
> unsigned dis_metastability_quirk:1;
> + unsigned host_vbus_glitches:1;
>
> u16 imod_interval;
> };
> @@ -1217,7 +1228,6 @@ struct dwc3 {
> #define INCRX_UNDEF_LENGTH_BURST_MODE 1
>
> #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
> -
No need to remove the new line here.
> /* -------------------------------------------------------------------------- */
>
> struct dwc3_event_type {
> --
> 1.7.1
>
--
- Leo
Hi Leo,
> -----Original Message-----
> From: Yang Li <[email protected]>
> Sent: Tuesday, February 26, 2019 05:29
> To: Ran Wang <[email protected]>
> Cc: Greg Kroah-Hartman <[email protected]>; Rob Herring
> <[email protected]>; Mark Rutland <[email protected]>; Felipe Balbi
> <[email protected]>; [email protected]; [email protected];
> [email protected]
> Subject: Re: [PATCH v2 2/2] usb: dwc3: Add workaround for host mode VBUS
> glitch when boot
>
> On Tue, Feb 19, 2019 at 1:24 AM Ran Wang <[email protected]> wrote:
> >
> > When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
> > (or its control signal) will be turned on immediately on related Root
> > Hub ports. Then, the VBUS is turned off for a little while(15us) when
> > do xhci reset (conducted by xhci driver) and back to normal finally,
> > we can observe a negative glitch of related signal happen.
> >
> > This VBUS glitch might cause some USB devices enumeration fail if
> > kernel boot with them connected. Such as
> > LS1012AFWRY/LS1043ARDB/LX2160AQDS /LS1088ARDB with Kingston 16GB
> > USB2.0/Kingston USB3.0/JetFlash Transcend 4GB USB2.0 drives. The fail
> > cases include enumerated as full-speed device or report wrong device
> descriptor, etc.
> >
> > One SW workaround which can fix this is by programing all xhci
> > PORTSC[PP] to 0 to turn off VBUS immediately after setting host mode
> > in DWC3 driver (per signal measurement result, it will be too late to
> > do it in xhci-plat.c or xhci.c). Then, after xhci reset complete in
> > xhci driver, PORTSC[PP]s' value will back to 1 automatically and VBUS
> > on at that time, no glitch happen and normal enumeration process has no
> impact.
> >
> > Signed-off-by: Ran Wang <[email protected]>
> > ---
> > Changes in v2:
> > - Rename related property to 'snps,host-vbus-glitches'
> > - Rename related dwc member to 'host_vbus_glitches'
> > - Add member 'host_vbus_glitches' description in 'dwc3'
> >
> > drivers/usb/dwc3/core.c | 47
> +++++++++++++++++++++++++++++++++++++++++++++++
> > drivers/usb/dwc3/core.h | 12 +++++++++++-
> > 2 files changed, 58 insertions(+), 1 deletions(-)
> >
> > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index
> > a1b126f..02d11bc 100644
> > --- a/drivers/usb/dwc3/core.c
> > +++ b/drivers/usb/dwc3/core.c
> > @@ -100,6 +100,41 @@ static int dwc3_get_dr_mode(struct dwc3 *dwc)
> > return 0;
> > }
> >
> > +/*
> > + * dwc3_power_of_all_roothub_ports - Power off all Root hub ports
> > + * @dwc3: Pointer to our controller context structure */ static void
> > +dwc3_power_off_all_roothub_ports(struct dwc3 *dwc) {
> > + int i, port_num;
> > + u32 reg, op_regs_base, offset;
> > + void __iomem *xhci_regs;
> > +
> > + /* xhci regs is not mapped yet, do it temperary here */
> > + if (dwc->xhci_resources[0].start) {
> > + xhci_regs = ioremap(dwc->xhci_resources[0].start,
> > + DWC3_XHCI_REGS_END);
> > + if (IS_ERR(xhci_regs)) {
> > + dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
> > + return;
> > + }
> > +
> > + op_regs_base = HC_LENGTH(readl(xhci_regs));
> > + reg = readl(xhci_regs + XHCI_HCSPARAMS1);
> > + port_num = HCS_MAX_PORTS(reg);
> > +
> > + for (i = 1; i <= port_num; i++) {
> > + offset = op_regs_base + XHCI_PORTSC_BASE +
> > + 0x10*(i-1);
>
> Define the 0x10 as macro? And why don't you have the initial value of i loop to
> be 0 to avoid the (i-1) here?
OK, thanks for pointing out.
> > + reg = readl(xhci_regs + offset);
> > + reg &= ~PORT_POWER;
> > + writel(reg, xhci_regs + offset);
> > + }
> > +
> > + iounmap(xhci_regs);
> > + } else
> > + dev_err(dwc->dev, "xhci base reg invalid\n"); }
> > +
> > void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode) {
> > u32 reg;
> > @@ -109,6 +144,15 @@ void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
> > reg |= DWC3_GCTL_PRTCAPDIR(mode);
> > dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> >
> > + /*
> > + * We have to power off all Root hub ports immediately after DWC3 set
> > + * to host mode to avoid VBUS glitch happen when xhci get reset later.
> > + */
> > + if (dwc->host_vbus_glitches) {
> > + if (mode == DWC3_GCTL_PRTCAP_HOST)
> > + dwc3_power_off_all_roothub_ports(dwc);
> > + }
> > +
> > dwc->current_dr_role = mode;
> > }
> >
> > @@ -1306,6 +1350,9 @@ static void dwc3_get_properties(struct dwc3 *dwc)
> > dwc->dis_metastability_quirk = device_property_read_bool(dev,
> > "snps,dis_metastability_quirk");
> >
> > + dwc->host_vbus_glitches = device_property_read_bool(dev,
> > + "snps,host-vbus-glitches");
> > +
> > dwc->lpm_nyet_threshold = lpm_nyet_threshold;
> > dwc->tx_de_emphasis = tx_de_emphasis;
> >
> > diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index
> > df87641..9b3a7ed 100644
> > --- a/drivers/usb/dwc3/core.h
> > +++ b/drivers/usb/dwc3/core.h
> > @@ -606,6 +606,14 @@
> > #define DWC3_OSTS_VBUSVLD BIT(1)
> > #define DWC3_OSTS_CONIDSTS BIT(0)
> >
> > +/* Partial XHCI Register and Bit fields for quirk */
> > +#define XHCI_HCSPARAMS1 0x4
> > +#define XHCI_PORTSC_BASE 0x400
> > +#define PORT_POWER (1 << 9)
> > +#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
> > +#define XHCI_HC_LENGTH(p) (((p)>>00)&0x00ff)
> > +#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
> > +
> > /* Structures */
> >
> > struct dwc3_trb;
> > @@ -1024,6 +1032,8 @@ struct dwc3_scratchpad_array {
> > * 2 - No de-emphasis
> > * 3 - Reserved
> > * @dis_metastability_quirk: set to disable metastability quirk.
> > + * @host-vbus-glitches: set to avoid vbus glitch during
> > + * xhci reset.
> > * @imod_interval: set the interrupt moderation interval in 250ns
> > * increments or 0 to disable.
> > */
> > @@ -1209,6 +1219,7 @@ struct dwc3 {
> > unsigned tx_de_emphasis:2;
> >
> > unsigned dis_metastability_quirk:1;
> > + unsigned host_vbus_glitches:1;
> >
> > u16 imod_interval;
> > };
> > @@ -1217,7 +1228,6 @@ struct dwc3 {
> > #define INCRX_UNDEF_LENGTH_BURST_MODE 1
> >
> > #define work_to_dwc(w) (container_of((w), struct dwc3, drd_work))
> > -
>
> No need to remove the new line here.
OK, will fix it in next version patch
Regards,
Ran
> > /*
> > ----------------------------------------------------------------------
> > ---- */
> >
> > struct dwc3_event_type {
> > --
> > 1.7.1
> >
>
>