Seville is a DSA switch that is embedded inside the T1040 SoC, and
supported by the mscc_seville DSA driver. The driver has been accepted
this release cycle and is currently available in net-next (and
therefore, in linux-next).
This series adds this switch to the SoC's dtsi files and to the T1040RDB
board file.
Vladimir Oltean (4):
powerpc: dts: t1040: add bindings for Seville Ethernet switch
powerpc: dts: t1040: label the 2 MDIO controllers
powerpc: dts: t1040rdb: put SGMII PHY under &mdio0 label
powerpc: dts: t1040rdb: add ports for Seville Ethernet switch
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 123 +++++++++++++++++++-
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 79 ++++++++++++-
2 files changed, 194 insertions(+), 8 deletions(-)
--
2.25.1
In preparation of referencing the MDIO nodes from board DTS files (so
that we can add PHY nodes easier), add labels to mdio0 and mdio1.
Signed-off-by: Vladimir Oltean <[email protected]>
---
arch/powerpc/boot/dts/fsl/t1040si-post.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
index 4af856dcc6a3..e1b138b3c714 100644
--- a/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
+++ b/arch/powerpc/boot/dts/fsl/t1040si-post.dtsi
@@ -620,11 +620,11 @@ enet3: ethernet@e6000 {
enet4: ethernet@e8000 {
};
- mdio@fc000 {
+ mdio0: mdio@fc000 {
interrupts = <100 1 0 0>;
};
- mdio@fd000 {
+ mdio1: mdio@fd000 {
status = "disabled";
};
};
--
2.25.1
We're going to add 8 more PHYs in a future patch. It is easier to follow
the hardware description if we don't need to fish for the path of the
MDIO controllers inside the SoC and just use the labels.
Signed-off-by: Vladimir Oltean <[email protected]>
---
arch/powerpc/boot/dts/fsl/t1040rdb.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
index 65ff34c49025..40d7126dbe90 100644
--- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
+++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
@@ -59,12 +59,6 @@ ethernet@e4000 {
phy-handle = <&phy_sgmii_2>;
phy-connection-type = "sgmii";
};
-
- mdio@fc000 {
- phy_sgmii_2: ethernet-phy@3 {
- reg = <0x03>;
- };
- };
};
};
@@ -76,3 +70,9 @@ cpld@3,0 {
};
#include "t1040si-post.dtsi"
+
+&mdio0 {
+ phy_sgmii_2: ethernet-phy@3 {
+ reg = <0x3>;
+ };
+};
--
2.25.1
> -----Original Message-----
> From: Vladimir Oltean <[email protected]>
> Sent: Wednesday, July 22, 2020 8:24 PM
> To: [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: [email protected]; [email protected]; linuxppc-
> [email protected]; [email protected];
> [email protected]; Madalin Bucur (OSS) <[email protected]>;
> Radu-andrei Bulie <[email protected]>; [email protected]
> Subject: [PATCH devicetree 3/4] powerpc: dts: t1040rdb: put SGMII PHY
> under &mdio0 label
>
> We're going to add 8 more PHYs in a future patch. It is easier to follow
> the hardware description if we don't need to fish for the path of the
> MDIO controllers inside the SoC and just use the labels.
>
Please align to the existing structure, it may be easier to add something
without paying attention to that but it's better to keep things organized.
This structure is used across all the device trees of the platforms using
DPAA, let's not start diverging now.
> Signed-off-by: Vladimir Oltean <[email protected]>
> ---
> arch/powerpc/boot/dts/fsl/t1040rdb.dts | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> index 65ff34c49025..40d7126dbe90 100644
> --- a/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1040rdb.dts
> @@ -59,12 +59,6 @@ ethernet@e4000 {
> phy-handle = <&phy_sgmii_2>;
> phy-connection-type = "sgmii";
> };
> -
> - mdio@fc000 {
> - phy_sgmii_2: ethernet-phy@3 {
> - reg = <0x03>;
> - };
> - };
> };
> };
>
> @@ -76,3 +70,9 @@ cpld@3,0 {
> };
>
> #include "t1040si-post.dtsi"
> +
> +&mdio0 {
> + phy_sgmii_2: ethernet-phy@3 {
> + reg = <0x3>;
> + };
> +};
> --
> 2.25.1