2020-07-21 15:21:59

by Franck Lenormand (OSS)

Subject: [PATCH v2 3/5] dt-bindings: firmware: imx-scu: Add SECVIO resource

From: Franck LENORMAND <[email protected]>

The SNVS can trigger interruption when detecting a SECurity
VIOlation.
This patch adds the definition of the resource.

Signed-off-by: Franck LENORMAND <[email protected]>
---
include/dt-bindings/firmware/imx/rsrc.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/dt-bindings/firmware/imx/rsrc.h b/include/dt-bindings/firmware/imx/rsrc.h
index 54278d5..fe5f25f 100644
--- a/include/dt-bindings/firmware/imx/rsrc.h
+++ b/include/dt-bindings/firmware/imx/rsrc.h
@@ -1,7 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2016 Freescale Semiconductor, Inc.
- * Copyright 2017-2018 NXP
+ * Copyright 2017-2018, 2020 NXP
*/

#ifndef __DT_BINDINGS_RSCRC_IMX_H
@@ -50,6 +50,7 @@
#define IMX_SC_R_DC_1_BLIT2 38
#define IMX_SC_R_DC_1_BLIT_OUT 39
#define IMX_SC_R_DC_1_WARP 42
+#define IMX_SC_R_SECVIO 44
#define IMX_SC_R_DC_1_VIDEO0 45
#define IMX_SC_R_DC_1_VIDEO1 46
#define IMX_SC_R_DC_1_FRAC0 47
--
2.7.4

2020-10-18 05:36:46

by Aisheng Dong

Subject: RE: [PATCH v2 3/5] dt-bindings: firmware: imx-scu: Add SECVIO resource

> From: Franck Lenormand (OSS) <[email protected]>
> Sent: Tuesday, July 21, 2020 11:21 PM
>
> The SNVS can trigger interruption when detecting a SECurity VIOlation.
> This patch adds the definition of the resource.
>

Not sure if the uppercase of 'SECurity VIOlation' is intended because it looks strange.
Otherwise, I'm okay with this patch.

Regards
Aisheng

> Signed-off-by: Franck LENORMAND <[email protected]>
> ---
> include/dt-bindings/firmware/imx/rsrc.h | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/include/dt-bindings/firmware/imx/rsrc.h
> b/include/dt-bindings/firmware/imx/rsrc.h
> index 54278d5..fe5f25f 100644
> --- a/include/dt-bindings/firmware/imx/rsrc.h
> +++ b/include/dt-bindings/firmware/imx/rsrc.h
> @@ -1,7 +1,7 @@
> /* SPDX-License-Identifier: GPL-2.0+ */
> /*
> * Copyright (C) 2016 Freescale Semiconductor, Inc.
> - * Copyright 2017-2018 NXP
> + * Copyright 2017-2018, 2020 NXP
> */
>
> #ifndef __DT_BINDINGS_RSCRC_IMX_H
> @@ -50,6 +50,7 @@
> #define IMX_SC_R_DC_1_BLIT2 38
> #define IMX_SC_R_DC_1_BLIT_OUT 39
> #define IMX_SC_R_DC_1_WARP 42
> +#define IMX_SC_R_SECVIO 44
> #define IMX_SC_R_DC_1_VIDEO0 45
> #define IMX_SC_R_DC_1_VIDEO1 46
> #define IMX_SC_R_DC_1_FRAC0 47
> --
> 2.7.4