i.MX PCIe controller is one dual mode PCIe controller, and can work either
as RC or EP.
This series add the i.MX PCIe EP mode support. And had been verified on
i.MX8MQ, i.MX8MM EVK and i.MX8MP EVK boards.
In the verification, one EVK board used as RC, the other one used as EP.
Use the cross TX/RX differential cable connect the two PCIe ports of these
two EVK boards.
+-----------+ +------------+
| PCIe TX |<-------------->|PCIe RX |
| | | |
|EVK Board | |EVK Board |
| | | |
| PCIe RX |<-------------->|PCIe TX |
+-----------+ +------------+
Main changes from v7 -> v8:
Refer to Rob's review comments.
- Merge the binding document changes into one commit.
- To avoid the duplication, restruct the common properties of i.MX PCIe
schema, thus they can be shared by both RC and Endpoint modes.
Main changes from v6 -> v7:
Refer to Krzysztof's review comments.
- Drop the 2/4/6 patches of v6 series.
- Based on for-next branch of Shawn's git, and the fsl,imx6q-pcie.yaml
changes in the v4.
Separate the DT-schema for i.MX PCIe Endpoint modes, and pass the
dt_binding_check and dtbs_check.
Main changes from v5 -> v6:
- The v6 only contains the DTS changes, since PCIe part had been picked up.
- Based on Shawn's for-next branch, and the following two patch-sets [1]
and [2] issued by Marek, rebase the DTS changes.
[1] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
[2] https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
Main changes from v4 -> v5:
- Rebase to v6.2-rc1.
- Follow the clock definitions on i.MX8MP platform refer to the
following commit.
https://patchwork.kernel.org/project/linux-arm-kernel/patch/[email protected]/
Main changes from v3 -> v4:
- Add the Rob's ACK in the dt-binding patch.
- Use "i.MX" to keep spell consistent.
- Squash generic endpoint infrastructure changes of
"[12/14] PCI: imx6: Add iMX8MM PCIe EP mode" into Kconfig changes.
NOTE:
The following commits should be cherried back firstly, when apply this
series.
Shawn's tree (git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git)
d50650500064 arm64: dts: imx8mp-evk: Add PCIe support
9e65987b9584 arm64: dts: imx8mp: Add iMX8MP PCIe support
5506018d3dec soc: imx: imx8mp-blk-ctrl: handle PCIe PHY resets
Philipp's tree (git://git.pengutronix.de/git/pza/linux)
051d9eb40388 reset: imx7: Fix the iMX8MP PCIe PHY PERST support
The PHY changes:
https://patchwork.kernel.org/project/linux-pci/cover/[email protected]/
Main changes from v2 -> v3:
- Add the i.MX8MP PCIe EP support, and verified on i.MX8MP EVK board.
- Rebase to latest pci/next branch(tag: v6.0-rc1 plus some PCIe changes).
Main changes from v1 -> v2:
- Add Rob's ACK into first two commits.
- Rebase to the tag: pci-v5.20-changes of the pci/next branch.
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml | 121 +++++++++++++++++++++++++++++++++++++++++++
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 217 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml | 111 +++-------------------------------------
MAINTAINERS | 2 +
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 ++++++++++
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 ++++++++++++
7 files changed, 429 insertions(+), 104 deletions(-)
[PATCH v8 1/4] dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
[PATCH v8 2/4] arm64: dts: Add i.MX8MM PCIe EP support
[PATCH v8 3/4] arm64: dts: Add i.MX8MQ PCIe EP support
[PATCH v8 4/4] arm64: dts: Add i.MX8MP PCIe EP support
Restruct i.MX PCIe schema, derive the common properties, thus they can
be shared by both the RC and Endpoint schema.
Update the description of fsl,imx6q-pcie.yaml, and move the EP mode
compatible to fsl,imx6q-pcie-ep.yaml.
Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
accordingly.
Signed-off-by: Richard Zhu <[email protected]>
---
.../bindings/pci/fsl,imx6q-pcie-common.yaml | 121 ++++++++++
.../bindings/pci/fsl,imx6q-pcie-ep.yaml | 217 ++++++++++++++++++
.../bindings/pci/fsl,imx6q-pcie.yaml | 111 +--------
MAINTAINERS | 2 +
4 files changed, 347 insertions(+), 104 deletions(-)
create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
new file mode 100644
index 000000000000..a2eb56de0294
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
@@ -0,0 +1,121 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 PCIe RC/EP controller
+
+maintainers:
+ - Lucas Stach <[email protected]>
+ - Richard Zhu <[email protected]>
+
+description:
+ Generic Freescale i.MX PCIe Root Port and Endpoint controller
+ properties.
+
+properties:
+ clocks:
+ minItems: 3
+ items:
+ - description: PCIe bridge clock.
+ - description: PCIe bus clock.
+ - description: PCIe PHY clock.
+ - description: Additional required clock entry for imx6sx-pcie,
+ imx8mq-pcie.
+
+ clock-names:
+ minItems: 3
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - enum: [ pcie_phy, pcie_aux ]
+ - enum: [ pcie_inbound_axi, pcie_aux ]
+
+ num-lanes:
+ const: 1
+
+ fsl,imx7d-pcie-phy:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: A phandle to an fsl,imx7d-pcie-phy node. Additional
+ required properties for imx7d-pcie and imx8mq-pcie.
+
+ power-domains:
+ minItems: 1
+ items:
+ - description: The phandle pointing to the DISPLAY domain for
+ imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
+ imx8mq-pcie.
+ - description: The phandle pointing to the PCIE_PHY power domains
+ for imx6sx-pcie.
+
+ power-domain-names:
+ minItems: 1
+ items:
+ - const: pcie
+ - const: pcie_phy
+
+ resets:
+ minItems: 2
+ maxItems: 3
+ description: Phandles to PCIe-related reset lines exposed by SRC
+ IP block. Additional required by imx7d-pcie and imx8mq-pcie.
+
+ reset-names:
+ minItems: 2
+ maxItems: 3
+
+ fsl,tx-deemph-gen1:
+ description: Gen1 De-emphasis value (optional required).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ fsl,tx-deemph-gen2-3p5db:
+ description: Gen2 (3.5db) De-emphasis value (optional required).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+
+ fsl,tx-deemph-gen2-6db:
+ description: Gen2 (6db) De-emphasis value (optional required).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 20
+
+ fsl,tx-swing-full:
+ description: Gen2 TX SWING FULL value (optional required).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 127
+
+ fsl,tx-swing-low:
+ description: TX launch amplitude swing_low value (optional required).
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 127
+
+ fsl,max-link-speed:
+ description: Specify PCI Gen for link capability (optional required).
+ Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
+ requirements and thus for gen2 capability a gen2 compliant clock
+ generator should be used and configured.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2, 3, 4]
+ default: 1
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: pcie-phy
+
+ vpcie-supply:
+ description: Should specify the regulator in charge of PCIe port power.
+ The regulator will be enabled when initializing the PCIe host and
+ disabled either as part of the init process or when shutting down
+ the host (optional required).
+
+ vph-supply:
+ description: Should specify the regulator in charge of VPH one of
+ the three PCIe PHY powers. This regulator can be supplied by both
+ 1.8v and 3.3v voltage supplies (optional required).
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
new file mode 100644
index 000000000000..8b2506a85083
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 PCIe Endpoint controller
+
+maintainers:
+ - Lucas Stach <[email protected]>
+ - Richard Zhu <[email protected]>
+
+description: |+
+ This PCIe controller is based on the Synopsys DesignWare PCIe IP and
+ thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
+ The controller instances are dual mode where in they can work either in
+ Root Port mode or Endpoint mode but one at a time.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ - fsl,imx8mp-pcie-ep
+
+ reg:
+ minItems: 2
+
+ reg-names:
+ items:
+ - const: dbi
+ - const: addr_space
+
+ interrupts:
+ items:
+ - description: builtin eDMA interrupter.
+
+ interrupt-names:
+ items:
+ - const: dma
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - num-lanes
+ - interrupts
+ - interrupt-names
+ - clocks
+ - clock-names
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+ - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx6sx-pcie-ep
+ then:
+ properties:
+ clock-names:
+ items:
+ - {}
+ - {}
+ - const: pcie_phy
+ - const: pcie_inbound_axi
+ power-domains:
+ minItems: 2
+ power-domain-names:
+ minItems: 2
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mq-pcie-ep
+ then:
+ properties:
+ clock-names:
+ items:
+ - {}
+ - {}
+ - const: pcie_phy
+ - const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ not:
+ contains:
+ enum:
+ - fsl,imx6sx-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ maxItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6qp-pcie-ep
+ - fsl,imx7d-pcie-ep
+ then:
+ properties:
+ clock-names:
+ maxItems: 3
+ contains:
+ const: pcie_phy
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mp-pcie-ep
+ then:
+ properties:
+ clock-names:
+ maxItems: 3
+ contains:
+ const: pcie_aux
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6qp-pcie-ep
+ then:
+ properties:
+ power-domains: false
+ power-domain-names: false
+
+ - if:
+ not:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6sx-pcie-ep
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6qp-pcie-ep
+ then:
+ properties:
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6sx-pcie-ep
+ - fsl,imx6qp-pcie-ep
+ - fsl,imx7d-pcie-ep
+ - fsl,imx8mq-pcie-ep
+ then:
+ properties:
+ resets:
+ minItems: 3
+ reset-names:
+ items:
+ - const: pciephy
+ - const: apps
+ - const: turnoff
+ else:
+ properties:
+ resets:
+ maxItems: 2
+ reset-names:
+ items:
+ - const: apps
+ - const: turnoff
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/power/imx8mp-power.h>
+ #include <dt-bindings/reset/imx8mp-reset.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ pcie_ep: pcie-ep@33800000 {
+ compatible = "fsl,imx8mp-pcie-ep";
+ reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
+ reg-names = "dbi", "addr_space";
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ fsl,max-link-speed = <3>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+ resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
index f13f87fddb3d..820e1f7cd1fa 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
@@ -13,6 +13,11 @@ maintainers:
description: |+
This PCIe host controller is based on the Synopsys DesignWare PCIe IP
and thus inherits all the common properties defined in snps,dw-pcie.yaml.
+ The controller instances are dual mode where in they can work either in
+ Root Port mode or Endpoint mode but one at a time.
+
+ See fsl,imx6q-pcie-ep.yaml for details on the Endpoint mode device tree
+ bindings.
properties:
compatible:
@@ -24,9 +29,6 @@ properties:
- fsl,imx8mq-pcie
- fsl,imx8mm-pcie
- fsl,imx8mp-pcie
- - fsl,imx8mm-pcie-ep
- - fsl,imx8mq-pcie-ep
- - fsl,imx8mp-pcie-ep
reg:
items:
@@ -46,96 +48,6 @@ properties:
items:
- const: msi
- clocks:
- minItems: 3
- items:
- - description: PCIe bridge clock.
- - description: PCIe bus clock.
- - description: PCIe PHY clock.
- - description: Additional required clock entry for imx6sx-pcie,
- imx8mq-pcie.
-
- clock-names:
- minItems: 3
- items:
- - const: pcie
- - const: pcie_bus
- - enum: [ pcie_phy, pcie_aux ]
- - enum: [ pcie_inbound_axi, pcie_aux ]
-
- num-lanes:
- const: 1
-
- fsl,imx7d-pcie-phy:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: A phandle to an fsl,imx7d-pcie-phy node. Additional
- required properties for imx7d-pcie and imx8mq-pcie.
-
- power-domains:
- minItems: 1
- items:
- - description: The phandle pointing to the DISPLAY domain for
- imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
- imx8mq-pcie.
- - description: The phandle pointing to the PCIE_PHY power domains
- for imx6sx-pcie.
-
- power-domain-names:
- minItems: 1
- items:
- - const: pcie
- - const: pcie_phy
-
- resets:
- minItems: 2
- maxItems: 3
- description: Phandles to PCIe-related reset lines exposed by SRC
- IP block. Additional required by imx7d-pcie and imx8mq-pcie.
-
- reset-names:
- minItems: 2
- maxItems: 3
-
- fsl,tx-deemph-gen1:
- description: Gen1 De-emphasis value (optional required).
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 0
-
- fsl,tx-deemph-gen2-3p5db:
- description: Gen2 (3.5db) De-emphasis value (optional required).
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 0
-
- fsl,tx-deemph-gen2-6db:
- description: Gen2 (6db) De-emphasis value (optional required).
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 20
-
- fsl,tx-swing-full:
- description: Gen2 TX SWING FULL value (optional required).
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 127
-
- fsl,tx-swing-low:
- description: TX launch amplitude swing_low value (optional required).
- $ref: /schemas/types.yaml#/definitions/uint32
- default: 127
-
- fsl,max-link-speed:
- description: Specify PCI Gen for link capability (optional required).
- Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
- requirements and thus for gen2 capability a gen2 compliant clock
- generator should be used and configured.
- $ref: /schemas/types.yaml#/definitions/uint32
- enum: [1, 2, 3, 4]
- default: 1
-
- phys:
- maxItems: 1
-
- phy-names:
- const: pcie-phy
-
reset-gpio:
description: Should specify the GPIO for controlling the PCI bus device
reset signal. It's not polarity aware and defaults to active-low reset
@@ -147,17 +59,6 @@ properties:
L=operation state) (optional required).
type: boolean
- vpcie-supply:
- description: Should specify the regulator in charge of PCIe port power.
- The regulator will be enabled when initializing the PCIe host and
- disabled either as part of the init process or when shutting down
- the host (optional required).
-
- vph-supply:
- description: Should specify the regulator in charge of VPH one of
- the three PCIe PHY powers. This regulator can be supplied by both
- 1.8v and 3.3v voltage supplies (optional required).
-
required:
- compatible
- reg
@@ -178,6 +79,8 @@ required:
allOf:
- $ref: /schemas/pci/snps,dw-pcie.yaml#
+ - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
+
- if:
properties:
compatible:
diff --git a/MAINTAINERS b/MAINTAINERS
index 5dce1c45f4d1..5ee8de98d4a4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15997,6 +15997,8 @@ M: Lucas Stach <[email protected]>
L: [email protected]
L: [email protected] (moderated for non-subscribers)
S: Maintained
+F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
+F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
F: Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml
F: drivers/pci/controller/dwc/*imx6*
--
2.34.1
Add i.MX8MM PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm.dtsi | 24 +++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
index 31f4548f85cf..a9552867e547 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi
@@ -1315,6 +1315,30 @@ pcie0: pcie@33800000 {
status = "disabled";
};
+ pcie0_ep: pcie-ep@33800000 {
+ compatible = "fsl,imx8mm-pcie-ep";
+ reg = <0x33800000 0x400000>,
+ <0x18000000 0x8000000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
+ <&clk IMX8MM_CLK_PCIE1_PHY>,
+ <&clk IMX8MM_CLK_PCIE1_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu_3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.34.1
Add i.MX8MQ PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq.dtsi | 32 +++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
index 98fbba4c99a9..9f950a6ac6c9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
@@ -1605,6 +1605,38 @@ pcie1: pcie@33c00000 {
status = "disabled";
};
+ pcie1_ep: pcie-ep@33c00000 {
+ compatible = "fsl,imx8mq-pcie-ep";
+ reg = <0x33c00000 0x000400000>,
+ <0x20000000 0x08000000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "dma";
+ fsl,max-link-speed = <2>;
+ clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_aux";
+ power-domains = <&pgc_pcie>;
+ resets = <&src IMX8MQ_RESET_PCIEPHY2>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_EN>,
+ <&src IMX8MQ_RESET_PCIE2_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ assigned-clocks = <&clk IMX8MQ_CLK_PCIE2_CTRL>,
+ <&clk IMX8MQ_CLK_PCIE2_PHY>,
+ <&clk IMX8MQ_CLK_PCIE2_AUX>;
+ assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_250M>,
+ <&clk IMX8MQ_SYS2_PLL_100M>,
+ <&clk IMX8MQ_SYS1_PLL_80M>;
+ assigned-clock-rates = <250000000>, <100000000>,
+ <10000000>;
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>, /* GIC Dist */
--
2.34.1
Add i.MX8MP PCIe EP support.
Signed-off-by: Richard Zhu <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 26 +++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index a19224fe1a6a..2f84b8b0118e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -1309,6 +1309,32 @@ pcie: pcie@33800000 {
status = "disabled";
};
+ pcie_ep: pcie-ep@33800000 {
+ compatible = "fsl,imx8mp-pcie-ep";
+ reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>;
+ reg-names = "dbi", "addr_space";
+ clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
+ <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "pcie", "pcie_bus", "pcie_aux";
+ assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
+ assigned-clock-rates = <10000000>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
+ num-lanes = <1>;
+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; /* eDMA */
+ interrupt-names = "dma";
+ fsl,max-link-speed = <3>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
+ resets = <&src IMX8MP_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX8MP_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "apps", "turnoff";
+ phys = <&pcie_phy>;
+ phy-names = "pcie-phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
gpu3d: gpu@38000000 {
compatible = "vivante,gc";
reg = <0x38000000 0x8000>;
--
2.34.1
On Wed, Feb 01, 2023 at 04:06:50PM +0800, Richard Zhu wrote:
> Restruct i.MX PCIe schema, derive the common properties, thus they can
> be shared by both the RC and Endpoint schema.
>
> Update the description of fsl,imx6q-pcie.yaml, and move the EP mode
> compatible to fsl,imx6q-pcie-ep.yaml.
>
> Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
> accordingly.
>
> Signed-off-by: Richard Zhu <[email protected]>
> ---
> .../bindings/pci/fsl,imx6q-pcie-common.yaml | 121 ++++++++++
> .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 217 ++++++++++++++++++
> .../bindings/pci/fsl,imx6q-pcie.yaml | 111 +--------
> MAINTAINERS | 2 +
> 4 files changed, 347 insertions(+), 104 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> create mode 100644 Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
>
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> new file mode 100644
> index 000000000000..a2eb56de0294
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> @@ -0,0 +1,121 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-common.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 PCIe RC/EP controller
> +
> +maintainers:
> + - Lucas Stach <[email protected]>
> + - Richard Zhu <[email protected]>
> +
> +description:
> + Generic Freescale i.MX PCIe Root Port and Endpoint controller
> + properties.
> +
> +properties:
> + clocks:
> + minItems: 3
> + items:
> + - description: PCIe bridge clock.
> + - description: PCIe bus clock.
> + - description: PCIe PHY clock.
> + - description: Additional required clock entry for imx6sx-pcie,
> + imx8mq-pcie.
> +
> + clock-names:
> + minItems: 3
> + items:
> + - const: pcie
> + - const: pcie_bus
> + - enum: [ pcie_phy, pcie_aux ]
> + - enum: [ pcie_inbound_axi, pcie_aux ]
> +
> + num-lanes:
> + const: 1
> +
> + fsl,imx7d-pcie-phy:
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> + required properties for imx7d-pcie and imx8mq-pcie.
> +
> + power-domains:
> + minItems: 1
> + items:
> + - description: The phandle pointing to the DISPLAY domain for
> + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> + imx8mq-pcie.
> + - description: The phandle pointing to the PCIE_PHY power domains
> + for imx6sx-pcie.
> +
> + power-domain-names:
> + minItems: 1
> + items:
> + - const: pcie
> + - const: pcie_phy
> +
> + resets:
> + minItems: 2
> + maxItems: 3
> + description: Phandles to PCIe-related reset lines exposed by SRC
> + IP block. Additional required by imx7d-pcie and imx8mq-pcie.
> +
> + reset-names:
> + minItems: 2
> + maxItems: 3
> +
> + fsl,tx-deemph-gen1:
> + description: Gen1 De-emphasis value (optional required).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + fsl,tx-deemph-gen2-3p5db:
> + description: Gen2 (3.5db) De-emphasis value (optional required).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 0
> +
> + fsl,tx-deemph-gen2-6db:
> + description: Gen2 (6db) De-emphasis value (optional required).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 20
> +
> + fsl,tx-swing-full:
> + description: Gen2 TX SWING FULL value (optional required).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 127
> +
> + fsl,tx-swing-low:
> + description: TX launch amplitude swing_low value (optional required).
> + $ref: /schemas/types.yaml#/definitions/uint32
> + default: 127
> +
> + fsl,max-link-speed:
> + description: Specify PCI Gen for link capability (optional required).
> + Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
> + requirements and thus for gen2 capability a gen2 compliant clock
> + generator should be used and configured.
> + $ref: /schemas/types.yaml#/definitions/uint32
> + enum: [1, 2, 3, 4]
> + default: 1
> +
> + phys:
> + maxItems: 1
> +
> + phy-names:
> + const: pcie-phy
> +
> + vpcie-supply:
> + description: Should specify the regulator in charge of PCIe port power.
> + The regulator will be enabled when initializing the PCIe host and
> + disabled either as part of the init process or when shutting down
> + the host (optional required).
> +
> + vph-supply:
> + description: Should specify the regulator in charge of VPH one of
> + the three PCIe PHY powers. This regulator can be supplied by both
> + 1.8v and 3.3v voltage supplies (optional required).
> +
> +additionalProperties: true
> +
> +...
> diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> new file mode 100644
> index 000000000000..8b2506a85083
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> @@ -0,0 +1,217 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/pci/fsl,imx6q-pcie-ep.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 PCIe Endpoint controller
> +
> +maintainers:
> + - Lucas Stach <[email protected]>
> + - Richard Zhu <[email protected]>
> +
> +description: |+
> + This PCIe controller is based on the Synopsys DesignWare PCIe IP and
> + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
> + The controller instances are dual mode where in they can work either in
> + Root Port mode or Endpoint mode but one at a time.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8mm-pcie-ep
> + - fsl,imx8mq-pcie-ep
> + - fsl,imx8mp-pcie-ep
> +
> + reg:
> + minItems: 2
> +
> + reg-names:
> + items:
> + - const: dbi
> + - const: addr_space
> +
> + interrupts:
> + items:
> + - description: builtin eDMA interrupter.
> +
> + interrupt-names:
> + items:
> + - const: dma
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - num-lanes
> + - interrupts
> + - interrupt-names
> + - clocks
> + - clock-names
> +
> +allOf:
> + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
> + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx6sx-pcie-ep
> + then:
> + properties:
> + clock-names:
> + items:
> + - {}
> + - {}
> + - const: pcie_phy
> + - const: pcie_inbound_axi
> + power-domains:
> + minItems: 2
> + power-domain-names:
> + minItems: 2
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: fsl,imx8mq-pcie-ep
> + then:
> + properties:
> + clock-names:
> + items:
> + - {}
> + - {}
> + - const: pcie_phy
> + - const: pcie_aux
> + - if:
> + properties:
> + compatible:
> + not:
> + contains:
> + enum:
> + - fsl,imx6sx-pcie-ep
> + - fsl,imx8mq-pcie-ep
> + then:
> + properties:
> + clocks:
> + maxItems: 3
> + clock-names:
> + maxItems: 3
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx6q-pcie-ep
> + - fsl,imx6qp-pcie-ep
> + - fsl,imx7d-pcie-ep
> + then:
> + properties:
> + clock-names:
> + maxItems: 3
> + contains:
> + const: pcie_phy
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx8mm-pcie-ep
> + - fsl,imx8mp-pcie-ep
> + then:
> + properties:
> + clock-names:
> + maxItems: 3
> + contains:
> + const: pcie_aux
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx6q-pcie-ep
> + - fsl,imx6qp-pcie-ep
> + then:
> + properties:
> + power-domains: false
> + power-domain-names: false
> +
> + - if:
> + not:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx6sx-pcie-ep
> + - fsl,imx6q-pcie-ep
> + - fsl,imx6qp-pcie-ep
> + then:
> + properties:
> + power-domains:
> + maxItems: 1
> + power-domain-names: false
> +
> + - if:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx6q-pcie-ep
> + - fsl,imx6sx-pcie-ep
> + - fsl,imx6qp-pcie-ep
> + - fsl,imx7d-pcie-ep
> + - fsl,imx8mq-pcie-ep
> + then:
> + properties:
> + resets:
> + minItems: 3
> + reset-names:
> + items:
> + - const: pciephy
> + - const: apps
> + - const: turnoff
> + else:
> + properties:
> + resets:
> + maxItems: 2
> + reset-names:
> + items:
> + - const: apps
> + - const: turnoff
All these constraints should be the same regardless of host or endpoint
mode, so they belong in the common schema. After all, it's the same h/w
for each SoC.
Rob
> -----Original Message-----
> From: Rob Herring <[email protected]>
> Sent: 2023??2??2?? 3:08
> To: Hongxing Zhu <[email protected]>
> Cc: [email protected]; [email protected];
> [email protected]; [email protected]; Peng Fan
> <[email protected]>; [email protected]; Marcel Ziswiler
> <[email protected]>; [email protected]; Frank Li
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; dl-linux-imx <[email protected]>
> Subject: Re: [PATCH v8 1/4] dt-bindings: imx6q-pcie: Restruct i.MX PCIe schema
>
> On Wed, Feb 01, 2023 at 04:06:50PM +0800, Richard Zhu wrote:
> > Restruct i.MX PCIe schema, derive the common properties, thus they can
> > be shared by both the RC and Endpoint schema.
> >
> > Update the description of fsl,imx6q-pcie.yaml, and move the EP mode
> > compatible to fsl,imx6q-pcie-ep.yaml.
> >
> > Add support for i.MX8M PCIe Endpoint modes, and update the MAINTAINER
> > accordingly.
> >
> > Signed-off-by: Richard Zhu <[email protected]>
> > ---
> > .../bindings/pci/fsl,imx6q-pcie-common.yaml | 121 ++++++++++
> > .../bindings/pci/fsl,imx6q-pcie-ep.yaml | 217 ++++++++++++++++++
> > .../bindings/pci/fsl,imx6q-pcie.yaml | 111 +--------
> > MAINTAINERS | 2 +
> > 4 files changed, 347 insertions(+), 104 deletions(-) create mode
> > 100644
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> > create mode 100644
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> > new file mode 100644
> > index 000000000000..a2eb56de0294
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-common.yaml
> > @@ -0,0 +1,121 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie-common.yaml%23&data=
> 05%
> >
> +7C01%7Chongxing.zhu%40nxp.com%7C7a6d389fd3434c0ab8ee08db04879fe7
> %7C68
> >
> +6ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638108752776087413%7C
> Unknown
> >
> +%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haW
> wiLC
> >
> +JXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=E4svdTu4JGnq80n8E6px4sDLABJ
> T%2Fm1%
> > +2BXCLAMr2Dnso%3D&reserved=0
> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chongxing.
> zhu%
> >
> +40nxp.com%7C7a6d389fd3434c0ab8ee08db04879fe7%7C686ea1d3bc2b4c6fa
> 92cd9
> >
> +9c5c301635%7C0%7C0%7C638108752776087413%7CUnknown%7CTWFpbGZs
> b3d8eyJWI
> >
> +joiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3
> 000%
> >
> +7C%7C%7C&sdata=%2BpZUAonpppVjVYdxWJH%2BxXm0c6lKYGePqrTf5Gg2Gf
> Q%3D&res
> > +erved=0
> > +
> > +title: Freescale i.MX6 PCIe RC/EP controller
> > +
> > +maintainers:
> > + - Lucas Stach <[email protected]>
> > + - Richard Zhu <[email protected]>
> > +
> > +description:
> > + Generic Freescale i.MX PCIe Root Port and Endpoint controller
> > + properties.
> > +
> > +properties:
> > + clocks:
> > + minItems: 3
> > + items:
> > + - description: PCIe bridge clock.
> > + - description: PCIe bus clock.
> > + - description: PCIe PHY clock.
> > + - description: Additional required clock entry for imx6sx-pcie,
> > + imx8mq-pcie.
> > +
> > + clock-names:
> > + minItems: 3
> > + items:
> > + - const: pcie
> > + - const: pcie_bus
> > + - enum: [ pcie_phy, pcie_aux ]
> > + - enum: [ pcie_inbound_axi, pcie_aux ]
> > +
> > + num-lanes:
> > + const: 1
> > +
> > + fsl,imx7d-pcie-phy:
> > + $ref: /schemas/types.yaml#/definitions/phandle
> > + description: A phandle to an fsl,imx7d-pcie-phy node. Additional
> > + required properties for imx7d-pcie and imx8mq-pcie.
> > +
> > + power-domains:
> > + minItems: 1
> > + items:
> > + - description: The phandle pointing to the DISPLAY domain for
> > + imx6sx-pcie, to PCIE_PHY power domain for imx7d-pcie and
> > + imx8mq-pcie.
> > + - description: The phandle pointing to the PCIE_PHY power domains
> > + for imx6sx-pcie.
> > +
> > + power-domain-names:
> > + minItems: 1
> > + items:
> > + - const: pcie
> > + - const: pcie_phy
> > +
> > + resets:
> > + minItems: 2
> > + maxItems: 3
> > + description: Phandles to PCIe-related reset lines exposed by SRC
> > + IP block. Additional required by imx7d-pcie and imx8mq-pcie.
> > +
> > + reset-names:
> > + minItems: 2
> > + maxItems: 3
> > +
> > + fsl,tx-deemph-gen1:
> > + description: Gen1 De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > +
> > + fsl,tx-deemph-gen2-3p5db:
> > + description: Gen2 (3.5db) De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 0
> > +
> > + fsl,tx-deemph-gen2-6db:
> > + description: Gen2 (6db) De-emphasis value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 20
> > +
> > + fsl,tx-swing-full:
> > + description: Gen2 TX SWING FULL value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 127
> > +
> > + fsl,tx-swing-low:
> > + description: TX launch amplitude swing_low value (optional required).
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + default: 127
> > +
> > + fsl,max-link-speed:
> > + description: Specify PCI Gen for link capability (optional required).
> > + Note that the IMX6 LVDS clock outputs do not meet gen2 jitter
> > + requirements and thus for gen2 capability a gen2 compliant clock
> > + generator should be used and configured.
> > + $ref: /schemas/types.yaml#/definitions/uint32
> > + enum: [1, 2, 3, 4]
> > + default: 1
> > +
> > + phys:
> > + maxItems: 1
> > +
> > + phy-names:
> > + const: pcie-phy
> > +
> > + vpcie-supply:
> > + description: Should specify the regulator in charge of PCIe port power.
> > + The regulator will be enabled when initializing the PCIe host and
> > + disabled either as part of the init process or when shutting down
> > + the host (optional required).
> > +
> > + vph-supply:
> > + description: Should specify the regulator in charge of VPH one of
> > + the three PCIe PHY powers. This regulator can be supplied by both
> > + 1.8v and 3.3v voltage supplies (optional required).
> > +
> > +additionalProperties: true
> > +
> > +...
> > diff --git
> > a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > new file mode 100644
> > index 000000000000..8b2506a85083
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
> > @@ -0,0 +1,217 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2
> > +---
> > +$id:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fschemas%2Fpci%2Ffsl%2Cimx6q-pcie-ep.yaml%23&data=05%7
> C01
> >
> +%7Chongxing.zhu%40nxp.com%7C7a6d389fd3434c0ab8ee08db04879fe7%7C
> 686ea1
> >
> +d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C638108752776087413%7CUnkn
> own%7CT
> >
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> > +$schema:
> > +https://eur01.safelinks.protection.outlook.com/?url=http%3A%2F%2Fdevi
> >
> +cetree.org%2Fmeta-schemas%2Fcore.yaml%23&data=05%7C01%7Chongxing.
> zhu%
> >
> +40nxp.com%7C7a6d389fd3434c0ab8ee08db04879fe7%7C686ea1d3bc2b4c6fa
> 92cd9
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> Q%3D&res
> > +erved=0
> > +
> > +title: Freescale i.MX6 PCIe Endpoint controller
> > +
> > +maintainers:
> > + - Lucas Stach <[email protected]>
> > + - Richard Zhu <[email protected]>
> > +
> > +description: |+
> > + This PCIe controller is based on the Synopsys DesignWare PCIe IP
> > +and
> > + thus inherits all the common properties defined in snps,dw-pcie-ep.yaml.
> > + The controller instances are dual mode where in they can work
> > +either in
> > + Root Port mode or Endpoint mode but one at a time.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8mm-pcie-ep
> > + - fsl,imx8mq-pcie-ep
> > + - fsl,imx8mp-pcie-ep
> > +
> > + reg:
> > + minItems: 2
> > +
> > + reg-names:
> > + items:
> > + - const: dbi
> > + - const: addr_space
> > +
> > + interrupts:
> > + items:
> > + - description: builtin eDMA interrupter.
> > +
> > + interrupt-names:
> > + items:
> > + - const: dma
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - reg-names
> > + - num-lanes
> > + - interrupts
> > + - interrupt-names
> > + - clocks
> > + - clock-names
> > +
> > +allOf:
> > + - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
> > + - $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx6sx-pcie-ep
> > + then:
> > + properties:
> > + clock-names:
> > + items:
> > + - {}
> > + - {}
> > + - const: pcie_phy
> > + - const: pcie_inbound_axi
> > + power-domains:
> > + minItems: 2
> > + power-domain-names:
> > + minItems: 2
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + const: fsl,imx8mq-pcie-ep
> > + then:
> > + properties:
> > + clock-names:
> > + items:
> > + - {}
> > + - {}
> > + - const: pcie_phy
> > + - const: pcie_aux
> > + - if:
> > + properties:
> > + compatible:
> > + not:
> > + contains:
> > + enum:
> > + - fsl,imx6sx-pcie-ep
> > + - fsl,imx8mq-pcie-ep
> > + then:
> > + properties:
> > + clocks:
> > + maxItems: 3
> > + clock-names:
> > + maxItems: 3
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx6q-pcie-ep
> > + - fsl,imx6qp-pcie-ep
> > + - fsl,imx7d-pcie-ep
> > + then:
> > + properties:
> > + clock-names:
> > + maxItems: 3
> > + contains:
> > + const: pcie_phy
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx8mm-pcie-ep
> > + - fsl,imx8mp-pcie-ep
> > + then:
> > + properties:
> > + clock-names:
> > + maxItems: 3
> > + contains:
> > + const: pcie_aux
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx6q-pcie-ep
> > + - fsl,imx6qp-pcie-ep
> > + then:
> > + properties:
> > + power-domains: false
> > + power-domain-names: false
> > +
> > + - if:
> > + not:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx6sx-pcie-ep
> > + - fsl,imx6q-pcie-ep
> > + - fsl,imx6qp-pcie-ep
> > + then:
> > + properties:
> > + power-domains:
> > + maxItems: 1
> > + power-domain-names: false
> > +
> > + - if:
> > + properties:
> > + compatible:
> > + contains:
> > + enum:
> > + - fsl,imx6q-pcie-ep
> > + - fsl,imx6sx-pcie-ep
> > + - fsl,imx6qp-pcie-ep
> > + - fsl,imx7d-pcie-ep
> > + - fsl,imx8mq-pcie-ep
> > + then:
> > + properties:
> > + resets:
> > + minItems: 3
> > + reset-names:
> > + items:
> > + - const: pciephy
> > + - const: apps
> > + - const: turnoff
> > + else:
> > + properties:
> > + resets:
> > + maxItems: 2
> > + reset-names:
> > + items:
> > + - const: apps
> > + - const: turnoff
>
> All these constraints should be the same regardless of host or endpoint mode, so
> they belong in the common schema. After all, it's the same h/w for each SoC.
Got that. Thanks a lot.
I'm not sure to move these to generic common schema or not in v8 series.
Now, I know how do that. Thanks for your advice.
Best Regards
Richard Zhu
>
> Rob