This patchset includes below fixes for clock driver
1> Fix Divider2 calculation
2> Memory leak in clock registration
3> Fix invalid name queries
4> Limit bestdiv with maxdiv
Quanyang Wang (1):
clk: zynqmp: fix memory leak in zynqmp_register_clocks
Rajan Vaja (2):
clk: zynqmp: Limit bestdiv with maxdiv
drivers: clk: Fix invalid clock name queries
Tejas Patel (1):
drivers: clk: zynqmp: Fix divider2 calculation
drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
2 files changed, 28 insertions(+), 11 deletions(-)
--
2.7.4
From: Rajan Vaja <[email protected]>
The clock driver makes EEMI call to get the name of invalid clk
when executing versal_get_clock_info() function. This results in
error messages.
Added check for validating clock before saving clock attribute and
calling zynqmp_pm_clock_get_name() in versal_get_clock_info() function.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/clkc.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
index 4dd8413..ff2d229 100644
--- a/drivers/clk/zynqmp/clkc.c
+++ b/drivers/clk/zynqmp/clkc.c
@@ -667,6 +667,11 @@ static void zynqmp_get_clock_info(void)
continue;
clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
+ /* skip query for Invalid clock */
+ ret = zynqmp_is_valid_clock(i);
+ if (ret != CLK_ATTR_VALID)
+ continue;
+
clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
--
2.7.4
From: Tejas Patel <[email protected]>
zynqmp_get_divider2_val() calculates, divider value of type DIV2 clock,
considering best possible combination of DIV1 and DIV2.
To find best possible values of DIV1 and DIV2, DIV1's parent rate
should be consider and not DIV2's parent rate since it would rate of
div1 clock. Consider a below topology,
out_clk->div2_clk->div1_clk->fixed_parent
where out_clk = (fixed_parent/div1_clk) / div2_clk, so parent clock
of div1_clk (i.e. out_clk) should be divided by div1_clk and div2_clk.
Existing code divides parent rate of div2_clk's clock instead of
div1_clk's parent rate, which is wrong.
Fix the same by considering div1's parent clock rate.
Fixes: 4ebd92d2e228 ("clk: zynqmp: Fix divider calculation")
Signed-off-by: Tejas Patel <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
---
drivers/clk/zynqmp/divider.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
index 7d2cb61..dea3e21 100644
--- a/drivers/clk/zynqmp/divider.c
+++ b/drivers/clk/zynqmp/divider.c
@@ -112,23 +112,30 @@ static unsigned long zynqmp_clk_divider_recalc_rate(struct clk_hw *hw,
static void zynqmp_get_divider2_val(struct clk_hw *hw,
unsigned long rate,
- unsigned long parent_rate,
struct zynqmp_clk_divider *divider,
int *bestdiv)
{
int div1;
int div2;
long error = LONG_MAX;
- struct clk_hw *parent_hw = clk_hw_get_parent(hw);
- struct zynqmp_clk_divider *pdivider = to_zynqmp_clk_divider(parent_hw);
+ unsigned long div1_prate;
+ struct clk_hw *div1_parent_hw;
+ struct clk_hw *div2_parent_hw = clk_hw_get_parent(hw);
+ struct zynqmp_clk_divider *pdivider =
+ to_zynqmp_clk_divider(div2_parent_hw);
if (!pdivider)
return;
+ div1_parent_hw = clk_hw_get_parent(div2_parent_hw);
+ if (!div1_parent_hw)
+ return;
+
+ div1_prate = clk_hw_get_rate(div1_parent_hw);
*bestdiv = 1;
for (div1 = 1; div1 <= pdivider->max_div;) {
for (div2 = 1; div2 <= divider->max_div;) {
- long new_error = ((parent_rate / div1) / div2) - rate;
+ long new_error = ((div1_prate / div1) / div2) - rate;
if (abs(new_error) < abs(error)) {
*bestdiv = div2;
@@ -193,7 +200,7 @@ static long zynqmp_clk_divider_round_rate(struct clk_hw *hw,
*/
if (div_type == TYPE_DIV2 &&
(clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT)) {
- zynqmp_get_divider2_val(hw, rate, *prate, divider, &bestdiv);
+ zynqmp_get_divider2_val(hw, rate, divider, &bestdiv);
}
if ((clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && divider->is_frac)
--
2.7.4
A gentle reminder for review.
On 3/2/20, 1:43 PM, "Jolly Shah" <[email protected]> wrote:
This patchset includes below fixes for clock driver
1> Fix Divider2 calculation
2> Memory leak in clock registration
3> Fix invalid name queries
4> Limit bestdiv with maxdiv
Quanyang Wang (1):
clk: zynqmp: fix memory leak in zynqmp_register_clocks
Rajan Vaja (2):
clk: zynqmp: Limit bestdiv with maxdiv
drivers: clk: Fix invalid clock name queries
Tejas Patel (1):
drivers: clk: zynqmp: Fix divider2 calculation
drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
2 files changed, 28 insertions(+), 11 deletions(-)
--
2.7.4
Please ignore below email. V2 patchset needs to be reviewed not below one.
Thanks,
Jolly Shah
On 3/23/20, 2:13 PM, "Jolly Shah" <[email protected]> wrote:
A gentle reminder for review.
On 3/2/20, 1:43 PM, "Jolly Shah" <[email protected]> wrote:
This patchset includes below fixes for clock driver
1> Fix Divider2 calculation
2> Memory leak in clock registration
3> Fix invalid name queries
4> Limit bestdiv with maxdiv
Quanyang Wang (1):
clk: zynqmp: fix memory leak in zynqmp_register_clocks
Rajan Vaja (2):
clk: zynqmp: Limit bestdiv with maxdiv
drivers: clk: Fix invalid clock name queries
Tejas Patel (1):
drivers: clk: zynqmp: Fix divider2 calculation
drivers/clk/zynqmp/clkc.c | 20 ++++++++++++++------
drivers/clk/zynqmp/divider.c | 19 ++++++++++++++-----
2 files changed, 28 insertions(+), 11 deletions(-)
--
2.7.4