2016-03-07 23:11:59

by Josh Poimboeuf

Subject: [PATCH] drm/radeon: refactor CIK tiling table initialization

When compiling the radeon driver on x86_64 with CONFIG_STACK_VALIDATION
enabled, objtool gives the following warnings:

drivers/gpu/drm/radeon/cik.o: warning: objtool: cik_tiling_mode_table_init()+0x6ce: call without frame pointer save/setup
drivers/gpu/drm/radeon/cik.o: warning: objtool: cik_tiling_mode_table_init()+0x72b: call without frame pointer save/setup
drivers/gpu/drm/radeon/cik.o: warning: objtool: cik_tiling_mode_table_init()+0x464: call without frame pointer save/setup
...

These are actually false positive warnings; there are no frame pointer
bugs. Instead objtool gets confused by the jump tables created by all
the switch statements, combined with some other gcc optimizations. It
tries to follows all possible code paths, but it fails to realize that
some of the paths aren't possible. For example:

4c97: 31 c0 xor %eax,%eax
...
4ca2: 89 c1 mov %eax,%ecx
4ca4: ff 24 cd 00 00 00 00 jmpq *0x0(,%rcx,8) 4ca7: R_X86_64_32S .rodata+0x148

First eax is cleared to zero with the "xor %eax,%eax" instruction.
Later, it moves the value of eax (zero in this case) to ecx, and uses
that value to jump to the first entry in a jump table in .rodata.

Because objtool doesn't have an x86 emulator, it doesn't know that rcx
is zero. So instead of following a single code path to the first jump
table entry, it follows all possible jump table entry paths in parallel.

Usually such overactive analysis isn't a problem. In every other jump
table in the kernel, all the jump targets have the same frame pointer
state. But in this exceedingly rare case, different targets have
different frame pointer states. Objtool notices that and creates the
false positive warnings.

In theory we could use the STACK_FRAME_NON_STANDARD marker to tell
objtool to skip analysis of the function. However, that's less than
ideal.

Looking at the cik_tiling_mode_table_init() code, it seems overly
complex with lots of repetition. So let's simplify it. All the switch
statements and conditionals can be replaced with much simpler logic by
generalizing the different behaviors and moving the initialization data
into data structures.

The change is a win-win: it's easier to parse for both humans and
machines. It also reduces the binary size by about 2%:

text data bss dec hex filename
101011 30360 0 131371 2012b cik-before.o
98699 30200 0 128899 1f783 cik-after.o

[ Note: Unfortunately I don't know how to test this code, so it's
completely untested. Any help or guidance with ensuring that the
correct initialization is still being written would be greatly
appreciated! ]

Reported-by: kbuild test robot <[email protected]>
Signed-off-by: Josh Poimboeuf <[email protected]>
---
Based on linux-next.

drivers/gpu/drm/radeon/cik.c | 1352 ++++++++++--------------------------------
1 file changed, 325 insertions(+), 1027 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0600140..1a477e6 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2327,6 +2327,290 @@ out:
return err;
}

+#define PIPE_CONFIG_2 0
+#define PIPE_CONFIG_4 1
+#define PIPE_CONFIG_8 2
+#define PIPE_CONFIG_16 3
+
+#define PIPE_CONFIG_4_RBS4 4
+
+#define TILE_SPLIT_ROW_SIZE ((unsigned char)-1)
+
+#define NUM_TILE_MODE_STATES 32
+#define NUM_SECONDARY_TILE_MODE_STATES 16
+
+static unsigned char array_modes[][NUM_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0 ... 4] = ARRAY_2D_TILED_THIN1,
+ [5] = ARRAY_1D_TILED_THIN1,
+ [6 ... 7] = ARRAY_PRT_2D_TILED_THIN1,
+ [8] = ARRAY_LINEAR_ALIGNED,
+ [9] = ARRAY_1D_TILED_THIN1,
+ [10] = ARRAY_2D_TILED_THIN1,
+ [11] = ARRAY_PRT_TILED_THIN1,
+ [12] = ARRAY_PRT_2D_TILED_THIN1,
+ [13] = ARRAY_1D_TILED_THIN1,
+ [14] = ARRAY_2D_TILED_THIN1,
+ [16] = ARRAY_PRT_TILED_THIN1,
+ [17] = ARRAY_PRT_2D_TILED_THIN1,
+ [27] = ARRAY_1D_TILED_THIN1,
+ [28] = ARRAY_PRT_2D_TILED_THIN1,
+ [29] = ARRAY_PRT_TILED_THIN1,
+ [30] = ARRAY_PRT_2D_TILED_THIN1,
+ },
+ { /* PIPE_CONFIG_4 */
+ [0 ... 4] = ARRAY_2D_TILED_THIN1,
+ [5] = ARRAY_1D_TILED_THIN1,
+ [6 ... 7] = ARRAY_PRT_2D_TILED_THIN1,
+ [8] = ARRAY_LINEAR_ALIGNED,
+ [9] = ARRAY_1D_TILED_THIN1,
+ [10] = ARRAY_2D_TILED_THIN1,
+ [11] = ARRAY_PRT_TILED_THIN1,
+ [12] = ARRAY_PRT_2D_TILED_THIN1,
+ [13] = ARRAY_1D_TILED_THIN1,
+ [14] = ARRAY_2D_TILED_THIN1,
+ [16] = ARRAY_PRT_TILED_THIN1,
+ [17] = ARRAY_PRT_2D_TILED_THIN1,
+ [27] = ARRAY_1D_TILED_THIN1,
+ [28] = ARRAY_PRT_2D_TILED_THIN1,
+ [29] = ARRAY_PRT_TILED_THIN1,
+ [30] = ARRAY_PRT_2D_TILED_THIN1,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0 ... 4] = ARRAY_2D_TILED_THIN1,
+ [5] = ARRAY_1D_TILED_THIN1,
+ [6 ... 7] = ARRAY_PRT_2D_TILED_THIN1,
+ [8] = ARRAY_LINEAR_ALIGNED,
+ [9] = ARRAY_1D_TILED_THIN1,
+ [10] = ARRAY_2D_TILED_THIN1,
+ [11] = ARRAY_PRT_TILED_THIN1,
+ [12] = ARRAY_PRT_2D_TILED_THIN1,
+ [13] = ARRAY_1D_TILED_THIN1,
+ [14] = ARRAY_2D_TILED_THIN1,
+ [16] = ARRAY_PRT_TILED_THIN1,
+ [17] = ARRAY_PRT_2D_TILED_THIN1,
+ [27] = ARRAY_1D_TILED_THIN1,
+ [28] = ARRAY_2D_TILED_THIN1,
+ [29] = ARRAY_PRT_TILED_THIN1,
+ [30] = ARRAY_PRT_2D_TILED_THIN1,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0 ... 4] = ARRAY_2D_TILED_THIN1,
+ [5] = ARRAY_1D_TILED_THIN1,
+ [6 ... 7] = ARRAY_PRT_2D_TILED_THIN1,
+ [8] = ARRAY_LINEAR_ALIGNED,
+ [9] = ARRAY_1D_TILED_THIN1,
+ [10] = ARRAY_2D_TILED_THIN1,
+ [11] = ARRAY_PRT_TILED_THIN1,
+ [12] = ARRAY_PRT_2D_TILED_THIN1,
+ [13] = ARRAY_1D_TILED_THIN1,
+ [14] = ARRAY_2D_TILED_THIN1,
+ [16] = ARRAY_PRT_TILED_THIN1,
+ [17] = ARRAY_PRT_2D_TILED_THIN1,
+ [27] = ARRAY_1D_TILED_THIN1,
+ [28] = ARRAY_2D_TILED_THIN1,
+ [29] = ARRAY_PRT_TILED_THIN1,
+ [30] = ARRAY_PRT_2D_TILED_THIN1,
+ },
+};
+
+static const unsigned char micro_tile_modes[NUM_TILE_MODE_STATES] = {
+ [0 ... 7] = ADDR_SURF_DEPTH_MICRO_TILING,
+ [9 ... 12] = ADDR_SURF_DISPLAY_MICRO_TILING,
+ [13 ... 14] = ADDR_SURF_THIN_MICRO_TILING,
+ [16 ... 17] = ADDR_SURF_THIN_MICRO_TILING,
+ [27 ... 30] = ADDR_SURF_ROTATED_MICRO_TILING,
+};
+
+static const unsigned char pipe_configs[][NUM_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0 ... 14] = ADDR_SURF_P2,
+ [16 ... 17] = ADDR_SURF_P2,
+ [27 ... 30] = ADDR_SURF_P2,
+ },
+ { /* PIPE_CONFIG_4 (num_rbs < 4) */
+ [0 ... 14] = ADDR_SURF_P4_8x16,
+ [16 ... 17] = ADDR_SURF_P4_8x16,
+ [27 ... 30] = ADDR_SURF_P4_8x16,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0 ... 10] = ADDR_SURF_P8_32x32_16x16,
+ [11] = ADDR_SURF_P8_32x32_8x16,
+ [12 ... 14] = ADDR_SURF_P8_32x32_16x16,
+ [16] = ADDR_SURF_P8_32x32_8x16,
+ [17] = ADDR_SURF_P8_32x32_16x16,
+ [27 ... 28] = ADDR_SURF_P8_32x32_16x16,
+ [29] = ADDR_SURF_P8_32x32_8x16,
+ [30] = ADDR_SURF_P8_32x32_16x16,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0 ... 10] = ADDR_SURF_P16_32x32_16x16,
+ [11] = ADDR_SURF_P16_32x32_8x16,
+ [12 ... 14] = ADDR_SURF_P16_32x32_16x16,
+ [16] = ADDR_SURF_P16_32x32_8x16,
+ [17] = ADDR_SURF_P16_32x32_16x16,
+ [27 ... 28] = ADDR_SURF_P16_32x32_16x16,
+ [29] = ADDR_SURF_P16_32x32_8x16,
+ [30] = ADDR_SURF_P16_32x32_16x16,
+ },
+ { /* PIPE_CONFIG_4_RBS4 (num_rbs == 4) */
+ [0 ... 10] = ADDR_SURF_P4_16x16,
+ [11] = ADDR_SURF_P4_8x16,
+ [12 ... 14] = ADDR_SURF_P4_16x16,
+ [16] = ADDR_SURF_P4_8x16,
+ [17] = ADDR_SURF_P4_16x16,
+ [27 ... 28] = ADDR_SURF_P4_16x16,
+ [29] = ADDR_SURF_P4_8x16,
+ [30] = ADDR_SURF_P4_16x16,
+ },
+};
+
+static const unsigned char tile_splits[NUM_TILE_MODE_STATES] = {
+ [0] = ADDR_SURF_TILE_SPLIT_64B,
+ [1] = ADDR_SURF_TILE_SPLIT_128B,
+ [2] = ADDR_SURF_TILE_SPLIT_256B,
+ [3] = ADDR_SURF_TILE_SPLIT_512B,
+ [4] = TILE_SPLIT_ROW_SIZE,
+ [6] = ADDR_SURF_TILE_SPLIT_256B,
+ [7] = TILE_SPLIT_ROW_SIZE,
+};
+
+static const unsigned char sample_splits[NUM_TILE_MODE_STATES] = {
+ [10 ... 12] = ADDR_SURF_SAMPLE_SPLIT_2,
+ [14] = ADDR_SURF_SAMPLE_SPLIT_2,
+ [16 ... 17] = ADDR_SURF_SAMPLE_SPLIT_2,
+ [28 ... 30] = ADDR_SURF_SAMPLE_SPLIT_2,
+};
+
+static const unsigned char bank_widths[][NUM_SECONDARY_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0 ... 1] = ADDR_SURF_BANK_WIDTH_2,
+ [2 ... 6] = ADDR_SURF_BANK_WIDTH_1,
+ [8 ... 9] = ADDR_SURF_BANK_WIDTH_4,
+ [10 ... 11] = ADDR_SURF_BANK_WIDTH_2,
+ [12 ... 14] = ADDR_SURF_BANK_WIDTH_1,
+ },
+ { /* PIPE_CONFIG_4 */
+ [0 ... 6] = ADDR_SURF_BANK_WIDTH_1,
+ [8 ... 9] = ADDR_SURF_BANK_WIDTH_2,
+ [10 ... 14] = ADDR_SURF_BANK_WIDTH_1,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0 ... 6] = ADDR_SURF_BANK_WIDTH_1,
+ [8 ... 14] = ADDR_SURF_BANK_WIDTH_1,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0 ... 6] = ADDR_SURF_BANK_WIDTH_1,
+ [8 ... 14] = ADDR_SURF_BANK_WIDTH_1,
+ },
+};
+
+static const unsigned char bank_heights[][NUM_SECONDARY_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0] = ADDR_SURF_BANK_HEIGHT_4,
+ [1 ... 2] = ADDR_SURF_BANK_HEIGHT_2,
+ [3 ... 6] = ADDR_SURF_BANK_HEIGHT_1,
+ [8] = ADDR_SURF_BANK_HEIGHT_8,
+ [9 ... 10] = ADDR_SURF_BANK_HEIGHT_4,
+ [11 ... 12] = ADDR_SURF_BANK_HEIGHT_2,
+ [13 ... 14] = ADDR_SURF_BANK_HEIGHT_1,
+ },
+ { /* PIPE_CONFIG_4 */
+ [0] = ADDR_SURF_BANK_HEIGHT_4,
+ [1] = ADDR_SURF_BANK_HEIGHT_2,
+ [2 ... 6] = ADDR_SURF_BANK_HEIGHT_1,
+ [8] = ADDR_SURF_BANK_HEIGHT_8,
+ [9 ... 10] = ADDR_SURF_BANK_HEIGHT_4,
+ [11] = ADDR_SURF_BANK_HEIGHT_2,
+ [12 ... 14] = ADDR_SURF_BANK_HEIGHT_1,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0] = ADDR_SURF_BANK_HEIGHT_4,
+ [1] = ADDR_SURF_BANK_HEIGHT_2,
+ [2 ... 6] = ADDR_SURF_BANK_HEIGHT_1,
+ [8] = ADDR_SURF_BANK_HEIGHT_8,
+ [9] = ADDR_SURF_BANK_HEIGHT_4,
+ [10] = ADDR_SURF_BANK_HEIGHT_2,
+ [11 ... 14] = ADDR_SURF_BANK_HEIGHT_1,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0] = ADDR_SURF_BANK_HEIGHT_4,
+ [1] = ADDR_SURF_BANK_HEIGHT_2,
+ [2 ... 6] = ADDR_SURF_BANK_HEIGHT_1,
+ [8] = ADDR_SURF_BANK_HEIGHT_4,
+ [9] = ADDR_SURF_BANK_HEIGHT_2,
+ [10 ... 14] = ADDR_SURF_BANK_HEIGHT_1,
+ },
+};
+
+static const unsigned char macro_tile_aspects[][NUM_SECONDARY_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0 ... 5] = ADDR_SURF_MACRO_ASPECT_4,
+ [6] = ADDR_SURF_MACRO_ASPECT_2,
+ [8 ... 13] = ADDR_SURF_MACRO_ASPECT_4,
+ [14] = ADDR_SURF_MACRO_ASPECT_2,
+ },
+ { /* PIPE_CONFIG_4 */
+ [0 ... 1] = ADDR_SURF_MACRO_ASPECT_4,
+ [2 ... 5] = ADDR_SURF_MACRO_ASPECT_2,
+ [6] = ADDR_SURF_MACRO_ASPECT_1,
+ [8 ... 11] = ADDR_SURF_MACRO_ASPECT_4,
+ [12 ... 13] = ADDR_SURF_MACRO_ASPECT_2,
+ [14] = ADDR_SURF_MACRO_ASPECT_1,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0] = ADDR_SURF_MACRO_ASPECT_4,
+ [1 ... 3] = ADDR_SURF_MACRO_ASPECT_2,
+ [4 ... 6] = ADDR_SURF_MACRO_ASPECT_1,
+ [8 ... 9] = ADDR_SURF_MACRO_ASPECT_4,
+ [10 ... 11] = ADDR_SURF_MACRO_ASPECT_2,
+ [12 ... 14] = ADDR_SURF_MACRO_ASPECT_1,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0 ... 1] = ADDR_SURF_MACRO_ASPECT_2,
+ [2 ... 6] = ADDR_SURF_MACRO_ASPECT_1,
+ [8 ... 9] = ADDR_SURF_MACRO_ASPECT_2,
+ [10 ... 14] = ADDR_SURF_MACRO_ASPECT_1,
+ },
+};
+
+static const unsigned char num_banks[][NUM_SECONDARY_TILE_MODE_STATES] = {
+ { /* PIPE_CONFIG_2 */
+ [0 ... 5] = ADDR_SURF_16_BANK,
+ [6] = ADDR_SURF_8_BANK,
+ [8 ... 13] = ADDR_SURF_16_BANK,
+ [14] = ADDR_SURF_8_BANK,
+ },
+ { /* PIPE_CONFIG_4 */
+ [0 ... 4] = ADDR_SURF_16_BANK,
+ [5] = ADDR_SURF_8_BANK,
+ [6] = ADDR_SURF_4_BANK,
+ [8 ... 12] = ADDR_SURF_16_BANK,
+ [13] = ADDR_SURF_8_BANK,
+ [14] = ADDR_SURF_4_BANK,
+ },
+ { /* PIPE_CONFIG_8 */
+ [0 ... 3] = ADDR_SURF_16_BANK,
+ [4] = ADDR_SURF_8_BANK,
+ [5] = ADDR_SURF_4_BANK,
+ [6] = ADDR_SURF_2_BANK,
+ [8 ... 11] = ADDR_SURF_16_BANK,
+ [12] = ADDR_SURF_8_BANK,
+ [13] = ADDR_SURF_4_BANK,
+ [14] = ADDR_SURF_2_BANK,
+ },
+ { /* PIPE_CONFIG_16 */
+ [0 ... 3] = ADDR_SURF_16_BANK,
+ [4] = ADDR_SURF_8_BANK,
+ [5] = ADDR_SURF_4_BANK,
+ [6] = ADDR_SURF_2_BANK,
+ [8 ... 10] = ADDR_SURF_16_BANK,
+ [11] = ADDR_SURF_8_BANK,
+ [12] = ADDR_SURF_4_BANK,
+ [13 ... 14] = ADDR_SURF_2_BANK,
+ },
+};
+
/*
* Core functions
*/
@@ -2343,12 +2627,12 @@ out:
*/
static void cik_tiling_mode_table_init(struct radeon_device *rdev)
{
- const u32 num_tile_mode_states = 32;
- const u32 num_secondary_tile_mode_states = 16;
u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
u32 num_pipe_configs;
u32 num_rbs = rdev->config.cik.max_backends_per_se *
rdev->config.cik.max_shader_engines;
+ unsigned int cfg;
+ unsigned char tile_split;

switch (rdev->config.cik.mem_row_size_in_kb) {
case 1:
@@ -2367,1032 +2651,46 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
if (num_pipe_configs > 8)
num_pipe_configs = 16;

- if (num_pipe_configs == 16) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 8) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 4) {
- if (num_rbs == 4) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_rbs < 4) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 2) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P2);
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else
+ switch (num_pipe_configs) {
+ case 2: cfg = PIPE_CONFIG_2; break;
+ case 4: cfg = PIPE_CONFIG_4; break;
+ case 8: cfg = PIPE_CONFIG_8; break;
+ case 16: cfg = PIPE_CONFIG_16; break;
+ default:
DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
+ return;
+ }
+
+ for (reg_offset = 0; reg_offset < NUM_TILE_MODE_STATES; reg_offset++) {
+
+ gb_tile_moden = ARRAY_MODE(array_modes[cfg][reg_offset]) |
+ MICRO_TILE_MODE_NEW(micro_tile_modes[reg_offset]) |
+ SAMPLE_SPLIT(sample_splits[reg_offset]);
+
+ tile_split = tile_splits[reg_offset];
+ if (tile_split == TILE_SPLIT_ROW_SIZE)
+ tile_split = split_equal_to_row_size;
+ gb_tile_moden |= TILE_SPLIT(tile_split);
+
+ if (num_pipe_configs == 4 && num_rbs == 4)
+ gb_tile_moden |= PIPE_CONFIG(pipe_configs[PIPE_CONFIG_4_RBS4][reg_offset]);
+ else
+ gb_tile_moden |= PIPE_CONFIG(pipe_configs[cfg][reg_offset]);
+
+ rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
+ }
+
+ for (reg_offset = 0; reg_offset < NUM_SECONDARY_TILE_MODE_STATES; reg_offset++) {
+
+ gb_tile_moden = BANK_WIDTH(bank_widths[cfg][reg_offset]) |
+ BANK_HEIGHT(bank_heights[cfg][reg_offset]) |
+ MACRO_TILE_ASPECT(macro_tile_aspects[cfg][reg_offset]) |
+ NUM_BANKS(num_banks[cfg][reg_offset]);
+
+ rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
+ WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
+ }
}

/**
--
2.4.3

2016-03-08 00:01:08

by Deucher, Alexander

Subject: RE: [PATCH] drm/radeon: refactor CIK tiling table initialization

> -----Original Message-----
> From: Josh Poimboeuf [mailto:[email protected]]
> Sent: Monday, March 07, 2016 6:10 PM
> To: Deucher, Alexander; Koenig, Christian
> Cc: [email protected]; [email protected]; kbuild
> test robot; Ingo Molnar
> Subject: [PATCH] drm/radeon: refactor CIK tiling table initialization
>
> When compiling the radeon driver on x86_64 with
> CONFIG_STACK_VALIDATION
> enabled, objtool gives the following warnings:
>
> drivers/gpu/drm/radeon/cik.o: warning: objtool:
> cik_tiling_mode_table_init()+0x6ce: call without frame pointer save/setup
> drivers/gpu/drm/radeon/cik.o: warning: objtool:
> cik_tiling_mode_table_init()+0x72b: call without frame pointer save/setup
> drivers/gpu/drm/radeon/cik.o: warning: objtool:
> cik_tiling_mode_table_init()+0x464: call without frame pointer save/setup
> ...
>
> These are actually false positive warnings; there are no frame pointer
> bugs. Instead objtool gets confused by the jump tables created by all
> the switch statements, combined with some other gcc optimizations. It
> tries to follows all possible code paths, but it fails to realize that
> some of the paths aren't possible. For example:
>
> 4c97: 31 c0 xor %eax,%eax
> ...
> 4ca2: 89 c1 mov %eax,%ecx
> 4ca4: ff 24 cd 00 00 00 00 jmpq *0x0(,%rcx,8) 4ca7: R_X86_64_32S
> .rodata+0x148
>
> First eax is cleared to zero with the "xor %eax,%eax" instruction.
> Later, it moves the value of eax (zero in this case) to ecx, and uses
> that value to jump to the first entry in a jump table in .rodata.
>
> Because objtool doesn't have an x86 emulator, it doesn't know that rcx
> is zero. So instead of following a single code path to the first jump
> table entry, it follows all possible jump table entry paths in parallel.
>
> Usually such overactive analysis isn't a problem. In every other jump
> table in the kernel, all the jump targets have the same frame pointer
> state. But in this exceedingly rare case, different targets have
> different frame pointer states. Objtool notices that and creates the
> false positive warnings.
>
> In theory we could use the STACK_FRAME_NON_STANDARD marker to tell
> objtool to skip analysis of the function. However, that's less than
> ideal.
>
> Looking at the cik_tiling_mode_table_init() code, it seems overly
> complex with lots of repetition. So let's simplify it. All the switch
> statements and conditionals can be replaced with much simpler logic by
> generalizing the different behaviors and moving the initialization data
> into data structures.
>
> The change is a win-win: it's easier to parse for both humans and
> machines. It also reduces the binary size by about 2%:
>
> text data bss dec hex filename
> 101011 30360 0 131371 2012b cik-before.o
> 98699 30200 0 128899 1f783 cik-after.o
>
> [ Note: Unfortunately I don't know how to test this code, so it's
> completely untested. Any help or guidance with ensuring that the
> correct initialization is still being written would be greatly
> appreciated! ]

I think it would be clearer to rework it similarly to how it was reworked in amdgpu (see gfx_v8_0.c and gfx_v7_0.c in drm-next). Also ideally you'd update the similar code in si.c as well for consistency.

Alex

2016-03-09 17:48:03

by Josh Poimboeuf

Subject: Re: [PATCH] drm/radeon: refactor CIK tiling table initialization

On Mon, Mar 07, 2016 at 11:45:36PM +0000, Deucher, Alexander wrote:
> > -----Original Message-----
> > From: Josh Poimboeuf [mailto:[email protected]]
> > Sent: Monday, March 07, 2016 6:10 PM
> > To: Deucher, Alexander; Koenig, Christian
> > Cc: [email protected]; [email protected]; kbuild
> > test robot; Ingo Molnar
> > Subject: [PATCH] drm/radeon: refactor CIK tiling table initialization
> >
> > When compiling the radeon driver on x86_64 with
> > CONFIG_STACK_VALIDATION
> > enabled, objtool gives the following warnings:
> >
> > drivers/gpu/drm/radeon/cik.o: warning: objtool:
> > cik_tiling_mode_table_init()+0x6ce: call without frame pointer save/setup
> > drivers/gpu/drm/radeon/cik.o: warning: objtool:
> > cik_tiling_mode_table_init()+0x72b: call without frame pointer save/setup
> > drivers/gpu/drm/radeon/cik.o: warning: objtool:
> > cik_tiling_mode_table_init()+0x464: call without frame pointer save/setup
> > ...
> >
> > These are actually false positive warnings; there are no frame pointer
> > bugs. Instead objtool gets confused by the jump tables created by all
> > the switch statements, combined with some other gcc optimizations. It
> > tries to follows all possible code paths, but it fails to realize that
> > some of the paths aren't possible. For example:
> >
> > 4c97: 31 c0 xor %eax,%eax
> > ...
> > 4ca2: 89 c1 mov %eax,%ecx
> > 4ca4: ff 24 cd 00 00 00 00 jmpq *0x0(,%rcx,8) 4ca7: R_X86_64_32S
> > .rodata+0x148
> >
> > First eax is cleared to zero with the "xor %eax,%eax" instruction.
> > Later, it moves the value of eax (zero in this case) to ecx, and uses
> > that value to jump to the first entry in a jump table in .rodata.
> >
> > Because objtool doesn't have an x86 emulator, it doesn't know that rcx
> > is zero. So instead of following a single code path to the first jump
> > table entry, it follows all possible jump table entry paths in parallel.
> >
> > Usually such overactive analysis isn't a problem. In every other jump
> > table in the kernel, all the jump targets have the same frame pointer
> > state. But in this exceedingly rare case, different targets have
> > different frame pointer states. Objtool notices that and creates the
> > false positive warnings.
> >
> > In theory we could use the STACK_FRAME_NON_STANDARD marker to tell
> > objtool to skip analysis of the function. However, that's less than
> > ideal.
> >
> > Looking at the cik_tiling_mode_table_init() code, it seems overly
> > complex with lots of repetition. So let's simplify it. All the switch
> > statements and conditionals can be replaced with much simpler logic by
> > generalizing the different behaviors and moving the initialization data
> > into data structures.
> >
> > The change is a win-win: it's easier to parse for both humans and
> > machines. It also reduces the binary size by about 2%:
> >
> > text data bss dec hex filename
> > 101011 30360 0 131371 2012b cik-before.o
> > 98699 30200 0 128899 1f783 cik-after.o
> >
> > [ Note: Unfortunately I don't know how to test this code, so it's
> > completely untested. Any help or guidance with ensuring that the
> > correct initialization is still being written would be greatly
> > appreciated! ]
>
> I think it would be clearer to rework it similarly to how it was
> reworked in amdgpu (see gfx_v8_0.c and gfx_v7_0.c in drm-next). Also
> ideally you'd update the similar code in si.c as well for consistency.

Hi Alex,

Thanks for the pointers. As it turns out, the false positive warning in
objtool was easier to fix than I originally thought, so this warning has
gone away. But regardless I'll follow through and make a v2 patch based
on your suggestions.

--
Josh

2016-03-11 14:19:08

by Josh Poimboeuf

Subject: [PATCH v2 1/2] drm/radeon: refactor CIK tiling table initialization

Simplify the control flow of cik_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.

Signed-off-by: Josh Poimboeuf <[email protected]>
---
drivers/gpu/drm/radeon/cik.c | 1691 +++++++++++++++++-------------------------
1 file changed, 666 insertions(+), 1025 deletions(-)

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 0600140..1a92ce7 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2343,9 +2343,13 @@ out:
*/
static void cik_tiling_mode_table_init(struct radeon_device *rdev)
{
- const u32 num_tile_mode_states = 32;
- const u32 num_secondary_tile_mode_states = 16;
- u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
+ u32 *tile = rdev->config.cik.tile_mode_array;
+ u32 *macrotile = rdev->config.cik.macrotile_mode_array;
+ const u32 num_tile_mode_states =
+ ARRAY_SIZE(rdev->config.cik.tile_mode_array);
+ const u32 num_secondary_tile_mode_states =
+ ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
+ u32 reg_offset, split_equal_to_row_size;
u32 num_pipe_configs;
u32 num_rbs = rdev->config.cik.max_backends_per_se *
rdev->config.cik.max_shader_engines;
@@ -2367,1032 +2371,669 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
if (num_pipe_configs > 8)
num_pipe_configs = 16;

- if (num_pipe_configs == 16) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 8) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_2_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 4) {
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ tile[reg_offset] = 0;
+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
+ macrotile[reg_offset] = 0;
+
+ switch(num_pipe_configs) {
+ case 16:
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+
+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_2_BANK));
+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_2_BANK));
+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_2_BANK));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
+ WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
+ break;
+
+ case 8:
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+ tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+
+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_2_BANK));
+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_2_BANK));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
+ WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
+ break;
+
+ case 4:
if (num_rbs == 4) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_16x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16));
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+ tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_16x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+
} else if (num_rbs < 4) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16));
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
- NUM_BANKS(ADDR_SURF_4_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if (num_pipe_configs == 2) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
- break;
- case 1:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
- break;
- case 2:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 3:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
- break;
- case 4:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 5:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
- break;
- case 6:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
- break;
- case 7:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- TILE_SPLIT(split_equal_to_row_size));
- break;
- case 8:
- gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- PIPE_CONFIG(ADDR_SURF_P2);
- break;
- case 9:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2));
- break;
- case 10:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 11:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 12:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 13:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
- break;
- case 14:
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 16:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 17:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 27:
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2));
- break;
- case 28:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 29:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- case 30:
- gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
- MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P2) |
- SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 1:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 2:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 3:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 4:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 5:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 6:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- case 8:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 9:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 10:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 11:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 12:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 13:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
- NUM_BANKS(ADDR_SURF_16_BANK));
- break;
- case 14:
- gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
- NUM_BANKS(ADDR_SURF_8_BANK));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16));
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
+ tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
}
- } else
+
+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
+ NUM_BANKS(ADDR_SURF_4_BANK));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
+ WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
+ break;
+
+ case 2:
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
+ tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
+ tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
+ tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ TILE_SPLIT(split_equal_to_row_size));
+ tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ PIPE_CONFIG(ADDR_SURF_P2);
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2));
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2));
+ tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+ tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
+ MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P2) |
+ SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
+
+ macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+ macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
+ NUM_BANKS(ADDR_SURF_16_BANK));
+ macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+ NUM_BANKS(ADDR_SURF_8_BANK));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
+ WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
+ break;
+
+ default:
DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
+ }
}

/**
--
2.4.3

2016-03-11 14:19:14

by Josh Poimboeuf

Subject: [PATCH v2 2/2] drm/radeon: refactor SI tiling table initialization

Simplify the control flow of si_tiling_mode_table_init() similar to how
it was done in gfx_v7_0.c and gfx_v8_0.c.

Signed-off-by: Josh Poimboeuf <[email protected]>
---
drivers/gpu/drm/radeon/si.c | 925 +++++++++++++++++++++-----------------------
1 file changed, 439 insertions(+), 486 deletions(-)

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index f878d69..b3e7c8b 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2442,8 +2442,10 @@ void dce6_bandwidth_update(struct radeon_device *rdev)
*/
static void si_tiling_mode_table_init(struct radeon_device *rdev)
{
- const u32 num_tile_mode_states = 32;
- u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
+ u32 *tile = rdev->config.si.tile_mode_array;
+ const u32 num_tile_mode_states =
+ ARRAY_SIZE(rdev->config.si.tile_mode_array);
+ u32 reg_offset, split_equal_to_row_size;

switch (rdev->config.si.mem_row_size_in_kb) {
case 1:
@@ -2458,491 +2460,442 @@ static void si_tiling_mode_table_init(struct radeon_device *rdev)
break;
}

- if ((rdev->family == CHIP_TAHITI) ||
- (rdev->family == CHIP_PITCAIRN)) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0: /* non-AA compressed depth or any compressed stencil */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 1: /* 2xAA/4xAA compressed depth only */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 2: /* 8xAA compressed depth only */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 8: /* 1D and 1D Array Surfaces */
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 9: /* Displayable maps. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 10: /* Display 8bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 11: /* Display 16bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 12: /* Display 32bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 13: /* Thin. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 14: /* Thin 8 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 15: /* Thin 16 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 16: /* Thin 32 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 17: /* Thin 64 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- case 21: /* 8 bpp PRT. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 22: /* 16 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 23: /* 32 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 24: /* 64 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 25: /* 128 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
- NUM_BANKS(ADDR_SURF_8_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else if ((rdev->family == CHIP_VERDE) ||
- (rdev->family == CHIP_OLAND) ||
- (rdev->family == CHIP_HAINAN)) {
- for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
- switch (reg_offset) {
- case 0: /* non-AA compressed depth or any compressed stencil */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 1: /* 2xAA/4xAA compressed depth only */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 2: /* 8xAA compressed depth only */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 3: /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 4: /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 5: /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 6: /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 7: /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 8: /* 1D and 1D Array Surfaces */
- gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 9: /* Displayable maps. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 10: /* Display 8bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 11: /* Display 16bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 12: /* Display 32bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 13: /* Thin. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 14: /* Thin 8 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 15: /* Thin 16 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 16: /* Thin 32 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 17: /* Thin 64 bpp. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P4_8x16) |
- TILE_SPLIT(split_equal_to_row_size) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 21: /* 8 bpp PRT. */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 22: /* 16 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
- break;
- case 23: /* 32 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 24: /* 64 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
- NUM_BANKS(ADDR_SURF_16_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
- break;
- case 25: /* 128 bpp PRT */
- gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
- MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
- PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
- TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
- NUM_BANKS(ADDR_SURF_8_BANK) |
- BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
- BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
- MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
- break;
- default:
- gb_tile_moden = 0;
- break;
- }
- rdev->config.si.tile_mode_array[reg_offset] = gb_tile_moden;
- WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
- }
- } else
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ tile[reg_offset] = 0;
+
+ switch(rdev->family) {
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ /* non-AA compressed depth or any compressed stencil */
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 2xAA/4xAA compressed depth only */
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 8xAA compressed depth only */
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+ tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+ tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+ tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+ tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 1D and 1D Array Surfaces */
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Displayable maps. */
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Display 8bpp. */
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Display 16bpp. */
+ tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Display 32bpp. */
+ tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* Thin. */
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin 8 bpp. */
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* Thin 16 bpp. */
+ tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* Thin 32 bpp. */
+ tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* Thin 64 bpp. */
+ tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+ /* 8 bpp PRT. */
+ tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 16 bpp PRT */
+ tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 32 bpp PRT */
+ tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 64 bpp PRT */
+ tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 128 bpp PRT */
+ tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+ NUM_BANKS(ADDR_SURF_8_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ break;
+
+ case CHIP_VERDE:
+ case CHIP_OLAND:
+ case CHIP_HAINAN:
+ /* non-AA compressed depth or any compressed stencil */
+ tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 2xAA/4xAA compressed depth only */
+ tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 8xAA compressed depth only */
+ tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 2xAA/4xAA compressed depth with stencil (for depth buffer) */
+ tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* Maps w/ a dimension less than the 2D macro-tile dimensions (for mipmapped depth textures) */
+ tile[4] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Uncompressed 16bpp depth - and stencil buffer allocated with it */
+ tile[5] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Uncompressed 32bpp depth - and stencil buffer allocated with it */
+ tile[6] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Uncompressed 8bpp stencil without depth (drivers typically do not use) */
+ tile[7] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 1D and 1D Array Surfaces */
+ tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Displayable maps. */
+ tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Display 8bpp. */
+ tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* Display 16bpp. */
+ tile[11] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Display 32bpp. */
+ tile[12] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin. */
+ tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin 8 bpp. */
+ tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin 16 bpp. */
+ tile[15] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin 32 bpp. */
+ tile[16] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* Thin 64 bpp. */
+ tile[17] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+ TILE_SPLIT(split_equal_to_row_size) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 8 bpp PRT. */
+ tile[21] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 16 bpp PRT */
+ tile[22] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
+ /* 32 bpp PRT */
+ tile[23] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 64 bpp PRT */
+ tile[24] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+ NUM_BANKS(ADDR_SURF_16_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
+ /* 128 bpp PRT */
+ tile[25] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+ MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+ PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
+ TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+ NUM_BANKS(ADDR_SURF_8_BANK) |
+ BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+ BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+ MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
+
+ for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
+ WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
+ break;
+
+ default:
DRM_ERROR("unknown asic: 0x%x\n", rdev->family);
+ }
}

static void si_select_se_sh(struct radeon_device *rdev,
--
2.4.3

2016-03-11 14:59:24

by Christian König

Subject: Re: [PATCH v2 1/2] drm/radeon: refactor CIK tiling table initialization

Am 11.03.2016 um 15:18 schrieb Josh Poimboeuf:
> Simplify the control flow of cik_tiling_mode_table_init() similar to how
> it was done in gfx_v7_0.c and gfx_v8_0.c.
>
> Signed-off-by: Josh Poimboeuf <[email protected]>

I'm not so deep into the tilling config stuff, but briefly skimming over
it it clearly looks good to me.

Patch is Acked-by: Christian K?nig <[email protected]>

Thanks for the help,
Christian.

> ---
> drivers/gpu/drm/radeon/cik.c | 1691 +++++++++++++++++-------------------------
> 1 file changed, 666 insertions(+), 1025 deletions(-)
>
> diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
> index 0600140..1a92ce7 100644
> --- a/drivers/gpu/drm/radeon/cik.c
> +++ b/drivers/gpu/drm/radeon/cik.c
> @@ -2343,9 +2343,13 @@ out:
> */
> static void cik_tiling_mode_table_init(struct radeon_device *rdev)
> {
> - const u32 num_tile_mode_states = 32;
> - const u32 num_secondary_tile_mode_states = 16;
> - u32 reg_offset, gb_tile_moden, split_equal_to_row_size;
> + u32 *tile = rdev->config.cik.tile_mode_array;
> + u32 *macrotile = rdev->config.cik.macrotile_mode_array;
> + const u32 num_tile_mode_states =
> + ARRAY_SIZE(rdev->config.cik.tile_mode_array);
> + const u32 num_secondary_tile_mode_states =
> + ARRAY_SIZE(rdev->config.cik.macrotile_mode_array);
> + u32 reg_offset, split_equal_to_row_size;
> u32 num_pipe_configs;
> u32 num_rbs = rdev->config.cik.max_backends_per_se *
> rdev->config.cik.max_shader_engines;
> @@ -2367,1032 +2371,669 @@ static void cik_tiling_mode_table_init(struct radeon_device *rdev)
> if (num_pipe_configs > 8)
> num_pipe_configs = 16;
>
> - if (num_pipe_configs == 16) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 8) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_2_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 4) {
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + tile[reg_offset] = 0;
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + macrotile[reg_offset] = 0;
> +
> + switch(num_pipe_configs) {
> + case 16:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P16_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 8:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_2_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 4:
> if (num_rbs == 4) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_16x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> } else if (num_rbs < 4) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16));
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> - NUM_BANKS(ADDR_SURF_4_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - } else if (num_pipe_configs == 2) {
> - for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> - break;
> - case 1:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> - break;
> - case 2:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 3:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> - break;
> - case 4:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 5:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> - break;
> - case 6:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> - break;
> - case 7:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - TILE_SPLIT(split_equal_to_row_size));
> - break;
> - case 8:
> - gb_tile_moden = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> - PIPE_CONFIG(ADDR_SURF_P2);
> - break;
> - case 9:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 10:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 11:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 12:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 13:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> - break;
> - case 14:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 16:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 17:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 27:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2));
> - break;
> - case 28:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 29:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - case 30:
> - gb_tile_moden = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> - MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> - PIPE_CONFIG(ADDR_SURF_P2) |
> - SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.tile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> - }
> - for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++) {
> - switch (reg_offset) {
> - case 0:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 1:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 2:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 3:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 4:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 5:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 6:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - case 8:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 9:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 10:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 11:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 12:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 13:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> - NUM_BANKS(ADDR_SURF_16_BANK));
> - break;
> - case 14:
> - gb_tile_moden = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> - BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> - MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> - NUM_BANKS(ADDR_SURF_8_BANK));
> - break;
> - default:
> - gb_tile_moden = 0;
> - break;
> - }
> - rdev->config.cik.macrotile_mode_array[reg_offset] = gb_tile_moden;
> - WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), gb_tile_moden);
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16));
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P4_8x16) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> }
> - } else
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
> + NUM_BANKS(ADDR_SURF_4_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + case 2:
> + tile[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B));
> + tile[1] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B));
> + tile[2] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[3] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B));
> + tile[4] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[5] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING));
> + tile[6] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B));
> + tile[7] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DEPTH_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + TILE_SPLIT(split_equal_to_row_size));
> + tile[8] = ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
> + PIPE_CONFIG(ADDR_SURF_P2);
> + tile[9] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2));
> + tile[10] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[11] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[12] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_DISPLAY_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[13] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING));
> + tile[14] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[16] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[17] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_THIN_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[27] = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2));
> + tile[28] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[29] = (ARRAY_MODE(ARRAY_PRT_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> + tile[30] = (ARRAY_MODE(ARRAY_PRT_2D_TILED_THIN1) |
> + MICRO_TILE_MODE_NEW(ADDR_SURF_ROTATED_MICRO_TILING) |
> + PIPE_CONFIG(ADDR_SURF_P2) |
> + SAMPLE_SPLIT(ADDR_SURF_SAMPLE_SPLIT_2));
> +
> + macrotile[0] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[1] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[2] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[3] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[4] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[5] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[6] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> + macrotile[8] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_8) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[9] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_4) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[10] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[11] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[12] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[13] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
> + NUM_BANKS(ADDR_SURF_16_BANK));
> + macrotile[14] = (BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
> + BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
> + MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
> + NUM_BANKS(ADDR_SURF_8_BANK));
> +
> + for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++)
> + WREG32(GB_TILE_MODE0 + (reg_offset * 4), tile[reg_offset]);
> + for (reg_offset = 0; reg_offset < num_secondary_tile_mode_states; reg_offset++)
> + WREG32(GB_MACROTILE_MODE0 + (reg_offset * 4), macrotile[reg_offset]);
> + break;
> +
> + default:
> DRM_ERROR("unknown num pipe config: 0x%x\n", num_pipe_configs);
> + }
> }
>
> /**