This patch is in the continuation to the discussions which happened on
'commit f89504300e94 ("spi: Stacked/parallel memories bindings")' for
adding dt-binding support for stacked/parallel memories.
This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI
driver to add stacked and parallel memories support.
The first nine patches
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
https://lore.kernel.org/all/[email protected]/
of the previous series got applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
But the rest of the patches in the series did not get applied as failure
was reported for spi driver with GPIO CS, so send the remaining patches
in the series after rebasing it on top of for-next branch and fixing the
issue.
---
BRANCH: for-next
Changes in v7:
- Updated spi_dev_check() to avoid failures for spi driver GPIO CS and
moved the error message from __spi_add_device() to spi_dev_check().
- Resolved code indentation issue in spi_set_cs().
- In spi_set_cs() call spi_delay_exec( ) once if the controller supports
multi cs with both the CS backed by GPIO.
- Updated __spi_validate()to add checks for both the GPIO CS.
- Replaced cs_index_mask bit mask magic number with SPI_CS_CNT_MAX.
- Updated struct spi_controller to represent multi CS capability of the
spi controller through a flag bit SPI_CONTROLLER_MULTI_CS instead of
a boolen structure member "multi_cs_cap".
- Updated 1/7 & 7/7 patch description .
Changes in v6:
- Rebased on top of latest v6.3-rc1 and fixed merge conflicts in
spi-mpc512x-psc.c, sfdp.c, spansion.c files and removed spi-omap-100k.c.
- Updated spi_dev_check( ) to reject new devices if any one of the
chipselect is used by another device.
Changes in v5:
- Rebased the patches on top of v6.3-rc1 and fixed the merge conflicts.
- Fixed compilation warnings in spi-sh-msiof.c with shmobile_defconfig
Changes in v4:
- Fixed build error in spi-pl022.c file - reported by Mark.
- Fixed build error in spi-sn-f-ospi.c file.
- Added Reviewed-by: Serge Semin <[email protected]> tag.
- Added two more patches to replace spi->chip_select with API calls in
mpc832x_rdb.c & cs35l41_hda_spi.c files.
Changes in v3:
- Rebased the patches on top of
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next
- Added a patch to convert spi_nor_otp_region_len(nor) &
spi_nor_otp_n_regions(nor) macros into inline functions
- Added Reviewed-by & Acked-by tags
Changes in v2:
- Rebased the patches on top of v6.2-rc1
- Created separate patch to add get & set APIs for spi->chip_select &
spi->cs_gpiod, and replaced all spi->chip_select and spi->cs_gpiod
references with the API calls.
- Created separate patch to add get & set APIs for nor->params.
---
Amit Kumar Mahapatra (7):
spi: Add stacked and parallel memories support in SPI core
mtd: spi-nor: Convert macros with inline functions
mtd: spi-nor: Add APIs to set/get nor->params
mtd: spi-nor: Add stacked memories support in spi-nor
spi: spi-zynqmp-gqspi: Add stacked memories support in GQSPI driver
mtd: spi-nor: Add parallel memories support in spi-nor
spi: spi-zynqmp-gqspi: Add parallel memories support in GQSPI driver
drivers/mtd/spi-nor/atmel.c | 17 +-
drivers/mtd/spi-nor/core.c | 665 ++++++++++++++++++++++++++-----
drivers/mtd/spi-nor/core.h | 8 +
drivers/mtd/spi-nor/debugfs.c | 4 +-
drivers/mtd/spi-nor/gigadevice.c | 4 +-
drivers/mtd/spi-nor/issi.c | 11 +-
drivers/mtd/spi-nor/macronix.c | 6 +-
drivers/mtd/spi-nor/micron-st.c | 39 +-
drivers/mtd/spi-nor/otp.c | 48 ++-
drivers/mtd/spi-nor/sfdp.c | 29 +-
drivers/mtd/spi-nor/spansion.c | 50 ++-
drivers/mtd/spi-nor/sst.c | 7 +-
drivers/mtd/spi-nor/swp.c | 22 +-
drivers/mtd/spi-nor/winbond.c | 10 +-
drivers/mtd/spi-nor/xilinx.c | 18 +-
drivers/spi/spi-zynqmp-gqspi.c | 58 ++-
drivers/spi/spi.c | 226 +++++++----
include/linux/mtd/spi-nor.h | 18 +-
include/linux/spi/spi.h | 32 +-
19 files changed, 1002 insertions(+), 270 deletions(-)
--
2.17.1
Each flash that is connected in stacked mode should have a separate
parameter structure. So, the flash parameter member(*params) of the spi_nor
structure is changed to an array (*params[2]). The array is used to store
the parameters of each flash connected in stacked configuration.
The current implementation assumes that a maximum of two flashes are
connected in stacked mode and both the flashes are of same make but can
differ in sizes. So, except the sizes all other flash parameters of both
the flashes are identical.
SPI-NOR is not aware of the chip_select values, for any incoming request
SPI-NOR will decide the flash index with the help of individual flash size
and the configuration type (single/stacked). SPI-NOR will pass on the flash
index information to the SPI core & SPI driver by setting the appropriate
bit in nor->spimem->spi->cs_index_mask. For example, if nth bit of
nor->spimem->spi->cs_index_mask is set then the driver would
assert/de-assert spi->chip_slect[n].
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/core.c | 282 +++++++++++++++++++++++++++++-------
drivers/mtd/spi-nor/core.h | 4 +
include/linux/mtd/spi-nor.h | 12 +-
3 files changed, 244 insertions(+), 54 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 66b6934b4465..0bc6b42f276c 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -1441,13 +1441,18 @@ static int spi_nor_erase_multi_sectors(struct spi_nor *nor, u64 addr, u32 len)
static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- u32 addr, len;
+ struct spi_nor_flash_parameter *params;
+ u32 addr, len, offset, cur_cs_num = 0;
uint32_t rem;
int ret;
+ u64 sz;
dev_dbg(nor->dev, "at 0x%llx, len %lld\n", (long long)instr->addr,
(long long)instr->len);
+ params = spi_nor_get_params(nor, 0);
+ sz = params->size;
+
if (spi_nor_has_uniform_erase(nor)) {
div_u64_rem(instr->len, mtd->erasesize, &rem);
if (rem)
@@ -1465,26 +1470,30 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
unsigned long timeout;
- ret = spi_nor_write_enable(nor);
- if (ret)
- goto erase_err;
+ while (cur_cs_num < SNOR_FLASH_CNT_MAX && params) {
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
- ret = spi_nor_erase_chip(nor);
- if (ret)
- goto erase_err;
+ ret = spi_nor_erase_chip(nor);
+ if (ret)
+ goto erase_err;
- /*
- * Scale the timeout linearly with the size of the flash, with
- * a minimum calibrated to an old 2MB flash. We could try to
- * pull these from CFI/SFDP, but these values should be good
- * enough for now.
- */
- timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
- CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
- (unsigned long)(mtd->size / SZ_2M));
- ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
- if (ret)
- goto erase_err;
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(params->size / SZ_2M));
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+ if (ret)
+ goto erase_err;
+ cur_cs_num++;
+ }
/* REVISIT in some cases we could speed up erasing large regions
* by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
@@ -1493,12 +1502,26 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
/* "sector"-at-a-time erase */
} else if (spi_nor_has_uniform_erase(nor)) {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+
while (len) {
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
ret = spi_nor_write_enable(nor);
if (ret)
goto erase_err;
- ret = spi_nor_erase_sector(nor, addr);
+ offset = addr;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+
+ ret = spi_nor_erase_sector(nor, offset);
if (ret)
goto erase_err;
@@ -1508,13 +1531,45 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
addr += mtd->erasesize;
len -= mtd->erasesize;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
/* erase multiple sectors */
} else {
- ret = spi_nor_erase_multi_sectors(nor, addr, len);
- if (ret)
- goto erase_err;
+ u64 erase_len = 0;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ /* perform multi sector erase onec per Flash*/
+ while (len) {
+ erase_len = (len > (sz - addr)) ? (sz - addr) : len;
+ offset = addr;
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+ ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ if (ret)
+ goto erase_err;
+ len -= erase_len;
+ addr += erase_len;
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
ret = spi_nor_write_disable(nor);
@@ -1713,7 +1768,10 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
size_t *retlen, u_char *buf)
{
struct spi_nor *nor = mtd_to_spi_nor(mtd);
- ssize_t ret;
+ struct spi_nor_flash_parameter *params;
+ ssize_t ret, read_len;
+ u32 cur_cs_num = 0;
+ u64 sz;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
@@ -1721,9 +1779,23 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
if (ret)
return ret;
+ params = spi_nor_get_params(nor, 0);
+ sz = params->size;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
while (len) {
loff_t addr = from;
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ read_len = (len > (sz - addr)) ? (sz - addr) : len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+
addr = spi_nor_convert_addr(nor, addr);
ret = spi_nor_read_data(nor, addr, len, buf);
@@ -1735,11 +1807,22 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
if (ret < 0)
goto read_err;
- WARN_ON(ret > len);
+ WARN_ON(ret > read_len);
*retlen += ret;
buf += ret;
from += ret;
len -= ret;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ *
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && (from > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+
}
ret = 0;
@@ -1759,13 +1842,22 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
struct spi_nor *nor = mtd_to_spi_nor(mtd);
struct spi_nor_flash_parameter *params;
size_t page_offset, page_remain, i;
+ u32 page_size, cur_cs_num = 0;
ssize_t ret;
- u32 page_size;
+ u64 sz;
dev_dbg(nor->dev, "to 0x%08x, len %zd\n", (u32)to, len);
params = spi_nor_get_params(nor, 0);
page_size = params->page_size;
+ sz = params->size;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
ret = spi_nor_lock_and_prep(nor);
if (ret)
@@ -1790,6 +1882,10 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
/* the size of data remaining on the first page */
page_remain = min_t(size_t, page_size - page_offset, len - i);
+ nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+
addr = spi_nor_convert_addr(nor, addr);
ret = spi_nor_write_enable(nor);
@@ -1806,6 +1902,15 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
goto write_err;
*retlen += written;
i += written;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && ((to + i) > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
write_err:
@@ -1918,8 +2023,6 @@ int spi_nor_hwcaps_pp2cmd(u32 hwcaps)
static int spi_nor_spimem_check_op(struct spi_nor *nor,
struct spi_mem_op *op)
{
- struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
-
/*
* First test with 4 address bytes. The opcode itself might
* be a 3B addressing opcode but we don't care, because
@@ -1928,7 +2031,7 @@ static int spi_nor_spimem_check_op(struct spi_nor *nor,
*/
op->addr.nbytes = 4;
if (!spi_mem_supports_op(nor->spimem, op)) {
- if (params->size > SZ_16M)
+ if (nor->mtd.size > SZ_16M)
return -EOPNOTSUPP;
/* If flash size <= 16MB, 3 address bytes are sufficient */
@@ -2525,6 +2628,10 @@ static void spi_nor_init_fixup_flags(struct spi_nor *nor)
static void spi_nor_late_init_params(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct device_node *np = spi_nor_get_flash_node(nor);
+ u64 flash_size[SNOR_FLASH_CNT_MAX];
+ u32 idx = 0, i = 0;
+ int rc;
if (nor->manufacturer && nor->manufacturer->fixups &&
nor->manufacturer->fixups->late_init)
@@ -2542,6 +2649,36 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
*/
if (nor->flags & SNOR_F_HAS_LOCK && !params->locking_ops)
spi_nor_init_default_locking_ops(nor);
+ /*
+ * The flashes that are connected in stacked mode should be of same make.
+ * Except the flash size all other properties are identical for all the
+ * flashes connected in stacked mode.
+ * The flashes that are connected in parallel mode should be identical.
+ */
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = of_property_read_u64_index(np, "stacked-memories", idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_STACKED))
+ nor->flags |= SNOR_F_HAS_STACKED;
+ }
+ }
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ for (idx = 1; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL);
+ if (params) {
+ memcpy(params, spi_nor_get_params(nor, 0), sizeof(*params));
+ params->size = flash_size[idx];
+ spi_nor_set_params(nor, idx, params);
+ }
+ }
+ }
}
/**
@@ -2750,22 +2887,36 @@ static int spi_nor_octal_dtr_enable(struct spi_nor *nor, bool enable)
*/
static int spi_nor_quad_enable(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
+ struct spi_nor_flash_parameter *params;
+ int err, idx;
- if (!params->quad_enable)
- return 0;
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params) {
+ if (!params->quad_enable)
+ return 0;
- if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
- spi_nor_get_protocol_width(nor->write_proto) == 4))
- return 0;
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4))
+ return 0;
+ /*
+ * Set the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 0x01 << idx;
- return params->quad_enable(nor);
+ err = params->quad_enable(nor);
+ if (err)
+ return err;
+ }
+ }
+ return err;
}
static int spi_nor_init(struct spi_nor *nor)
{
- struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
- int err;
+ struct spi_nor_flash_parameter *params;
+ int err, idx;
err = spi_nor_octal_dtr_enable(nor, true);
if (err) {
@@ -2806,9 +2957,19 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- err = params->set_4byte_addr_mode(nor, true);
- if (err && err != -ENOTSUPP)
- return err;
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ err = params->set_4byte_addr_mode(nor, true);
+ if (err && err != -ENOTSUPP)
+ return err;
+ }
+ }
}
return 0;
@@ -2924,19 +3085,31 @@ void spi_nor_restore(struct spi_nor *nor)
{
struct spi_nor_flash_parameter *params;
int ret;
+ int idx;
/* restore the addressing mode */
if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET) {
- params = spi_nor_get_params(nor, 0);
- ret = params->set_4byte_addr_mode(nor, false);
- if (ret)
- /*
- * Do not stop the execution in the hope that the flash
- * will default to the 3-byte address mode after the
- * software reset.
- */
- dev_err(nor->dev, "Failed to exit 4-byte address mode, err = %d\n", ret);
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ ret = params->set_4byte_addr_mode(nor, false);
+ if (ret)
+ /*
+ * Do not stop the execution in the hope that the flash
+ * will default to the 3-byte address mode after the
+ * software reset.
+ */
+ dev_err(nor->dev,
+ "Failed to exit 4-byte address mode, err = %d\n",
+ ret);
+ }
+ }
}
if (nor->flags & SNOR_F_SOFT_RESET)
@@ -3004,6 +3177,8 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
struct spi_nor_flash_parameter *params = spi_nor_get_params(nor, 0);
struct mtd_info *mtd = &nor->mtd;
struct device *dev = nor->dev;
+ u64 total_sz = 0;
+ int idx;
spi_nor_set_mtd_locking_ops(nor);
spi_nor_set_mtd_otp_ops(nor);
@@ -3019,7 +3194,12 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
mtd->_erase = spi_nor_erase;
mtd->writesize = params->writesize;
mtd->writebufsize = params->page_size;
- mtd->size = params->size;
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params)
+ total_sz += params->size;
+ }
+ mtd->size = total_sz;
mtd->_read = spi_nor_read;
/* Might be already set by some SST flashes. */
if (!mtd->_write)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index 25423225c29d..cff2f9c389b8 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -11,6 +11,9 @@
#define SPI_NOR_MAX_ID_LEN 6
+/* In single configuration enable CS0 */
+#define SPI_NOR_ENABLE_CS0 BIT(0)
+
/* Standard SPI NOR flash operations. */
#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
@@ -130,6 +133,7 @@ enum spi_nor_option_flags {
SNOR_F_IO_MODE_EN_VOLATILE = BIT(11),
SNOR_F_SOFT_RESET = BIT(12),
SNOR_F_SWP_IS_VOLATILE = BIT(13),
+ SNOR_F_HAS_STACKED = BIT(14),
};
struct spi_nor_read_command {
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index 338b73125131..99f0f2ede444 100644
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -127,6 +127,12 @@
#define SR2_LB3 BIT(5) /* Security Register Lock Bit 3 */
#define SR2_QUAD_EN_BIT7 BIT(7)
+/*
+ * Maximum number of flashes that can be connected
+ * in stacked/parallel configuration
+ */
+#define SNOR_FLASH_CNT_MAX 2
+
/* Supported SPI protocols */
#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
#define SNOR_PROTO_INST_SHIFT 16
@@ -399,7 +405,7 @@ struct spi_nor {
const struct spi_nor_controller_ops *controller_ops;
- struct spi_nor_flash_parameter *params;
+ struct spi_nor_flash_parameter *params[SNOR_FLASH_CNT_MAX];
struct {
struct spi_mem_dirmap_desc *rdesc;
@@ -422,13 +428,13 @@ static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
static inline struct spi_nor_flash_parameter *spi_nor_get_params(const struct spi_nor *nor, u8 idx)
{
- return nor->params;
+ return nor->params[idx];
}
static inline void spi_nor_set_params(struct spi_nor *nor, u8 idx,
struct spi_nor_flash_parameter *params)
{
- nor->params = params;
+ nor->params[idx] = params;
}
/**
* spi_nor_scan() - scan the SPI NOR
--
2.17.1
During probe GQSPI driver sets SPI_CONTROLLER_MULTI_CS bit in ctlr->flags
for notifying SPI core about multi CS capability of the controller.
In parallel mode the controller can either split the data between both the
flash or can send the same data to both the flashes, this is determined by
the STRIPE bit. While sending commands to the flashes the GQSPI driver
send the same command to both the flashes by resetting the STRIPE bit, but
while writing/reading data to & from the flash the GQSPI driver splits the
data evenly between both the flashes by setting the STRIPE bit.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/spi/spi-zynqmp-gqspi.c | 39 +++++++++++++++++++++++++++++++++-
1 file changed, 38 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-zynqmp-gqspi.c b/drivers/spi/spi-zynqmp-gqspi.c
index 3d2b92a88e8a..2b2b5c0385fc 100644
--- a/drivers/spi/spi-zynqmp-gqspi.c
+++ b/drivers/spi/spi-zynqmp-gqspi.c
@@ -23,6 +23,7 @@
#include <linux/spinlock.h>
#include <linux/workqueue.h>
#include <linux/spi/spi-mem.h>
+#include <linux/mtd/spi-nor.h>
/* Generic QSPI register offsets */
#define GQSPI_CONFIG_OFST 0x00000100
@@ -192,6 +193,7 @@ struct qspi_platform_data {
* @op_lock: Operational lock
* @speed_hz: Current SPI bus clock speed in hz
* @has_tapdelay: Used for tapdelay register available in qspi
+ * @is_parallel: Used for multi CS support
*/
struct zynqmp_qspi {
struct spi_controller *ctlr;
@@ -214,8 +216,33 @@ struct zynqmp_qspi {
struct mutex op_lock;
u32 speed_hz;
bool has_tapdelay;
+ bool is_parallel;
};
+/**
+ * zynqmp_gqspi_update_stripe - For GQSPI controller data stripe capabilities
+ * @op: Pointer to mem ops
+ * Return: Status of the data stripe
+ *
+ * Returns true if data stripe need to be enabled, else returns false
+ */
+bool zynqmp_gqspi_update_stripe(const struct spi_mem_op *op)
+{
+ if (op->cmd.opcode == SPINOR_OP_BE_4K ||
+ op->cmd.opcode == SPINOR_OP_BE_32K ||
+ op->cmd.opcode == SPINOR_OP_CHIP_ERASE ||
+ op->cmd.opcode == SPINOR_OP_SE ||
+ op->cmd.opcode == SPINOR_OP_BE_32K_4B ||
+ op->cmd.opcode == SPINOR_OP_SE_4B ||
+ op->cmd.opcode == SPINOR_OP_BE_4K_4B ||
+ op->cmd.opcode == SPINOR_OP_WRSR ||
+ op->cmd.opcode == SPINOR_OP_BRWR ||
+ (op->cmd.opcode == SPINOR_OP_WRSR2 && !op->addr.nbytes))
+ return false;
+
+ return true;
+}
+
/**
* zynqmp_gqspi_read - For GQSPI controller read operation
* @xqspi: Pointer to the zynqmp_qspi structure
@@ -470,7 +497,14 @@ static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
- if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
+ if ((qspi->cs_index_mask & GQSPI_SELECT_LOWER_CS) &&
+ (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS)) {
+ zynqmp_gqspi_selectslave(xqspi,
+ GQSPI_SELECT_FLASH_CS_BOTH,
+ GQSPI_SELECT_FLASH_BUS_BOTH);
+ if (!xqspi->is_parallel)
+ xqspi->is_parallel = true;
+ } else if (qspi->cs_index_mask & GQSPI_SELECT_UPPER_CS) {
zynqmp_gqspi_selectslave(xqspi,
GQSPI_SELECT_FLASH_CS_UPPER,
GQSPI_SELECT_FLASH_BUS_LOWER);
@@ -1139,6 +1173,8 @@ static int zynqmp_qspi_exec_op(struct spi_mem *mem,
}
if (op->data.nbytes) {
+ if (xqspi->is_parallel && zynqmp_gqspi_update_stripe(op))
+ genfifoentry |= GQSPI_GENFIFO_STRIPE;
reinit_completion(&xqspi->data_completion);
if (op->data.dir == SPI_MEM_DATA_OUT) {
xqspi->txbuf = (u8 *)op->data.buf.out;
@@ -1334,6 +1370,7 @@ static int zynqmp_qspi_probe(struct platform_device *pdev)
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
ctlr->dev.of_node = np;
ctlr->auto_runtime_pm = true;
+ ctlr->flags |= SPI_CONTROLLER_MULTI_CS;
ret = devm_spi_register_controller(&pdev->dev, ctlr);
if (ret) {
--
2.17.1
The current implementation assumes that a maximum of two flashes are
connected in parallel mode. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR sets 0th bit for CS0 & 1st bit for CS1 in
nor->spimem->spi->cs_index_mask. The QSPI driver will then assert/de-assert
CS0 & CS1.
Write operation in parallel mode are performed in page size * 2 chunks as
each write operation results in writing both the flashes. For doubling the
address space each operation is performed at addr/2 flash offset, where
addr is the address specified by the user.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/mtd/spi-nor/core.c | 514 +++++++++++++++++++++++---------
drivers/mtd/spi-nor/core.h | 4 +
drivers/mtd/spi-nor/micron-st.c | 5 +
3 files changed, 384 insertions(+), 139 deletions(-)
diff --git a/drivers/mtd/spi-nor/core.c b/drivers/mtd/spi-nor/core.c
index 0bc6b42f276c..18fc4a1c28d4 100644
--- a/drivers/mtd/spi-nor/core.c
+++ b/drivers/mtd/spi-nor/core.c
@@ -464,17 +464,29 @@ int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)
op.data.nbytes = 2;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ op.data.nbytes = 2;
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
} else {
- ret = spi_nor_controller_ops_read_reg(nor, SPINOR_OP_RDSR, sr,
- 1);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ ret = spi_nor_controller_ops_read_reg(nor,
+ SPINOR_OP_RDSR,
+ sr, 2);
+ else
+ ret = spi_nor_controller_ops_read_reg(nor,
+ SPINOR_OP_RDSR,
+ sr, 1);
}
if (ret)
dev_dbg(nor->dev, "error %d reading SR\n", ret);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ sr[0] |= sr[1];
+
return ret;
}
@@ -1466,12 +1478,122 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
if (ret)
return ret;
- /* whole-chip erase? */
- if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
- unsigned long timeout;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL)) {
+ /* whole-chip erase? */
+ if (len == mtd->size && !(nor->flags & SNOR_F_NO_OP_CHIP_ERASE)) {
+ unsigned long timeout;
+
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && params) {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
+
+ ret = spi_nor_erase_chip(nor);
+ if (ret)
+ goto erase_err;
+
+ /*
+ * Scale the timeout linearly with the size of the flash, with
+ * a minimum calibrated to an old 2MB flash. We could try to
+ * pull these from CFI/SFDP, but these values should be good
+ * enough for now.
+ */
+ timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
+ CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
+ (unsigned long)(params->size /
+ SZ_2M));
+ ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
+ if (ret)
+ goto erase_err;
+
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ }
+
+ /* REVISIT in some cases we could speed up erasing large regions
+ * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
+ * to use "small sector erase", but that's not always optimal.
+ */
+
+ /* "sector"-at-a-time erase */
+ } else if (spi_nor_has_uniform_erase(nor)) {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) &&
+ (addr > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ while (len) {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
+
+ offset = addr;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+ ret = spi_nor_erase_sector(nor, offset);
+ if (ret)
+ goto erase_err;
+
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto erase_err;
+
+ addr += mtd->erasesize;
+ len -= mtd->erasesize;
+
+ /*
+ * Flash cross over condition in stacked mode.
+ */
+ if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ }
+
+ /* erase multiple sectors */
+ } else {
+ u64 erase_len = 0;
+
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) &&
+ (addr > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ /* perform multi sector erase onec per Flash*/
+ while (len) {
+ erase_len = (len > (sz - addr)) ? (sz - addr) : len;
+ offset = addr;
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ if (nor->flags & SNOR_F_HAS_STACKED) {
+ params = spi_nor_get_params(nor, cur_cs_num);
+ offset -= (sz - params->size);
+ }
+ ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ if (ret)
+ goto erase_err;
+ len -= erase_len;
+ addr += erase_len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ }
+ } else {
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+
+ /* whole-chip erase? */
+ if (len == mtd->size && !(nor->flags &
+ SNOR_F_NO_OP_CHIP_ERASE)) {
+ unsigned long timeout;
- while (cur_cs_num < SNOR_FLASH_CNT_MAX && params) {
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
ret = spi_nor_write_enable(nor);
if (ret)
goto erase_err;
@@ -1488,90 +1610,45 @@ static int spi_nor_erase(struct mtd_info *mtd, struct erase_info *instr)
*/
timeout = max(CHIP_ERASE_2MB_READY_WAIT_JIFFIES,
CHIP_ERASE_2MB_READY_WAIT_JIFFIES *
- (unsigned long)(params->size / SZ_2M));
+ (unsigned long)(mtd->size / SZ_2M));
ret = spi_nor_wait_till_ready_with_timeout(nor, timeout);
if (ret)
goto erase_err;
- cur_cs_num++;
- }
-
- /* REVISIT in some cases we could speed up erasing large regions
- * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
- * to use "small sector erase", but that's not always optimal.
- */
- /* "sector"-at-a-time erase */
- } else if (spi_nor_has_uniform_erase(nor)) {
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
- }
+ /* REVISIT in some cases we could speed up erasing large regions
+ * by using SPINOR_OP_SE instead of SPINOR_OP_BE_4K. We may have set up
+ * to use "small sector erase", but that's not always optimal.
+ */
- while (len) {
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- ret = spi_nor_write_enable(nor);
- if (ret)
- goto erase_err;
+ /* "sector"-at-a-time erase */
+ } else if (spi_nor_has_uniform_erase(nor)) {
+ while (len) {
+ ret = spi_nor_write_enable(nor);
+ if (ret)
+ goto erase_err;
- offset = addr;
- if (nor->flags & SNOR_F_HAS_STACKED) {
- params = spi_nor_get_params(nor, cur_cs_num);
- offset -= (sz - params->size);
- }
+ offset = addr / 2;
- ret = spi_nor_erase_sector(nor, offset);
- if (ret)
- goto erase_err;
-
- ret = spi_nor_wait_till_ready(nor);
- if (ret)
- goto erase_err;
+ ret = spi_nor_erase_sector(nor, offset);
+ if (ret)
+ goto erase_err;
- addr += mtd->erasesize;
- len -= mtd->erasesize;
+ ret = spi_nor_wait_till_ready(nor);
+ if (ret)
+ goto erase_err;
- /*
- * Flash cross over condition in stacked mode.
- */
- if ((nor->flags & SNOR_F_HAS_STACKED) && (addr > sz - 1)) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ addr += mtd->erasesize;
+ len -= mtd->erasesize;
}
- }
-
- /* erase multiple sectors */
- } else {
- u64 erase_len = 0;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (addr > sz - 1) && params) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
- }
- /* perform multi sector erase onec per Flash*/
- while (len) {
- erase_len = (len > (sz - addr)) ? (sz - addr) : len;
- offset = addr;
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- if (nor->flags & SNOR_F_HAS_STACKED) {
- params = spi_nor_get_params(nor, cur_cs_num);
- offset -= (sz - params->size);
- }
- ret = spi_nor_erase_multi_sectors(nor, offset, erase_len);
+ /* erase multiple sectors */
+ } else {
+ offset = addr / 2;
+ ret = spi_nor_erase_multi_sectors(nor, offset, len);
if (ret)
goto erase_err;
- len -= erase_len;
- addr += erase_len;
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
}
}
-
ret = spi_nor_write_disable(nor);
erase_err:
@@ -1771,34 +1848,59 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
struct spi_nor_flash_parameter *params;
ssize_t ret, read_len;
u32 cur_cs_num = 0;
- u64 sz;
+ u_char *readbuf;
+ bool is_ofst_odd = false;
+ u64 sz = 0;
dev_dbg(nor->dev, "from 0x%08x, len %zd\n", (u32)from, len);
- ret = spi_nor_lock_and_prep(nor);
- if (ret)
- return ret;
-
params = spi_nor_get_params(nor, 0);
sz = params->size;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
+ /*
+ * Cannot read from odd offset in parallel mode, so read
+ * len + 1 from offset + 1 and ignore offset[0] data.
+ */
+ if ((nor->flags & SNOR_F_HAS_PARALLEL) && (from & 0x01)) {
+ from = (loff_t)(from - 1);
+ len = (size_t)(len + 1);
+ is_ofst_odd = true;
+ readbuf = kmalloc(len, GFP_KERNEL);
+ if (!readbuf)
+ return -ENOMEM;
+ } else {
+ readbuf = buf;
+ }
+
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL)) {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (from > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
}
+ ret = spi_nor_lock_and_prep(nor);
+ if (ret)
+ return ret;
+
while (len) {
loff_t addr = from;
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- read_len = (len > (sz - addr)) ? (sz - addr) : len;
- params = spi_nor_get_params(nor, cur_cs_num);
- addr -= (sz - params->size);
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ read_len = len;
+ addr /= 2;
+ } else {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ read_len = (len > (sz - addr)) ? (sz - addr) : len;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+ }
addr = spi_nor_convert_addr(nor, addr);
- ret = spi_nor_read_data(nor, addr, len, buf);
+ ret = spi_nor_read_data(nor, addr, read_len, readbuf);
if (ret == 0) {
/* We shouldn't see 0-length reads */
ret = -EIO;
@@ -1808,8 +1910,20 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
goto read_err;
WARN_ON(ret > read_len);
- *retlen += ret;
+ if (is_ofst_odd) {
+ /*
+ * Cannot read from odd offset in parallel mode.
+ * So read len + 1 from offset + 1 from the flash
+ * and copy len data from readbuf[1].
+ */
+ memcpy(buf, (readbuf + 1), (len - 1));
+ *retlen += (ret - 1);
+ } else {
+ *retlen += ret;
+ }
buf += ret;
+ if (!is_ofst_odd)
+ readbuf += ret;
from += ret;
len -= ret;
@@ -1827,6 +1941,9 @@ static int spi_nor_read(struct mtd_info *mtd, loff_t from, size_t len,
ret = 0;
read_err:
+ if (is_ofst_odd)
+ kfree(readbuf);
+
spi_nor_unlock_and_unprep(nor);
return ret;
}
@@ -1852,13 +1969,38 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
page_size = params->page_size;
sz = params->size;
- /* Determine the flash from which the operation need to start */
- while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) {
- cur_cs_num++;
- params = spi_nor_get_params(nor, cur_cs_num);
- sz += params->size;
- }
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ /*
+ * Cannot write to odd offset in parallel mode,
+ * so write 2 byte first.
+ */
+ if (to & 0x01) {
+ u8 two[2] = {0xff, buf[0]};
+ size_t written_len;
+
+ ret = spi_nor_write(mtd, to & ~1, 2, &written_len, two);
+ if (ret < 0)
+ return ret;
+ *retlen += 1; /* We've written only one actual byte */
+ ++buf;
+ --len;
+ ++to;
+ }
+ /*
+ * Write operation are performed in page size chunks and in
+ * parallel memories both the flashes are written simultaneously,
+ * hence doubled the page_size.
+ */
+ page_size <<= 1;
+ } else {
+ /* Determine the flash from which the operation need to start */
+ while ((cur_cs_num < SNOR_FLASH_CNT_MAX) && (to > sz - 1) && params) {
+ cur_cs_num++;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ sz += params->size;
+ }
+ }
ret = spi_nor_lock_and_prep(nor);
if (ret)
return ret;
@@ -1882,9 +2024,14 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
/* the size of data remaining on the first page */
page_remain = min_t(size_t, page_size - page_offset, len - i);
- nor->spimem->spi->cs_index_mask = 0x01 << cur_cs_num;
- params = spi_nor_get_params(nor, cur_cs_num);
- addr -= (sz - params->size);
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ addr /= 2;
+ } else {
+ nor->spimem->spi->cs_index_mask = 1 << cur_cs_num;
+ params = spi_nor_get_params(nor, cur_cs_num);
+ addr -= (sz - params->size);
+ }
addr = spi_nor_convert_addr(nor, addr);
@@ -2332,7 +2479,15 @@ static int spi_nor_select_erase(struct spi_nor *nor)
if (!erase)
return -EINVAL;
nor->erase_opcode = erase->opcode;
- mtd->erasesize = erase->size;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = erase->size * 2;
+ else
+ mtd->erasesize = erase->size;
return 0;
}
@@ -2350,7 +2505,15 @@ static int spi_nor_select_erase(struct spi_nor *nor)
if (!erase)
return -EINVAL;
- mtd->erasesize = erase->size;
+ /*
+ * In parallel-memories the erase operation is
+ * performed on both the flashes simultaneously
+ * so, double the erasesize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->erasesize = erase->size * 2;
+ else
+ mtd->erasesize = erase->size;
return 0;
}
@@ -2668,7 +2831,22 @@ static void spi_nor_late_init_params(struct spi_nor *nor)
nor->flags |= SNOR_F_HAS_STACKED;
}
}
- if (nor->flags & SNOR_F_HAS_STACKED) {
+ i = 0;
+ idx = 0;
+ while (i < SNOR_FLASH_CNT_MAX) {
+ rc = of_property_read_u64_index(np, "parallel-memories", idx, &flash_size[i]);
+ if (rc == -EINVAL) {
+ break;
+ } else if (rc == -EOVERFLOW) {
+ idx++;
+ } else {
+ idx++;
+ i++;
+ if (!(nor->flags & SNOR_F_HAS_PARALLEL))
+ nor->flags |= SNOR_F_HAS_PARALLEL;
+ }
+ }
+ if (nor->flags & (SNOR_F_HAS_STACKED | SNOR_F_HAS_PARALLEL)) {
for (idx = 1; idx < SNOR_FLASH_CNT_MAX; idx++) {
params = spi_nor_get_params(nor, idx);
params = devm_kzalloc(nor->dev, sizeof(*params), GFP_KERNEL);
@@ -2890,24 +3068,42 @@ static int spi_nor_quad_enable(struct spi_nor *nor)
struct spi_nor_flash_parameter *params;
int err, idx;
- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
- params = spi_nor_get_params(nor, idx);
- if (params) {
- if (!params->quad_enable)
- return 0;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ params = spi_nor_get_params(nor, 0);
+ if (!params->quad_enable)
+ return 0;
- if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
- spi_nor_get_protocol_width(nor->write_proto) == 4))
- return 0;
- /*
- * Set the appropriate CS index before
- * issuing the command.
- */
- nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4))
+ return 0;
+ /*
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
+ */
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ err = params->quad_enable(nor);
+ if (err)
+ return err;
+ } else {
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params) {
+ if (!params->quad_enable)
+ return 0;
- err = params->quad_enable(nor);
- if (err)
- return err;
+ if (!(spi_nor_get_protocol_width(nor->read_proto) == 4 ||
+ spi_nor_get_protocol_width(nor->write_proto) == 4))
+ return 0;
+ /*
+ * Set the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+
+ err = params->quad_enable(nor);
+ if (err)
+ return err;
+ }
}
}
return err;
@@ -2957,17 +3153,29 @@ static int spi_nor_init(struct spi_nor *nor)
*/
WARN_ONCE(nor->flags & SNOR_F_BROKEN_RESET,
"enabling reset hack; may not recover from unexpected reboots\n");
- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
- params = spi_nor_get_params(nor, idx);
- if (params) {
- /*
- * Select the appropriate CS index before
- * issuing the command.
- */
- nor->spimem->spi->cs_index_mask = 0x01 << idx;
- err = params->set_4byte_addr_mode(nor, true);
- if (err && err != -ENOTSUPP)
- return err;
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ /*
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
+ */
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ params = spi_nor_get_params(nor, 0);
+ err = params->set_4byte_addr_mode(nor, true);
+ if (err && err != -ENOTSUPP)
+ return err;
+ } else {
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (params) {
+ /*
+ * Select the appropriate CS index before
+ * issuing the command.
+ */
+ nor->spimem->spi->cs_index_mask = 1 << idx;
+ err = params->set_4byte_addr_mode(nor, true);
+ if (err && err != -ENOTSUPP)
+ return err;
+ }
}
}
}
@@ -3090,20 +3298,39 @@ void spi_nor_restore(struct spi_nor *nor)
/* restore the addressing mode */
if (nor->addr_nbytes == 4 && !(nor->flags & SNOR_F_4B_OPCODES) &&
nor->flags & SNOR_F_BROKEN_RESET) {
- for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
- params = spi_nor_get_params(nor, idx);
- if (params) {
+ if (nor->flags & SNOR_F_HAS_PARALLEL) {
+ /*
+ * In parallel mode both chip selects i.e., CS0 &
+ * CS1 need to be asserted simulatneously.
+ */
+ nor->spimem->spi->cs_index_mask = SPI_NOR_ENABLE_MULTI_CS;
+ params = spi_nor_get_params(nor, 0);
+ ret = params->set_4byte_addr_mode(nor, false);
+ if (ret)
+ /*
+ * Do not stop the execution in the hope that the flash
+ * will default to the 3-byte address mode after the
+ * software reset.
+ */
+ dev_err(nor->dev,
+ "Failed to exit 4-byte address mode, err = %d\n",
+ ret);
+ } else {
+ for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
+ params = spi_nor_get_params(nor, idx);
+ if (!params)
+ break;
/*
* Select the appropriate CS index before
* issuing the command.
*/
- nor->spimem->spi->cs_index_mask = 0x01 << idx;
+ nor->spimem->spi->cs_index_mask = 1 << idx;
ret = params->set_4byte_addr_mode(nor, false);
if (ret)
/*
- * Do not stop the execution in the hope that the flash
- * will default to the 3-byte address mode after the
- * software reset.
+ * Do not stop the execution in the hope that the
+ * flash will default to the 3-byte address mode
+ * after the software reset.
*/
dev_err(nor->dev,
"Failed to exit 4-byte address mode, err = %d\n",
@@ -3193,7 +3420,16 @@ static void spi_nor_set_mtd_info(struct spi_nor *nor)
else
mtd->_erase = spi_nor_erase;
mtd->writesize = params->writesize;
- mtd->writebufsize = params->page_size;
+ /*
+ * In parallel-memories the write operation is
+ * performed on both the flashes simultaneously
+ * one page per flash, so double the writebufsize.
+ */
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ mtd->writebufsize = params->page_size << 1;
+ else
+ mtd->writebufsize = params->page_size;
+
for (idx = 0; idx < SNOR_FLASH_CNT_MAX; idx++) {
params = spi_nor_get_params(nor, idx);
if (params)
diff --git a/drivers/mtd/spi-nor/core.h b/drivers/mtd/spi-nor/core.h
index cff2f9c389b8..6c6df417a9c6 100644
--- a/drivers/mtd/spi-nor/core.h
+++ b/drivers/mtd/spi-nor/core.h
@@ -14,6 +14,9 @@
/* In single configuration enable CS0 */
#define SPI_NOR_ENABLE_CS0 BIT(0)
+/* In parallel configuration enable multiple CS */
+#define SPI_NOR_ENABLE_MULTI_CS (BIT(0) | BIT(1))
+
/* Standard SPI NOR flash operations. */
#define SPI_NOR_READID_OP(naddr, ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_RDID, 0), \
@@ -134,6 +137,7 @@ enum spi_nor_option_flags {
SNOR_F_SOFT_RESET = BIT(12),
SNOR_F_SWP_IS_VOLATILE = BIT(13),
SNOR_F_HAS_STACKED = BIT(14),
+ SNOR_F_HAS_PARALLEL = BIT(15),
};
struct spi_nor_read_command {
diff --git a/drivers/mtd/spi-nor/micron-st.c b/drivers/mtd/spi-nor/micron-st.c
index b93e16094b6c..9be39f237dfc 100644
--- a/drivers/mtd/spi-nor/micron-st.c
+++ b/drivers/mtd/spi-nor/micron-st.c
@@ -357,6 +357,9 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
op.data.nbytes = 2;
}
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ op.data.nbytes = 2;
+
spi_nor_spimem_setup_op(nor, &op, nor->reg_proto);
ret = spi_mem_exec_op(nor->spimem, &op);
@@ -368,6 +371,8 @@ static int micron_st_nor_read_fsr(struct spi_nor *nor, u8 *fsr)
if (ret)
dev_dbg(nor->dev, "error %d reading FSR\n", ret);
+ if (nor->flags & SNOR_F_HAS_PARALLEL)
+ fsr[0] &= fsr[1];
return ret;
}
--
2.17.1
For supporting multiple CS the SPI device need to be aware of all the CS
values. So, the "chip_select" member in the spi_device structure is now an
array that holds all the CS values.
spi_device structure now has a "cs_index_mask" member. This acts as an
index to the chip_select array. If nth bit of spi->cs_index_mask is set
then the driver would assert spi->chip_select[n].
In parallel mode all the chip selects are asserted/de-asserted
simultaneously and each byte of data is stored in both devices, the even
bits in one, the odd bits in the other. The split is automatically handled
by the GQSPI controller. The GQSPI controller supports a maximum of two
flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag bit is
added in the spi controntroller flags, through ctlr->flags the spi core
will make sure that the controller is capable of handling multiple chip
selects at once.
For supporting multiple CS via GPIO the cs_gpiod member of the spi_device
structure is now an array that holds the gpio descriptor for each
chipselect.
Multi CS support using GPIO is not tested due to unavailability of
necessary hardware setup.
Multi CS configuration with one native CS and one GPIO CS is not supported
as this configuration could not be tested due to unavailability of
necessary hardware setup.
Signed-off-by: Amit Kumar Mahapatra <[email protected]>
---
drivers/spi/spi.c | 226 ++++++++++++++++++++++++++++------------
include/linux/spi/spi.h | 32 ++++--
2 files changed, 183 insertions(+), 75 deletions(-)
diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
index 9036d7a50674..04d7322170c4 100644
--- a/drivers/spi/spi.c
+++ b/drivers/spi/spi.c
@@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev, void *data)
{
struct spi_device *spi = to_spi_device(dev);
struct spi_device *new_spi = data;
+ int idx, nw_idx;
- if (spi->controller == new_spi->controller &&
- spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi, 0))
- return -EBUSY;
+ if (spi->controller == new_spi->controller) {
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX; nw_idx++) {
+ if ((idx != 0 && !spi_get_chipselect(spi, idx)) ||
+ (nw_idx != 0 && !spi_get_chipselect(spi, nw_idx))) {
+ continue;
+ } else if (spi_get_chipselect(spi, idx) ==
+ spi_get_chipselect(new_spi, nw_idx)) {
+ dev_err(dev,
+ "chipselect %d already in use\n",
+ spi_get_chipselect(new_spi, nw_idx));
+ return -EBUSY;
+ }
+ }
+ }
+ }
return 0;
}
@@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device *spi)
{
struct spi_controller *ctlr = spi->controller;
struct device *dev = ctlr->dev.parent;
- int status;
+ int status, idx;
/*
* We need to make sure there's no other device with this
@@ -638,8 +652,6 @@ static int __spi_add_device(struct spi_device *spi)
*/
status = bus_for_each_dev(&spi_bus_type, NULL, spi, spi_dev_check);
if (status) {
- dev_err(dev, "chipselect %d already in use\n",
- spi_get_chipselect(spi, 0));
return status;
}
@@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device *spi)
return -ENODEV;
}
- if (ctlr->cs_gpiods)
- spi_set_csgpiod(spi, 0, ctlr->cs_gpiods[spi_get_chipselect(spi, 0)]);
+ if (ctlr->cs_gpiods) {
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
+ }
/*
* Drivers may modify this initial i/o setup, but will
@@ -690,13 +704,15 @@ int spi_add_device(struct spi_device *spi)
{
struct spi_controller *ctlr = spi->controller;
struct device *dev = ctlr->dev.parent;
- int status;
+ int status, idx;
- /* Chipselects are numbered 0..max; validate. */
- if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
- dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
- ctlr->num_chipselect);
- return -EINVAL;
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ /* Chipselects are numbered 0..max; validate. */
+ if (spi_get_chipselect(spi, idx) >= ctlr->num_chipselect) {
+ dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx),
+ ctlr->num_chipselect);
+ return -EINVAL;
+ }
}
/* Set the bus ID string */
@@ -713,12 +729,15 @@ static int spi_add_device_locked(struct spi_device *spi)
{
struct spi_controller *ctlr = spi->controller;
struct device *dev = ctlr->dev.parent;
+ int idx;
- /* Chipselects are numbered 0..max; validate. */
- if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
- dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, 0),
- ctlr->num_chipselect);
- return -EINVAL;
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
+ /* Chipselects are numbered 0..max; validate. */
+ if (spi_get_chipselect(spi, idx) >= ctlr->num_chipselect) {
+ dev_err(dev, "cs%d >= max %d\n", spi_get_chipselect(spi, idx),
+ ctlr->num_chipselect);
+ return -EINVAL;
+ }
}
/* Set the bus ID string */
@@ -966,58 +985,118 @@ static void spi_res_release(struct spi_controller *ctlr, struct spi_message *mes
static void spi_set_cs(struct spi_device *spi, bool enable, bool force)
{
bool activate = enable;
+ u32 cs_num = __ffs(spi->cs_index_mask);
+ int idx;
/*
- * Avoid calling into the driver (or doing delays) if the chip select
- * isn't actually changing from the last time this was called.
+ * In parallel mode all the chip selects are asserted/de-asserted
+ * at once
*/
- if (!force && ((enable && spi->controller->last_cs == spi_get_chipselect(spi, 0)) ||
- (!enable && spi->controller->last_cs != spi_get_chipselect(spi, 0))) &&
- (spi->controller->last_cs_mode_high == (spi->mode & SPI_CS_HIGH)))
- return;
-
- trace_spi_set_cs(spi, activate);
-
- spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0) : -1;
- spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
-
- if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate)
- spi_delay_exec(&spi->cs_hold, NULL);
-
- if (spi->mode & SPI_CS_HIGH)
- enable = !enable;
+ if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) == SPI_PARALLEL_CS_MASK) {
+ spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
+
+ if ((spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) && !activate)
+ spi_delay_exec(&spi->cs_hold, NULL);
+
+ if (spi->mode & SPI_CS_HIGH)
+ enable = !enable;
+
+ if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi, 1)) {
+ if (!(spi->mode & SPI_NO_CS)) {
+ /*
+ * Historically ACPI has no means of the GPIO polarity and
+ * thus the SPISerialBus() resource defines it on the per-chip
+ * basis. In order to avoid a chain of negations, the GPIO
+ * polarity is considered being Active High. Even for the cases
+ * when _DSD() is involved (in the updated versions of ACPI)
+ * the GPIO CS polarity must be defined Active High to avoid
+ * ambiguity. That's why we use enable, that takes SPI_CS_HIGH
+ * into account.
+ */
+ if (has_acpi_companion(&spi->dev)) {
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
+ !enable);
+ } else {
+ for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
+ /* Polarity handled by GPIO library */
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
+ activate);
+ }
+ }
+ /* Some SPI masters need both GPIO CS & slave_select */
+ if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
+ spi->controller->set_cs)
+ spi->controller->set_cs(spi, !enable);
+ } else if (spi->controller->set_cs) {
+ spi->controller->set_cs(spi, !enable);
+ }
- if (spi_get_csgpiod(spi, 0)) {
- if (!(spi->mode & SPI_NO_CS)) {
- /*
- * Historically ACPI has no means of the GPIO polarity and
- * thus the SPISerialBus() resource defines it on the per-chip
- * basis. In order to avoid a chain of negations, the GPIO
- * polarity is considered being Active High. Even for the cases
- * when _DSD() is involved (in the updated versions of ACPI)
- * the GPIO CS polarity must be defined Active High to avoid
- * ambiguity. That's why we use enable, that takes SPI_CS_HIGH
- * into account.
- */
- if (has_acpi_companion(&spi->dev))
- gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
+ if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1) ||
+ !spi->controller->set_cs_timing) {
+ if (activate)
+ spi_delay_exec(&spi->cs_setup, NULL);
else
- /* Polarity handled by GPIO library */
- gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
+ spi_delay_exec(&spi->cs_inactive, NULL);
}
- /* Some SPI masters need both GPIO CS & slave_select */
- if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
- spi->controller->set_cs)
+ } else {
+ /*
+ * Avoid calling into the driver (or doing delays) if the chip select
+ * isn't actually changing from the last time this was called.
+ */
+ if (!force && ((enable && spi->controller->last_cs ==
+ spi_get_chipselect(spi, cs_num)) ||
+ (!enable && spi->controller->last_cs !=
+ spi_get_chipselect(spi, cs_num))) &&
+ (spi->controller->last_cs_mode_high ==
+ (spi->mode & SPI_CS_HIGH)))
+ return;
+
+ trace_spi_set_cs(spi, activate);
+
+ spi->controller->last_cs = enable ? spi_get_chipselect(spi, cs_num) : -1;
+ spi->controller->last_cs_mode_high = spi->mode & SPI_CS_HIGH;
+
+ if ((spi_get_csgpiod(spi, cs_num) || !spi->controller->set_cs_timing) && !activate)
+ spi_delay_exec(&spi->cs_hold, NULL);
+
+ if (spi->mode & SPI_CS_HIGH)
+ enable = !enable;
+
+ if (spi_get_csgpiod(spi, cs_num)) {
+ if (!(spi->mode & SPI_NO_CS)) {
+ /*
+ * Historically ACPI has no means of the GPIO polarity and
+ * thus the SPISerialBus() resource defines it on the per-chip
+ * basis. In order to avoid a chain of negations, the GPIO
+ * polarity is considered being Active High. Even for the cases
+ * when _DSD() is involved (in the updated versions of ACPI)
+ * the GPIO CS polarity must be defined Active High to avoid
+ * ambiguity. That's why we use enable, that takes SPI_CS_HIGH
+ * into account.
+ */
+ if (has_acpi_companion(&spi->dev))
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
+ !enable);
+ else
+ /* Polarity handled by GPIO library */
+ gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
+ activate);
+ }
+ /* Some SPI masters need both GPIO CS & slave_select */
+ if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
+ spi->controller->set_cs)
+ spi->controller->set_cs(spi, !enable);
+ } else if (spi->controller->set_cs) {
spi->controller->set_cs(spi, !enable);
- } else if (spi->controller->set_cs) {
- spi->controller->set_cs(spi, !enable);
- }
+ }
- if (spi_get_csgpiod(spi, 0) || !spi->controller->set_cs_timing) {
- if (activate)
- spi_delay_exec(&spi->cs_setup, NULL);
- else
- spi_delay_exec(&spi->cs_inactive, NULL);
+ if (spi_get_csgpiod(spi, cs_num) || !spi->controller->set_cs_timing) {
+ if (activate)
+ spi_delay_exec(&spi->cs_setup, NULL);
+ else
+ spi_delay_exec(&spi->cs_inactive, NULL);
+ }
}
}
@@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct device_node *nc,
static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
struct device_node *nc)
{
- u32 value;
- int rc;
+ u32 value, cs[SPI_CS_CNT_MAX] = {0};
+ int rc, idx;
/* Mode (clock phase/polarity/etc.) */
if (of_property_read_bool(nc, "spi-cpha"))
@@ -2320,13 +2399,21 @@ static int of_spi_parse_dt(struct spi_controller *ctlr, struct spi_device *spi,
}
/* Device address */
- rc = of_property_read_u32(nc, "reg", &value);
- if (rc) {
+ rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
+ SPI_CS_CNT_MAX);
+ if (rc < 0 || rc > ctlr->num_chipselect) {
dev_err(&ctlr->dev, "%pOF has no valid 'reg' property (%d)\n",
nc, rc);
return rc;
+ } else if ((of_property_read_bool(nc, "parallel-memories")) &&
+ (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
+ dev_err(&ctlr->dev, "SPI controller doesn't support multi CS\n");
+ return -EINVAL;
}
- spi_set_chipselect(spi, 0, value);
+ for (idx = 0; idx < rc; idx++)
+ spi_set_chipselect(spi, idx, cs[idx]);
+ /* By default set the spi->cs_index_mask as 1 */
+ spi->cs_index_mask = 0x01;
/* Device speed */
if (!of_property_read_u32(nc, "spi-max-frequency", &value))
@@ -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device *spi, struct spi_message *message)
* cs_change is set for each transfer.
*/
if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits & SPI_CS_WORD) ||
- spi_get_csgpiod(spi, 0))) {
+ spi_get_csgpiod(spi, 0) ||
+ spi_get_csgpiod(spi, 1))) {
size_t maxsize;
int ret;
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 873ced6ae4ca..6453b246e0af 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -19,6 +19,11 @@
#include <linux/acpi.h>
#include <linux/u64_stats_sync.h>
+/* Max no. of CS supported per spi device */
+#define SPI_CS_CNT_MAX 2
+
+/* chip select mask */
+#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
struct dma_chan;
struct software_node;
struct ptp_system_timestamp;
@@ -166,6 +171,7 @@ extern void spi_transfer_cs_change_delay_exec(struct spi_message *msg,
* deasserted. If @cs_change_delay is used from @spi_transfer, then the
* two delays will be added up.
* @pcpu_statistics: statistics for the spi_device
+ * @cs_index_mask: Bit mask of the active chipselect(s) in the chipselect array
*
* A @spi_device is used to interchange data between an SPI slave
* (usually a discrete chip) and CPU memory.
@@ -181,7 +187,7 @@ struct spi_device {
struct spi_controller *controller;
struct spi_controller *master; /* Compatibility layer */
u32 max_speed_hz;
- u8 chip_select;
+ u8 chip_select[SPI_CS_CNT_MAX];
u8 bits_per_word;
bool rt;
#define SPI_NO_TX BIT(31) /* No transmit wire */
@@ -202,7 +208,7 @@ struct spi_device {
void *controller_data;
char modalias[SPI_NAME_SIZE];
const char *driver_override;
- struct gpio_desc *cs_gpiod; /* Chip select gpio desc */
+ struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /* Chip select gpio desc */
struct spi_delay word_delay; /* Inter-word delay */
/* CS delays */
struct spi_delay cs_setup;
@@ -212,6 +218,13 @@ struct spi_device {
/* The statistics */
struct spi_statistics __percpu *pcpu_statistics;
+ /* Bit mask of the chipselect(s) that the driver need to use from
+ * the chipselect array.When the controller is capable to handle
+ * multiple chip selects & memories are connected in parallel
+ * then more than one bit need to be set in cs_index_mask.
+ */
+ u32 cs_index_mask : SPI_CS_CNT_MAX;
+
/*
* likely need more hooks for more protocol options affecting how
* the controller talks to each chip, like:
@@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const struct spi_device *spi)
static inline u8 spi_get_chipselect(const struct spi_device *spi, u8 idx)
{
- return spi->chip_select;
+ return spi->chip_select[idx];
}
static inline void spi_set_chipselect(struct spi_device *spi, u8 idx, u8 chipselect)
{
- spi->chip_select = chipselect;
+ spi->chip_select[idx] = chipselect;
}
static inline struct gpio_desc *spi_get_csgpiod(const struct spi_device *spi, u8 idx)
{
- return spi->cs_gpiod;
+ return spi->cs_gpiod[idx];
}
static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx, struct gpio_desc *csgpiod)
{
- spi->cs_gpiod = csgpiod;
+ spi->cs_gpiod[idx] = csgpiod;
}
/**
@@ -388,6 +401,8 @@ extern struct spi_device *spi_new_ancillary_device(struct spi_device *spi, u8 ch
* @bus_lock_spinlock: spinlock for SPI bus locking
* @bus_lock_mutex: mutex for exclusion of multiple callers
* @bus_lock_flag: indicates that the SPI bus is locked for exclusive use
+ * @multi_cs_cap: indicates that the SPI Controller can assert/de-assert
+ * more than one chip select at once.
* @setup: updates the device mode and clocking records used by a
* device's SPI controller; protocol code may call this. This
* must fail if an unrecognized or unsupported mode is requested.
@@ -554,6 +569,11 @@ struct spi_controller {
#define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx */
#define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select slave */
+ /*
+ * The spi-controller has multi chip select capability and can
+ * assert/de-assert more than one chip select at once.
+ */
+#define SPI_CONTROLLER_MULTI_CS BIT(6)
/* Flag indicating if the allocation of this struct is devres-managed */
bool devm_allocated;
--
2.17.1
Hi,
> -----Original Message-----
> From: Amit Kumar Mahapatra <[email protected]>
> Sent: Thursday, April 6, 2023 7:54 AM
> To: [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; [email protected]; linux-
> [email protected]; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Amit Kumar Mahapatra <amit.kumar-
> [email protected]>
> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
support
> in SPI core
>
> For supporting multiple CS the SPI device need to be aware of all
the CS
> values. So, the "chip_select" member in the spi_device structure is
now
> an
> array that holds all the CS values.
>
> spi_device structure now has a "cs_index_mask" member. This acts as
an
> index to the chip_select array. If nth bit of spi->cs_index_mask is
set
> then the driver would assert spi->chip_select[n].
>
> In parallel mode all the chip selects are asserted/de-asserted
> simultaneously and each byte of data is stored in both devices, the
even
> bits in one, the odd bits in the other. The split is automatically
handled
> by the GQSPI controller. The GQSPI controller supports a maximum of
> two
> flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag
> bit is
> added in the spi controntroller flags, through ctlr->flags the spi
core
> will make sure that the controller is capable of handling multiple
chip
> selects at once.
>
> For supporting multiple CS via GPIO the cs_gpiod member of the
> spi_device
> structure is now an array that holds the gpio descriptor for each
> chipselect.
>
> Multi CS support using GPIO is not tested due to unavailability of
> necessary hardware setup.
>
> Multi CS configuration with one native CS and one GPIO CS is not
> supported
> as this configuration could not be tested due to unavailability of
> necessary hardware setup.
I've tested this chain on a released laptop (HP EliteBook 840 G9)
which uses
SPI to interface to 2 amps, one amp uses a native CS and the other
uses a
GPIO CS, and I noticed that when using this chain, the second amp no
longer
works.
Thanks,
Stefan Binding
>
> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> [email protected]>
> ---
> drivers/spi/spi.c | 226
++++++++++++++++++++++++++++------------
> include/linux/spi/spi.h | 32 ++++--
> 2 files changed, 183 insertions(+), 75 deletions(-)
>
> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c
> index 9036d7a50674..04d7322170c4 100644
> --- a/drivers/spi/spi.c
> +++ b/drivers/spi/spi.c
> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
> void *data)
> {
> struct spi_device *spi = to_spi_device(dev);
> struct spi_device *new_spi = data;
> + int idx, nw_idx;
>
> - if (spi->controller == new_spi->controller &&
> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
0))
> - return -EBUSY;
> + if (spi->controller == new_spi->controller) {
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> nw_idx++) {
> + if ((idx != 0 &&
!spi_get_chipselect(spi,
> idx)) ||
> + (nw_idx != 0 &&
> !spi_get_chipselect(spi, nw_idx))) {
> + continue;
> + } else if (spi_get_chipselect(spi,
idx) ==
> + spi_get_chipselect(new_spi,
nw_idx))
> {
> + dev_err(dev,
> + "chipselect %d already
> in use\n",
> +
> spi_get_chipselect(new_spi, nw_idx));
> + return -EBUSY;
> + }
> + }
> + }
> + }
> return 0;
> }
>
> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
> *spi)
> {
> struct spi_controller *ctlr = spi->controller;
> struct device *dev = ctlr->dev.parent;
> - int status;
> + int status, idx;
>
> /*
> * We need to make sure there's no other device with this
> @@ -638,8 +652,6 @@ static int __spi_add_device(struct spi_device
> *spi)
> */
> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> spi_dev_check);
> if (status) {
> - dev_err(dev, "chipselect %d already in use\n",
> - spi_get_chipselect(spi, 0));
> return status;
> }
>
> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
> *spi)
> return -ENODEV;
> }
>
> - if (ctlr->cs_gpiods)
> - spi_set_csgpiod(spi, 0, ctlr-
> >cs_gpiods[spi_get_chipselect(spi, 0)]);
> + if (ctlr->cs_gpiods) {
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> + spi_set_csgpiod(spi, idx, ctlr-
> >cs_gpiods[spi_get_chipselect(spi, idx)]);
> + }
>
> /*
> * Drivers may modify this initial i/o setup, but will
> @@ -690,13 +704,15 @@ int spi_add_device(struct spi_device *spi)
> {
> struct spi_controller *ctlr = spi->controller;
> struct device *dev = ctlr->dev.parent;
> - int status;
> + int status, idx;
>
> - /* Chipselects are numbered 0..max; validate. */
> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> - dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, 0),
> - ctlr->num_chipselect);
> - return -EINVAL;
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + /* Chipselects are numbered 0..max; validate. */
> + if (spi_get_chipselect(spi, idx) >=
ctlr->num_chipselect) {
> + dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, idx),
> + ctlr->num_chipselect);
> + return -EINVAL;
> + }
> }
>
> /* Set the bus ID string */
> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
> spi_device *spi)
> {
> struct spi_controller *ctlr = spi->controller;
> struct device *dev = ctlr->dev.parent;
> + int idx;
>
> - /* Chipselects are numbered 0..max; validate. */
> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> - dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, 0),
> - ctlr->num_chipselect);
> - return -EINVAL;
> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> + /* Chipselects are numbered 0..max; validate. */
> + if (spi_get_chipselect(spi, idx) >=
ctlr->num_chipselect) {
> + dev_err(dev, "cs%d >= max %d\n",
> spi_get_chipselect(spi, idx),
> + ctlr->num_chipselect);
> + return -EINVAL;
> + }
> }
>
> /* Set the bus ID string */
> @@ -966,58 +985,118 @@ static void spi_res_release(struct
> spi_controller *ctlr, struct spi_message *mes
> static void spi_set_cs(struct spi_device *spi, bool enable, bool
force)
> {
> bool activate = enable;
> + u32 cs_num = __ffs(spi->cs_index_mask);
> + int idx;
>
> /*
> - * Avoid calling into the driver (or doing delays) if the chip
select
> - * isn't actually changing from the last time this was called.
> + * In parallel mode all the chip selects are
asserted/de-asserted
> + * at once
> */
> - if (!force && ((enable && spi->controller->last_cs ==
> spi_get_chipselect(spi, 0)) ||
> - (!enable && spi->controller->last_cs !=
> spi_get_chipselect(spi, 0))) &&
> - (spi->controller->last_cs_mode_high == (spi->mode &
> SPI_CS_HIGH)))
> - return;
> -
> - trace_spi_set_cs(spi, activate);
> -
> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
: -1;
> - spi->controller->last_cs_mode_high = spi->mode &
> SPI_CS_HIGH;
> -
> - if ((spi_get_csgpiod(spi, 0) ||
!spi->controller->set_cs_timing)
> && !activate)
> - spi_delay_exec(&spi->cs_hold, NULL);
> -
> - if (spi->mode & SPI_CS_HIGH)
> - enable = !enable;
> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
> SPI_PARALLEL_CS_MASK) {
> + spi->controller->last_cs_mode_high = spi->mode &
> SPI_CS_HIGH;
> +
> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> >set_cs_timing) && !activate)
> + spi_delay_exec(&spi->cs_hold, NULL);
> +
> + if (spi->mode & SPI_CS_HIGH)
> + enable = !enable;
> +
> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
1)) {
> + if (!(spi->mode & SPI_NO_CS)) {
> + /*
> + * Historically ACPI has no means of
the
> GPIO polarity and
> + * thus the SPISerialBus() resource
> defines it on the per-chip
> + * basis. In order to avoid a chain of
> negations, the GPIO
> + * polarity is considered being Active
> High. Even for the cases
> + * when _DSD() is involved (in the
> updated versions of ACPI)
> + * the GPIO CS polarity must be
defined
> Active High to avoid
> + * ambiguity. That's why we use
enable,
> that takes SPI_CS_HIGH
> + * into account.
> + */
> + if (has_acpi_companion(&spi->dev)) {
> + for (idx = 0; idx <
> SPI_CS_CNT_MAX; idx++)
> +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> +
> !enable);
> + } else {
> + for (idx = 0; idx <
> SPI_CS_CNT_MAX; idx++)
> + /* Polarity handled by
> GPIO library */
> +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> +
> activate);
> + }
> + }
> + /* Some SPI masters need both GPIO CS &
> slave_select */
> + if ((spi->controller->flags &
> SPI_MASTER_GPIO_SS) &&
> + spi->controller->set_cs)
> + spi->controller->set_cs(spi, !enable);
> + } else if (spi->controller->set_cs) {
> + spi->controller->set_cs(spi, !enable);
> + }
>
> - if (spi_get_csgpiod(spi, 0)) {
> - if (!(spi->mode & SPI_NO_CS)) {
> - /*
> - * Historically ACPI has no means of the GPIO
> polarity and
> - * thus the SPISerialBus() resource defines it
on
> the per-chip
> - * basis. In order to avoid a chain of
negations,
> the GPIO
> - * polarity is considered being Active High.
Even
> for the cases
> - * when _DSD() is involved (in the updated
> versions of ACPI)
> - * the GPIO CS polarity must be defined Active
> High to avoid
> - * ambiguity. That's why we use enable, that
> takes SPI_CS_HIGH
> - * into account.
> - */
> - if (has_acpi_companion(&spi->dev))
> -
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
||
> + !spi->controller->set_cs_timing) {
> + if (activate)
> + spi_delay_exec(&spi->cs_setup, NULL);
> else
> - /* Polarity handled by GPIO library */
> -
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> + spi_delay_exec(&spi->cs_inactive,
> NULL);
> }
> - /* Some SPI masters need both GPIO CS & slave_select
> */
> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
> - spi->controller->set_cs)
> + } else {
> + /*
> + * Avoid calling into the driver (or doing delays) if
the
> chip select
> + * isn't actually changing from the last time this was
> called.
> + */
> + if (!force && ((enable && spi->controller->last_cs ==
> + spi_get_chipselect(spi, cs_num)) ||
> + (!enable && spi->controller->last_cs
!=
> + spi_get_chipselect(spi, cs_num))) &&
> + (spi->controller->last_cs_mode_high ==
> + (spi->mode & SPI_CS_HIGH)))
> + return;
> +
> + trace_spi_set_cs(spi, activate);
> +
> + spi->controller->last_cs = enable ?
> spi_get_chipselect(spi, cs_num) : -1;
> + spi->controller->last_cs_mode_high = spi->mode &
> SPI_CS_HIGH;
> +
> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >set_cs_timing) && !activate)
> + spi_delay_exec(&spi->cs_hold, NULL);
> +
> + if (spi->mode & SPI_CS_HIGH)
> + enable = !enable;
> +
> + if (spi_get_csgpiod(spi, cs_num)) {
> + if (!(spi->mode & SPI_NO_CS)) {
> + /*
> + * Historically ACPI has no means of
the
> GPIO polarity and
> + * thus the SPISerialBus() resource
> defines it on the per-chip
> + * basis. In order to avoid a chain of
> negations, the GPIO
> + * polarity is considered being Active
> High. Even for the cases
> + * when _DSD() is involved (in the
> updated versions of ACPI)
> + * the GPIO CS polarity must be
defined
> Active High to avoid
> + * ambiguity. That's why we use
enable,
> that takes SPI_CS_HIGH
> + * into account.
> + */
> + if (has_acpi_companion(&spi->dev))
> +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> +
> !enable);
> + else
> + /* Polarity handled by GPIO
> library */
> +
> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> +
> activate);
> + }
> + /* Some SPI masters need both GPIO CS &
> slave_select */
> + if ((spi->controller->flags &
> SPI_MASTER_GPIO_SS) &&
> + spi->controller->set_cs)
> + spi->controller->set_cs(spi, !enable);
> + } else if (spi->controller->set_cs) {
> spi->controller->set_cs(spi, !enable);
> - } else if (spi->controller->set_cs) {
> - spi->controller->set_cs(spi, !enable);
> - }
> + }
>
> - if (spi_get_csgpiod(spi, 0) ||
!spi->controller->set_cs_timing) {
> - if (activate)
> - spi_delay_exec(&spi->cs_setup, NULL);
> - else
> - spi_delay_exec(&spi->cs_inactive, NULL);
> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >set_cs_timing) {
> + if (activate)
> + spi_delay_exec(&spi->cs_setup, NULL);
> + else
> + spi_delay_exec(&spi->cs_inactive,
> NULL);
> + }
> }
> }
>
> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
> device_node *nc,
> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
spi_device
> *spi,
> struct device_node *nc)
> {
> - u32 value;
> - int rc;
> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
> + int rc, idx;
>
> /* Mode (clock phase/polarity/etc.) */
> if (of_property_read_bool(nc, "spi-cpha"))
> @@ -2320,13 +2399,21 @@ static int of_spi_parse_dt(struct
> spi_controller *ctlr, struct spi_device *spi,
> }
>
> /* Device address */
> - rc = of_property_read_u32(nc, "reg", &value);
> - if (rc) {
> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> + SPI_CS_CNT_MAX);
> + if (rc < 0 || rc > ctlr->num_chipselect) {
> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> (%d)\n",
> nc, rc);
> return rc;
> + } else if ((of_property_read_bool(nc, "parallel-memories")) &&
> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> + dev_err(&ctlr->dev, "SPI controller doesn't support
multi
> CS\n");
> + return -EINVAL;
> }
> - spi_set_chipselect(spi, 0, value);
> + for (idx = 0; idx < rc; idx++)
> + spi_set_chipselect(spi, idx, cs[idx]);
> + /* By default set the spi->cs_index_mask as 1 */
> + spi->cs_index_mask = 0x01;
>
> /* Device speed */
> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> @@ -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device
> *spi, struct spi_message *message)
> * cs_change is set for each transfer.
> */
> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> SPI_CS_WORD) ||
> - spi_get_csgpiod(spi, 0))) {
> + spi_get_csgpiod(spi, 0) ||
> + spi_get_csgpiod(spi, 1))) {
> size_t maxsize;
> int ret;
>
> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> index 873ced6ae4ca..6453b246e0af 100644
> --- a/include/linux/spi/spi.h
> +++ b/include/linux/spi/spi.h
> @@ -19,6 +19,11 @@
> #include <linux/acpi.h>
> #include <linux/u64_stats_sync.h>
>
> +/* Max no. of CS supported per spi device */
> +#define SPI_CS_CNT_MAX 2
> +
> +/* chip select mask */
> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
> struct dma_chan;
> struct software_node;
> struct ptp_system_timestamp;
> @@ -166,6 +171,7 @@ extern void
> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> * deasserted. If @cs_change_delay is used from @spi_transfer,
> then the
> * two delays will be added up.
> * @pcpu_statistics: statistics for the spi_device
> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> chipselect array
> *
> * A @spi_device is used to interchange data between an SPI slave
> * (usually a discrete chip) and CPU memory.
> @@ -181,7 +187,7 @@ struct spi_device {
> struct spi_controller *controller;
> struct spi_controller *master; /* Compatibility layer
*/
> u32 max_speed_hz;
> - u8 chip_select;
> + u8 chip_select[SPI_CS_CNT_MAX];
> u8 bits_per_word;
> bool rt;
> #define SPI_NO_TX BIT(31) /* No transmit wire */
> @@ -202,7 +208,7 @@ struct spi_device {
> void *controller_data;
> char modalias[SPI_NAME_SIZE];
> const char *driver_override;
> - struct gpio_desc *cs_gpiod; /* Chip select gpio
desc
> */
> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
Chip
> select gpio desc */
> struct spi_delay word_delay; /* Inter-word delay */
> /* CS delays */
> struct spi_delay cs_setup;
> @@ -212,6 +218,13 @@ struct spi_device {
> /* The statistics */
> struct spi_statistics __percpu *pcpu_statistics;
>
> + /* Bit mask of the chipselect(s) that the driver need to use
from
> + * the chipselect array.When the controller is capable to
handle
> + * multiple chip selects & memories are connected in parallel
> + * then more than one bit need to be set in cs_index_mask.
> + */
> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> +
> /*
> * likely need more hooks for more protocol options affecting
> how
> * the controller talks to each chip, like:
> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
> struct spi_device *spi)
>
> static inline u8 spi_get_chipselect(const struct spi_device *spi,
u8 idx)
> {
> - return spi->chip_select;
> + return spi->chip_select[idx];
> }
>
> static inline void spi_set_chipselect(struct spi_device *spi, u8
idx, u8
> chipselect)
> {
> - spi->chip_select = chipselect;
> + spi->chip_select[idx] = chipselect;
> }
>
> static inline struct gpio_desc *spi_get_csgpiod(const struct
spi_device
> *spi, u8 idx)
> {
> - return spi->cs_gpiod;
> + return spi->cs_gpiod[idx];
> }
>
> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx,
struct
> gpio_desc *csgpiod)
> {
> - spi->cs_gpiod = csgpiod;
> + spi->cs_gpiod[idx] = csgpiod;
> }
>
> /**
> @@ -388,6 +401,8 @@ extern struct spi_device
> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> * @bus_lock_spinlock: spinlock for SPI bus locking
> * @bus_lock_mutex: mutex for exclusion of multiple callers
> * @bus_lock_flag: indicates that the SPI bus is locked for
exclusive use
> + * @multi_cs_cap: indicates that the SPI Controller can
assert/de-assert
> + * more than one chip select at once.
> * @setup: updates the device mode and clocking records used by a
> * device's SPI controller; protocol code may call this. This
> * must fail if an unrecognized or unsupported mode is requested.
> @@ -554,6 +569,11 @@ struct spi_controller {
> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> */
>
> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must select
> slave */
> + /*
> + * The spi-controller has multi chip select capability and can
> + * assert/de-assert more than one chip select at once.
> + */
> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
>
> /* Flag indicating if the allocation of this struct is devres-
> managed */
> bool devm_allocated;
> --
> 2.17.1
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Thursday, April 6, 2023 7:14 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories support
> in SPI core
>
> Hi,
>
> > -----Original Message-----
> > From: Amit Kumar Mahapatra <[email protected]>
> > Sent: Thursday, April 6, 2023 7:54 AM
> > To: [email protected]; [email protected]; [email protected];
> > [email protected]; [email protected]; [email protected];
> > [email protected]
> > Cc: [email protected]; [email protected]; linux-
> > [email protected]; [email protected]; linux-
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; [email protected];
> > [email protected]; Amit Kumar Mahapatra <amit.kumar-
> > [email protected]>
> > Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
> support
> > in SPI core
> >
> > For supporting multiple CS the SPI device need to be aware of all
> the CS
> > values. So, the "chip_select" member in the spi_device structure is
> now
> > an
> > array that holds all the CS values.
> >
> > spi_device structure now has a "cs_index_mask" member. This acts as
> an
> > index to the chip_select array. If nth bit of spi->cs_index_mask is
> set
> > then the driver would assert spi->chip_select[n].
> >
> > In parallel mode all the chip selects are asserted/de-asserted
> > simultaneously and each byte of data is stored in both devices, the
> even
> > bits in one, the odd bits in the other. The split is automatically
> handled
> > by the GQSPI controller. The GQSPI controller supports a maximum of
> > two flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag
> > bit is added in the spi controntroller flags, through ctlr->flags the
> > spi
> core
> > will make sure that the controller is capable of handling multiple
> chip
> > selects at once.
> >
> > For supporting multiple CS via GPIO the cs_gpiod member of the
> > spi_device structure is now an array that holds the gpio descriptor
> > for each chipselect.
> >
> > Multi CS support using GPIO is not tested due to unavailability of
> > necessary hardware setup.
> >
> > Multi CS configuration with one native CS and one GPIO CS is not
> > supported as this configuration could not be tested due to
> > unavailability of necessary hardware setup.
>
> I've tested this chain on a released laptop (HP EliteBook 840 G9) which uses
> SPI to interface to 2 amps, one amp uses a native CS and the other uses a
> GPIO CS, and I noticed that when using this chain, the second amp no longer
> works.
Thank you for testing this patch series on GPIO CS setup. As I don't have a
GPIO CS setup, is it possible for you debug the failure and share more
details/logs where the problem is?
Regards,
Amit
>
> Thanks,
> Stefan Binding
>
> >
> > Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> [email protected]>
> > ---
> > drivers/spi/spi.c | 226
> ++++++++++++++++++++++++++++------------
> > include/linux/spi/spi.h | 32 ++++--
> > 2 files changed, 183 insertions(+), 75 deletions(-)
> >
> > diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> > 9036d7a50674..04d7322170c4 100644
> > --- a/drivers/spi/spi.c
> > +++ b/drivers/spi/spi.c
> > @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
> > void *data) {
> > struct spi_device *spi = to_spi_device(dev);
> > struct spi_device *new_spi = data;
> > + int idx, nw_idx;
> >
> > - if (spi->controller == new_spi->controller &&
> > - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
> 0))
> > - return -EBUSY;
> > + if (spi->controller == new_spi->controller) {
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> > nw_idx++) {
> > + if ((idx != 0 &&
> !spi_get_chipselect(spi,
> > idx)) ||
> > + (nw_idx != 0 &&
> > !spi_get_chipselect(spi, nw_idx))) {
> > + continue;
> > + } else if (spi_get_chipselect(spi,
> idx) ==
> > + spi_get_chipselect(new_spi,
> nw_idx))
> > {
> > + dev_err(dev,
> > + "chipselect %d already
> > in use\n",
> > +
> > spi_get_chipselect(new_spi, nw_idx));
> > + return -EBUSY;
> > + }
> > + }
> > + }
> > + }
> > return 0;
> > }
> >
> > @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
> > *spi)
> > {
> > struct spi_controller *ctlr = spi->controller;
> > struct device *dev = ctlr->dev.parent;
> > - int status;
> > + int status, idx;
> >
> > /*
> > * We need to make sure there's no other device with this @@ -638,8
> > +652,6 @@ static int __spi_add_device(struct spi_device
> > *spi)
> > */
> > status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> spi_dev_check);
> > if (status) {
> > - dev_err(dev, "chipselect %d already in use\n",
> > - spi_get_chipselect(spi, 0));
> > return status;
> > }
> >
> > @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
> > *spi)
> > return -ENODEV;
> > }
> >
> > - if (ctlr->cs_gpiods)
> > - spi_set_csgpiod(spi, 0, ctlr-
> > >cs_gpiods[spi_get_chipselect(spi, 0)]);
> > + if (ctlr->cs_gpiods) {
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > + spi_set_csgpiod(spi, idx, ctlr-
> > >cs_gpiods[spi_get_chipselect(spi, idx)]);
> > + }
> >
> > /*
> > * Drivers may modify this initial i/o setup, but will @@ -690,13
> > +704,15 @@ int spi_add_device(struct spi_device *spi) {
> > struct spi_controller *ctlr = spi->controller;
> > struct device *dev = ctlr->dev.parent;
> > - int status;
> > + int status, idx;
> >
> > - /* Chipselects are numbered 0..max; validate. */
> > - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> > - dev_err(dev, "cs%d >= max %d\n",
> > spi_get_chipselect(spi, 0),
> > - ctlr->num_chipselect);
> > - return -EINVAL;
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + /* Chipselects are numbered 0..max; validate. */
> > + if (spi_get_chipselect(spi, idx) >=
> ctlr->num_chipselect) {
> > + dev_err(dev, "cs%d >= max %d\n",
> > spi_get_chipselect(spi, idx),
> > + ctlr->num_chipselect);
> > + return -EINVAL;
> > + }
> > }
> >
> > /* Set the bus ID string */
> > @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
> > spi_device *spi) {
> > struct spi_controller *ctlr = spi->controller;
> > struct device *dev = ctlr->dev.parent;
> > + int idx;
> >
> > - /* Chipselects are numbered 0..max; validate. */
> > - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> > - dev_err(dev, "cs%d >= max %d\n",
> > spi_get_chipselect(spi, 0),
> > - ctlr->num_chipselect);
> > - return -EINVAL;
> > + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > + /* Chipselects are numbered 0..max; validate. */
> > + if (spi_get_chipselect(spi, idx) >=
> ctlr->num_chipselect) {
> > + dev_err(dev, "cs%d >= max %d\n",
> > spi_get_chipselect(spi, idx),
> > + ctlr->num_chipselect);
> > + return -EINVAL;
> > + }
> > }
> >
> > /* Set the bus ID string */
> > @@ -966,58 +985,118 @@ static void spi_res_release(struct
> > spi_controller *ctlr, struct spi_message *mes static void
> > spi_set_cs(struct spi_device *spi, bool enable, bool
> force)
> > {
> > bool activate = enable;
> > + u32 cs_num = __ffs(spi->cs_index_mask);
> > + int idx;
> >
> > /*
> > - * Avoid calling into the driver (or doing delays) if the chip
> select
> > - * isn't actually changing from the last time this was called.
> > + * In parallel mode all the chip selects are
> asserted/de-asserted
> > + * at once
> > */
> > - if (!force && ((enable && spi->controller->last_cs ==
> > spi_get_chipselect(spi, 0)) ||
> > - (!enable && spi->controller->last_cs !=
> > spi_get_chipselect(spi, 0))) &&
> > - (spi->controller->last_cs_mode_high == (spi->mode &
> > SPI_CS_HIGH)))
> > - return;
> > -
> > - trace_spi_set_cs(spi, activate);
> > -
> > - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
> : -1;
> > - spi->controller->last_cs_mode_high = spi->mode &
> > SPI_CS_HIGH;
> > -
> > - if ((spi_get_csgpiod(spi, 0) ||
> !spi->controller->set_cs_timing)
> > && !activate)
> > - spi_delay_exec(&spi->cs_hold, NULL);
> > -
> > - if (spi->mode & SPI_CS_HIGH)
> > - enable = !enable;
> > + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
> > SPI_PARALLEL_CS_MASK) {
> > + spi->controller->last_cs_mode_high = spi->mode &
> > SPI_CS_HIGH;
> > +
> > + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> > >set_cs_timing) && !activate)
> > + spi_delay_exec(&spi->cs_hold, NULL);
> > +
> > + if (spi->mode & SPI_CS_HIGH)
> > + enable = !enable;
> > +
> > + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
> 1)) {
> > + if (!(spi->mode & SPI_NO_CS)) {
> > + /*
> > + * Historically ACPI has no means of
> the
> > GPIO polarity and
> > + * thus the SPISerialBus() resource
> > defines it on the per-chip
> > + * basis. In order to avoid a chain of
> > negations, the GPIO
> > + * polarity is considered being Active
> > High. Even for the cases
> > + * when _DSD() is involved (in the
> > updated versions of ACPI)
> > + * the GPIO CS polarity must be
> defined
> > Active High to avoid
> > + * ambiguity. That's why we use
> enable,
> > that takes SPI_CS_HIGH
> > + * into account.
> > + */
> > + if (has_acpi_companion(&spi->dev)) {
> > + for (idx = 0; idx <
> > SPI_CS_CNT_MAX; idx++)
> > +
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > +
> > !enable);
> > + } else {
> > + for (idx = 0; idx <
> > SPI_CS_CNT_MAX; idx++)
> > + /* Polarity handled by
> > GPIO library */
> > +
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> > +
> > activate);
> > + }
> > + }
> > + /* Some SPI masters need both GPIO CS &
> > slave_select */
> > + if ((spi->controller->flags &
> > SPI_MASTER_GPIO_SS) &&
> > + spi->controller->set_cs)
> > + spi->controller->set_cs(spi, !enable);
> > + } else if (spi->controller->set_cs) {
> > + spi->controller->set_cs(spi, !enable);
> > + }
> >
> > - if (spi_get_csgpiod(spi, 0)) {
> > - if (!(spi->mode & SPI_NO_CS)) {
> > - /*
> > - * Historically ACPI has no means of the GPIO
> > polarity and
> > - * thus the SPISerialBus() resource defines it
> on
> > the per-chip
> > - * basis. In order to avoid a chain of
> negations,
> > the GPIO
> > - * polarity is considered being Active High.
> Even
> > for the cases
> > - * when _DSD() is involved (in the updated
> > versions of ACPI)
> > - * the GPIO CS polarity must be defined Active
> > High to avoid
> > - * ambiguity. That's why we use enable, that
> > takes SPI_CS_HIGH
> > - * into account.
> > - */
> > - if (has_acpi_companion(&spi->dev))
> > -
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> > + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
> ||
> > + !spi->controller->set_cs_timing) {
> > + if (activate)
> > + spi_delay_exec(&spi->cs_setup, NULL);
> > else
> > - /* Polarity handled by GPIO library */
> > -
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> > + spi_delay_exec(&spi->cs_inactive,
> > NULL);
> > }
> > - /* Some SPI masters need both GPIO CS & slave_select
> > */
> > - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
> > - spi->controller->set_cs)
> > + } else {
> > + /*
> > + * Avoid calling into the driver (or doing delays) if
> the
> > chip select
> > + * isn't actually changing from the last time this was
> > called.
> > + */
> > + if (!force && ((enable && spi->controller->last_cs ==
> > + spi_get_chipselect(spi, cs_num)) ||
> > + (!enable && spi->controller->last_cs
> !=
> > + spi_get_chipselect(spi, cs_num))) &&
> > + (spi->controller->last_cs_mode_high ==
> > + (spi->mode & SPI_CS_HIGH)))
> > + return;
> > +
> > + trace_spi_set_cs(spi, activate);
> > +
> > + spi->controller->last_cs = enable ?
> > spi_get_chipselect(spi, cs_num) : -1;
> > + spi->controller->last_cs_mode_high = spi->mode &
> > SPI_CS_HIGH;
> > +
> > + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
> > >set_cs_timing) && !activate)
> > + spi_delay_exec(&spi->cs_hold, NULL);
> > +
> > + if (spi->mode & SPI_CS_HIGH)
> > + enable = !enable;
> > +
> > + if (spi_get_csgpiod(spi, cs_num)) {
> > + if (!(spi->mode & SPI_NO_CS)) {
> > + /*
> > + * Historically ACPI has no means of
> the
> > GPIO polarity and
> > + * thus the SPISerialBus() resource
> > defines it on the per-chip
> > + * basis. In order to avoid a chain of
> > negations, the GPIO
> > + * polarity is considered being Active
> > High. Even for the cases
> > + * when _DSD() is involved (in the
> > updated versions of ACPI)
> > + * the GPIO CS polarity must be
> defined
> > Active High to avoid
> > + * ambiguity. That's why we use
> enable,
> > that takes SPI_CS_HIGH
> > + * into account.
> > + */
> > + if (has_acpi_companion(&spi->dev))
> > +
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> > +
> > !enable);
> > + else
> > + /* Polarity handled by GPIO
> > library */
> > +
> > gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> > +
> > activate);
> > + }
> > + /* Some SPI masters need both GPIO CS &
> > slave_select */
> > + if ((spi->controller->flags &
> > SPI_MASTER_GPIO_SS) &&
> > + spi->controller->set_cs)
> > + spi->controller->set_cs(spi, !enable);
> > + } else if (spi->controller->set_cs) {
> > spi->controller->set_cs(spi, !enable);
> > - } else if (spi->controller->set_cs) {
> > - spi->controller->set_cs(spi, !enable);
> > - }
> > + }
> >
> > - if (spi_get_csgpiod(spi, 0) ||
> !spi->controller->set_cs_timing) {
> > - if (activate)
> > - spi_delay_exec(&spi->cs_setup, NULL);
> > - else
> > - spi_delay_exec(&spi->cs_inactive, NULL);
> > + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
> > >set_cs_timing) {
> > + if (activate)
> > + spi_delay_exec(&spi->cs_setup, NULL);
> > + else
> > + spi_delay_exec(&spi->cs_inactive,
> > NULL);
> > + }
> > }
> > }
> >
> > @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
> > device_node *nc, static int of_spi_parse_dt(struct spi_controller
> > *ctlr, struct
> spi_device
> > *spi,
> > struct device_node *nc)
> > {
> > - u32 value;
> > - int rc;
> > + u32 value, cs[SPI_CS_CNT_MAX] = {0};
> > + int rc, idx;
> >
> > /* Mode (clock phase/polarity/etc.) */
> > if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13 +2399,21
> @@
> > static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> > spi_device *spi,
> > }
> >
> > /* Device address */
> > - rc = of_property_read_u32(nc, "reg", &value);
> > - if (rc) {
> > + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> > + SPI_CS_CNT_MAX);
> > + if (rc < 0 || rc > ctlr->num_chipselect) {
> > dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> (%d)\n",
> > nc, rc);
> > return rc;
> > + } else if ((of_property_read_bool(nc, "parallel-memories")) &&
> > + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> > + dev_err(&ctlr->dev, "SPI controller doesn't support
> multi
> > CS\n");
> > + return -EINVAL;
> > }
> > - spi_set_chipselect(spi, 0, value);
> > + for (idx = 0; idx < rc; idx++)
> > + spi_set_chipselect(spi, idx, cs[idx]);
> > + /* By default set the spi->cs_index_mask as 1 */
> > + spi->cs_index_mask = 0x01;
> >
> > /* Device speed */
> > if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
> > -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device *spi,
> > struct spi_message *message)
> > * cs_change is set for each transfer.
> > */
> > if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> > SPI_CS_WORD) ||
> > - spi_get_csgpiod(spi, 0))) {
> > + spi_get_csgpiod(spi, 0) ||
> > + spi_get_csgpiod(spi, 1))) {
> > size_t maxsize;
> > int ret;
> >
> > diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> > 873ced6ae4ca..6453b246e0af 100644
> > --- a/include/linux/spi/spi.h
> > +++ b/include/linux/spi/spi.h
> > @@ -19,6 +19,11 @@
> > #include <linux/acpi.h>
> > #include <linux/u64_stats_sync.h>
> >
> > +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 2
> > +
> > +/* chip select mask */
> > +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
> > struct dma_chan;
> > struct software_node;
> > struct ptp_system_timestamp;
> > @@ -166,6 +171,7 @@ extern void
> > spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> > * deasserted. If @cs_change_delay is used from @spi_transfer,
> > then the
> > * two delays will be added up.
> > * @pcpu_statistics: statistics for the spi_device
> > + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> > chipselect array
> > *
> > * A @spi_device is used to interchange data between an SPI slave
> > * (usually a discrete chip) and CPU memory.
> > @@ -181,7 +187,7 @@ struct spi_device {
> > struct spi_controller *controller;
> > struct spi_controller *master; /* Compatibility layer
> */
> > u32 max_speed_hz;
> > - u8 chip_select;
> > + u8 chip_select[SPI_CS_CNT_MAX];
> > u8 bits_per_word;
> > bool rt;
> > #define SPI_NO_TX BIT(31) /* No transmit wire */
> > @@ -202,7 +208,7 @@ struct spi_device {
> > void *controller_data;
> > char modalias[SPI_NAME_SIZE];
> > const char *driver_override;
> > - struct gpio_desc *cs_gpiod; /* Chip select gpio
> desc
> > */
> > + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> Chip
> > select gpio desc */
> > struct spi_delay word_delay; /* Inter-word delay */
> > /* CS delays */
> > struct spi_delay cs_setup;
> > @@ -212,6 +218,13 @@ struct spi_device {
> > /* The statistics */
> > struct spi_statistics __percpu *pcpu_statistics;
> >
> > + /* Bit mask of the chipselect(s) that the driver need to use
> from
> > + * the chipselect array.When the controller is capable to
> handle
> > + * multiple chip selects & memories are connected in parallel
> > + * then more than one bit need to be set in cs_index_mask.
> > + */
> > + u32 cs_index_mask : SPI_CS_CNT_MAX;
> > +
> > /*
> > * likely need more hooks for more protocol options affecting how
> > * the controller talks to each chip, like:
> > @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const struct
> > spi_device *spi)
> >
> > static inline u8 spi_get_chipselect(const struct spi_device *spi,
> u8 idx)
> > {
> > - return spi->chip_select;
> > + return spi->chip_select[idx];
> > }
> >
> > static inline void spi_set_chipselect(struct spi_device *spi, u8
> idx, u8
> > chipselect)
> > {
> > - spi->chip_select = chipselect;
> > + spi->chip_select[idx] = chipselect;
> > }
> >
> > static inline struct gpio_desc *spi_get_csgpiod(const struct
> spi_device
> > *spi, u8 idx)
> > {
> > - return spi->cs_gpiod;
> > + return spi->cs_gpiod[idx];
> > }
> >
> > static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx,
> struct
> > gpio_desc *csgpiod)
> > {
> > - spi->cs_gpiod = csgpiod;
> > + spi->cs_gpiod[idx] = csgpiod;
> > }
> >
> > /**
> > @@ -388,6 +401,8 @@ extern struct spi_device
> > *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> > * @bus_lock_spinlock: spinlock for SPI bus locking
> > * @bus_lock_mutex: mutex for exclusion of multiple callers
> > * @bus_lock_flag: indicates that the SPI bus is locked for
> exclusive use
> > + * @multi_cs_cap: indicates that the SPI Controller can
> assert/de-assert
> > + * more than one chip select at once.
> > * @setup: updates the device mode and clocking records used by a
> > * device's SPI controller; protocol code may call this. This
> > * must fail if an unrecognized or unsupported mode is requested.
> > @@ -554,6 +569,11 @@ struct spi_controller {
> > #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> > */
> >
> > #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
> select
> > slave */
> > + /*
> > + * The spi-controller has multi chip select capability and can
> > + * assert/de-assert more than one chip select at once.
> > + */
> > +#define SPI_CONTROLLER_MULTI_CS BIT(6)
> >
> > /* Flag indicating if the allocation of this struct is devres-
> > managed */
> > bool devm_allocated;
> > --
> > 2.17.1
>
Hi,
On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Thursday, April 6, 2023 7:14 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>;
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories support
>> in SPI core
>>
>> Hi,
>>
>>> -----Original Message-----
>>> From: Amit Kumar Mahapatra <[email protected]>
>>> Sent: Thursday, April 6, 2023 7:54 AM
>>> To: [email protected]; [email protected]; [email protected];
>>> [email protected]; [email protected]; [email protected];
>>> [email protected]
>>> Cc: [email protected]; [email protected]; linux-
>>> [email protected]; [email protected]; linux-
>>> [email protected]; [email protected];
>>> [email protected]; [email protected];
>>> [email protected]; [email protected];
>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
>>> [email protected]>
>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
>> support
>>> in SPI core
>>>
>>> For supporting multiple CS the SPI device need to be aware of all
>> the CS
>>> values. So, the "chip_select" member in the spi_device structure is
>> now
>>> an
>>> array that holds all the CS values.
>>>
>>> spi_device structure now has a "cs_index_mask" member. This acts as
>> an
>>> index to the chip_select array. If nth bit of spi->cs_index_mask is
>> set
>>> then the driver would assert spi->chip_select[n].
>>>
>>> In parallel mode all the chip selects are asserted/de-asserted
>>> simultaneously and each byte of data is stored in both devices, the
>> even
>>> bits in one, the odd bits in the other. The split is automatically
>> handled
>>> by the GQSPI controller. The GQSPI controller supports a maximum of
>>> two flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS flag
>>> bit is added in the spi controntroller flags, through ctlr->flags the
>>> spi
>> core
>>> will make sure that the controller is capable of handling multiple
>> chip
>>> selects at once.
>>>
>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>> spi_device structure is now an array that holds the gpio descriptor
>>> for each chipselect.
>>>
>>> Multi CS support using GPIO is not tested due to unavailability of
>>> necessary hardware setup.
>>>
>>> Multi CS configuration with one native CS and one GPIO CS is not
>>> supported as this configuration could not be tested due to
>>> unavailability of necessary hardware setup.
>> I've tested this chain on a released laptop (HP EliteBook 840 G9) which uses
>> SPI to interface to 2 amps, one amp uses a native CS and the other uses a
>> GPIO CS, and I noticed that when using this chain, the second amp no longer
>> works.
> Thank you for testing this patch series on GPIO CS setup. As I don't have a
> GPIO CS setup, is it possible for you debug the failure and share more
> details/logs where the problem is?
>
> Regards,
> Amit
We are willing and able to debug this failure and share the failure logs.
The first issue that I see is a kernel crash when trying to set the GPIO CS:
[ 2.951658] general protection fault, probably for non-canonical
address 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI
[ 2.951771] CPU: 9 PID: 379 Comm: systemd-udevd Tainted: G
A 6.3.0-rc3+ #30
[ 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
[ 2.951882] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
[ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77
2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c
[ 2.952043] RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287
[ 2.952080] RAX: 0000000000000001 RBX: ffffa0a489534c00 RCX:
0000000000000000
[ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
dead000000000122
[ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
ffffc008c0deb868
[ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
dead000000000122
[ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
0000000000000000
[ 2.952299] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
knlGS:0000000000000000
[ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
0000000000770ee0
[ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
0000000000000000
[ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
0000000000000400
[ 2.952533] PKRU: 55555554
[ 2.952561] Call Trace:
[ 2.952579] <TASK>
[ 2.952598] spi_set_cs+0x257/0x4a0
[ 2.952630] spi_setup+0x1a2/0x500
[ 2.952667] __spi_add_device+0x88/0x160
[ 2.952710] spi_add_device+0x60/0x90
[ 2.952738] smi_spi_probe+0x178/0x370 [serial_multi_instantiate]
[ 2.952792] smi_probe+0xcf/0x110 [serial_multi_instantiate]
[ 2.952854] platform_probe+0x42/0xb0
[ 2.952885] really_probe+0x1b2/0x420
[ 2.952914] __driver_probe_device+0x7e/0x180
[ 2.952947] driver_probe_device+0x23/0xa0
[ 2.952993] __driver_attach+0xe4/0x1e0
[ 2.953021] ? __pfx___driver_attach+0x10/0x10
[ 2.953061] bus_for_each_dev+0x7a/0xd0
[ 2.953088] driver_attach+0x1e/0x30
[ 2.953123] bus_add_driver+0x11c/0x220
[ 2.953150] driver_register+0x64/0x130
[ 2.953174] ? __pfx_init_module+0x10/0x10 [serial_multi_instantiate]
[ 2.953221] __platform_driver_register+0x1e/0x30
[ 2.953251] smi_driver_init+0x1c/0xff0 [serial_multi_instantiate]
[ 2.953310] do_one_initcall+0x46/0x220
[ 2.953339] ? kmalloc_trace+0x2a/0xa0
[ 2.953375] do_init_module+0x52/0x220
[ 2.953411] load_module+0x223c/0x2460
[ 2.953450] __do_sys_finit_module+0xc8/0x140
[ 2.953479] ? __do_sys_finit_module+0xc8/0x140
[ 2.953510] __x64_sys_finit_module+0x18/0x20
[ 2.953538] do_syscall_64+0x38/0x90
[ 2.953574] entry_SYSCALL_64_after_hwframe+0x72/0xdc
[ 2.953606] RIP: 0033:0x7f7fa5d7476d
[ 2.953639] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
[ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246 ORIG_RAX:
0000000000000139
[ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
00007f7fa5d7476d
[ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
0000000000000006
[ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
0000000000000000
[ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
00007f7fa5c54ded
[ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
000055d648654ab0
[ 2.967668] resource: resource sanity check: requesting [mem
0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp 00:04
[mem 0xfedc0000-0xfedc7fff]
[ 2.968998] </TASK>
[ 2.971615] caller igen6_probe+0x178/0x8e0 [igen6_edac] mapping
multiple BARs
[ 2.975014] Modules linked in: igen6_edac(+) fjes(-)
serial_multi_instantiate(+) int3403_thermal sch_fq_codel
int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel acpi_tad
sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp parport drm
ramoops reed_solomon efi_pstore ip_tables x_tables autofs4
spi_pxa2xx_platform dw_dmac dw_dmac_core nvme intel_lpss_pci intel_lpss
crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64 nvme_core i2c_smbus
virt_dma xhci_pci_renesas video wmi pinctrl_tigerlake
[ 2.987901] ---[ end trace 0000000000000000 ]---
[ 3.157030] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
[ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77
2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c
[ 3.161461] RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287
[ 3.164005] RAX: 0000000000000001 RBX: ffffa0a489534c00 RCX:
0000000000000000
[ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
dead000000000122
[ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
ffffc008c0deb868
[ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
dead000000000122
[ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
0000000000000000
[ 3.175335] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
knlGS:0000000000000000
[ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
0000000000770ee0
[ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
0000000000000000
[ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
0000000000000400
[ 3.188647] PKRU: 55555554
Thanks,
Stefan
>
>> Thanks,
>> Stefan Binding
>>
>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>> [email protected]>
>>> ---
>>> drivers/spi/spi.c | 226
>> ++++++++++++++++++++++++++++------------
>>> include/linux/spi/spi.h | 32 ++++--
>>> 2 files changed, 183 insertions(+), 75 deletions(-)
>>>
>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>> 9036d7a50674..04d7322170c4 100644
>>> --- a/drivers/spi/spi.c
>>> +++ b/drivers/spi/spi.c
>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
>>> void *data) {
>>> struct spi_device *spi = to_spi_device(dev);
>>> struct spi_device *new_spi = data;
>>> + int idx, nw_idx;
>>>
>>> - if (spi->controller == new_spi->controller &&
>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
>> 0))
>>> - return -EBUSY;
>>> + if (spi->controller == new_spi->controller) {
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>> nw_idx++) {
>>> + if ((idx != 0 &&
>> !spi_get_chipselect(spi,
>>> idx)) ||
>>> + (nw_idx != 0 &&
>>> !spi_get_chipselect(spi, nw_idx))) {
>>> + continue;
>>> + } else if (spi_get_chipselect(spi,
>> idx) ==
>>> + spi_get_chipselect(new_spi,
>> nw_idx))
>>> {
>>> + dev_err(dev,
>>> + "chipselect %d already
>>> in use\n",
>>> +
>>> spi_get_chipselect(new_spi, nw_idx));
>>> + return -EBUSY;
>>> + }
>>> + }
>>> + }
>>> + }
>>> return 0;
>>> }
>>>
>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
>>> *spi)
>>> {
>>> struct spi_controller *ctlr = spi->controller;
>>> struct device *dev = ctlr->dev.parent;
>>> - int status;
>>> + int status, idx;
>>>
>>> /*
>>> * We need to make sure there's no other device with this @@ -638,8
>>> +652,6 @@ static int __spi_add_device(struct spi_device
>>> *spi)
>>> */
>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
>> spi_dev_check);
>>> if (status) {
>>> - dev_err(dev, "chipselect %d already in use\n",
>>> - spi_get_chipselect(spi, 0));
>>> return status;
>>> }
>>>
>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
>>> *spi)
>>> return -ENODEV;
>>> }
>>>
>>> - if (ctlr->cs_gpiods)
>>> - spi_set_csgpiod(spi, 0, ctlr-
>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
>>> + if (ctlr->cs_gpiods) {
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> + spi_set_csgpiod(spi, idx, ctlr-
>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>> + }
>>>
>>> /*
>>> * Drivers may modify this initial i/o setup, but will @@ -690,13
>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
>>> struct spi_controller *ctlr = spi->controller;
>>> struct device *dev = ctlr->dev.parent;
>>> - int status;
>>> + int status, idx;
>>>
>>> - /* Chipselects are numbered 0..max; validate. */
>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>> - dev_err(dev, "cs%d >= max %d\n",
>>> spi_get_chipselect(spi, 0),
>>> - ctlr->num_chipselect);
>>> - return -EINVAL;
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + /* Chipselects are numbered 0..max; validate. */
>>> + if (spi_get_chipselect(spi, idx) >=
>> ctlr->num_chipselect) {
>>> + dev_err(dev, "cs%d >= max %d\n",
>>> spi_get_chipselect(spi, idx),
>>> + ctlr->num_chipselect);
>>> + return -EINVAL;
>>> + }
>>> }
>>>
>>> /* Set the bus ID string */
>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
>>> spi_device *spi) {
>>> struct spi_controller *ctlr = spi->controller;
>>> struct device *dev = ctlr->dev.parent;
>>> + int idx;
>>>
>>> - /* Chipselects are numbered 0..max; validate. */
>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>> - dev_err(dev, "cs%d >= max %d\n",
>>> spi_get_chipselect(spi, 0),
>>> - ctlr->num_chipselect);
>>> - return -EINVAL;
>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> + /* Chipselects are numbered 0..max; validate. */
>>> + if (spi_get_chipselect(spi, idx) >=
>> ctlr->num_chipselect) {
>>> + dev_err(dev, "cs%d >= max %d\n",
>>> spi_get_chipselect(spi, idx),
>>> + ctlr->num_chipselect);
>>> + return -EINVAL;
>>> + }
>>> }
>>>
>>> /* Set the bus ID string */
>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
>>> spi_controller *ctlr, struct spi_message *mes static void
>>> spi_set_cs(struct spi_device *spi, bool enable, bool
>> force)
>>> {
>>> bool activate = enable;
>>> + u32 cs_num = __ffs(spi->cs_index_mask);
>>> + int idx;
>>>
>>> /*
>>> - * Avoid calling into the driver (or doing delays) if the chip
>> select
>>> - * isn't actually changing from the last time this was called.
>>> + * In parallel mode all the chip selects are
>> asserted/de-asserted
>>> + * at once
>>> */
>>> - if (!force && ((enable && spi->controller->last_cs ==
>>> spi_get_chipselect(spi, 0)) ||
>>> - (!enable && spi->controller->last_cs !=
>>> spi_get_chipselect(spi, 0))) &&
>>> - (spi->controller->last_cs_mode_high == (spi->mode &
>>> SPI_CS_HIGH)))
>>> - return;
>>> -
>>> - trace_spi_set_cs(spi, activate);
>>> -
>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
>> : -1;
>>> - spi->controller->last_cs_mode_high = spi->mode &
>>> SPI_CS_HIGH;
>>> -
>>> - if ((spi_get_csgpiod(spi, 0) ||
>> !spi->controller->set_cs_timing)
>>> && !activate)
>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>> -
>>> - if (spi->mode & SPI_CS_HIGH)
>>> - enable = !enable;
>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
>>> SPI_PARALLEL_CS_MASK) {
>>> + spi->controller->last_cs_mode_high = spi->mode &
>>> SPI_CS_HIGH;
>>> +
>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
>>>> set_cs_timing) && !activate)
>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>> +
>>> + if (spi->mode & SPI_CS_HIGH)
>>> + enable = !enable;
>>> +
>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
>> 1)) {
>>> + if (!(spi->mode & SPI_NO_CS)) {
>>> + /*
>>> + * Historically ACPI has no means of
>> the
>>> GPIO polarity and
>>> + * thus the SPISerialBus() resource
>>> defines it on the per-chip
>>> + * basis. In order to avoid a chain of
>>> negations, the GPIO
>>> + * polarity is considered being Active
>>> High. Even for the cases
>>> + * when _DSD() is involved (in the
>>> updated versions of ACPI)
>>> + * the GPIO CS polarity must be
>> defined
>>> Active High to avoid
>>> + * ambiguity. That's why we use
>> enable,
>>> that takes SPI_CS_HIGH
>>> + * into account.
>>> + */
>>> + if (has_acpi_companion(&spi->dev)) {
>>> + for (idx = 0; idx <
>>> SPI_CS_CNT_MAX; idx++)
>>> +
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>> +
>>> !enable);
>>> + } else {
>>> + for (idx = 0; idx <
>>> SPI_CS_CNT_MAX; idx++)
>>> + /* Polarity handled by
>>> GPIO library */
>>> +
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>> +
>>> activate);
>>> + }
>>> + }
>>> + /* Some SPI masters need both GPIO CS &
>>> slave_select */
>>> + if ((spi->controller->flags &
>>> SPI_MASTER_GPIO_SS) &&
>>> + spi->controller->set_cs)
>>> + spi->controller->set_cs(spi, !enable);
>>> + } else if (spi->controller->set_cs) {
>>> + spi->controller->set_cs(spi, !enable);
>>> + }
>>>
>>> - if (spi_get_csgpiod(spi, 0)) {
>>> - if (!(spi->mode & SPI_NO_CS)) {
>>> - /*
>>> - * Historically ACPI has no means of the GPIO
>>> polarity and
>>> - * thus the SPISerialBus() resource defines it
>> on
>>> the per-chip
>>> - * basis. In order to avoid a chain of
>> negations,
>>> the GPIO
>>> - * polarity is considered being Active High.
>> Even
>>> for the cases
>>> - * when _DSD() is involved (in the updated
>>> versions of ACPI)
>>> - * the GPIO CS polarity must be defined Active
>>> High to avoid
>>> - * ambiguity. That's why we use enable, that
>>> takes SPI_CS_HIGH
>>> - * into account.
>>> - */
>>> - if (has_acpi_companion(&spi->dev))
>>> -
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
>> ||
>>> + !spi->controller->set_cs_timing) {
>>> + if (activate)
>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>> else
>>> - /* Polarity handled by GPIO library */
>>> -
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>> + spi_delay_exec(&spi->cs_inactive,
>>> NULL);
>>> }
>>> - /* Some SPI masters need both GPIO CS & slave_select
>>> */
>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
>>> - spi->controller->set_cs)
>>> + } else {
>>> + /*
>>> + * Avoid calling into the driver (or doing delays) if
>> the
>>> chip select
>>> + * isn't actually changing from the last time this was
>>> called.
>>> + */
>>> + if (!force && ((enable && spi->controller->last_cs ==
>>> + spi_get_chipselect(spi, cs_num)) ||
>>> + (!enable && spi->controller->last_cs
>> !=
>>> + spi_get_chipselect(spi, cs_num))) &&
>>> + (spi->controller->last_cs_mode_high ==
>>> + (spi->mode & SPI_CS_HIGH)))
>>> + return;
>>> +
>>> + trace_spi_set_cs(spi, activate);
>>> +
>>> + spi->controller->last_cs = enable ?
>>> spi_get_chipselect(spi, cs_num) : -1;
>>> + spi->controller->last_cs_mode_high = spi->mode &
>>> SPI_CS_HIGH;
>>> +
>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>> set_cs_timing) && !activate)
>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>> +
>>> + if (spi->mode & SPI_CS_HIGH)
>>> + enable = !enable;
>>> +
>>> + if (spi_get_csgpiod(spi, cs_num)) {
>>> + if (!(spi->mode & SPI_NO_CS)) {
>>> + /*
>>> + * Historically ACPI has no means of
>> the
>>> GPIO polarity and
>>> + * thus the SPISerialBus() resource
>>> defines it on the per-chip
>>> + * basis. In order to avoid a chain of
>>> negations, the GPIO
>>> + * polarity is considered being Active
>>> High. Even for the cases
>>> + * when _DSD() is involved (in the
>>> updated versions of ACPI)
>>> + * the GPIO CS polarity must be
>> defined
>>> Active High to avoid
>>> + * ambiguity. That's why we use
>> enable,
>>> that takes SPI_CS_HIGH
>>> + * into account.
>>> + */
>>> + if (has_acpi_companion(&spi->dev))
>>> +
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>> +
>>> !enable);
>>> + else
>>> + /* Polarity handled by GPIO
>>> library */
>>> +
>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>> +
>>> activate);
>>> + }
>>> + /* Some SPI masters need both GPIO CS &
>>> slave_select */
>>> + if ((spi->controller->flags &
>>> SPI_MASTER_GPIO_SS) &&
>>> + spi->controller->set_cs)
>>> + spi->controller->set_cs(spi, !enable);
>>> + } else if (spi->controller->set_cs) {
>>> spi->controller->set_cs(spi, !enable);
>>> - } else if (spi->controller->set_cs) {
>>> - spi->controller->set_cs(spi, !enable);
>>> - }
>>> + }
>>>
>>> - if (spi_get_csgpiod(spi, 0) ||
>> !spi->controller->set_cs_timing) {
>>> - if (activate)
>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>> - else
>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>> set_cs_timing) {
>>> + if (activate)
>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>> + else
>>> + spi_delay_exec(&spi->cs_inactive,
>>> NULL);
>>> + }
>>> }
>>> }
>>>
>>> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
>>> *ctlr, struct
>> spi_device
>>> *spi,
>>> struct device_node *nc)
>>> {
>>> - u32 value;
>>> - int rc;
>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
>>> + int rc, idx;
>>>
>>> /* Mode (clock phase/polarity/etc.) */
>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13 +2399,21
>> @@
>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
>>> spi_device *spi,
>>> }
>>>
>>> /* Device address */
>>> - rc = of_property_read_u32(nc, "reg", &value);
>>> - if (rc) {
>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
>>> + SPI_CS_CNT_MAX);
>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>> (%d)\n",
>>> nc, rc);
>>> return rc;
>>> + } else if ((of_property_read_bool(nc, "parallel-memories")) &&
>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
>> multi
>>> CS\n");
>>> + return -EINVAL;
>>> }
>>> - spi_set_chipselect(spi, 0, value);
>>> + for (idx = 0; idx < rc; idx++)
>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>> + /* By default set the spi->cs_index_mask as 1 */
>>> + spi->cs_index_mask = 0x01;
>>>
>>> /* Device speed */
>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device *spi,
>>> struct spi_message *message)
>>> * cs_change is set for each transfer.
>>> */
>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>> SPI_CS_WORD) ||
>>> - spi_get_csgpiod(spi, 0))) {
>>> + spi_get_csgpiod(spi, 0) ||
>>> + spi_get_csgpiod(spi, 1))) {
>>> size_t maxsize;
>>> int ret;
>>>
>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
>>> 873ced6ae4ca..6453b246e0af 100644
>>> --- a/include/linux/spi/spi.h
>>> +++ b/include/linux/spi/spi.h
>>> @@ -19,6 +19,11 @@
>>> #include <linux/acpi.h>
>>> #include <linux/u64_stats_sync.h>
>>>
>>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX 2
>>> +
>>> +/* chip select mask */
>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
>>> struct dma_chan;
>>> struct software_node;
>>> struct ptp_system_timestamp;
>>> @@ -166,6 +171,7 @@ extern void
>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>> * deasserted. If @cs_change_delay is used from @spi_transfer,
>>> then the
>>> * two delays will be added up.
>>> * @pcpu_statistics: statistics for the spi_device
>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>> chipselect array
>>> *
>>> * A @spi_device is used to interchange data between an SPI slave
>>> * (usually a discrete chip) and CPU memory.
>>> @@ -181,7 +187,7 @@ struct spi_device {
>>> struct spi_controller *controller;
>>> struct spi_controller *master; /* Compatibility layer
>> */
>>> u32 max_speed_hz;
>>> - u8 chip_select;
>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>> u8 bits_per_word;
>>> bool rt;
>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>> @@ -202,7 +208,7 @@ struct spi_device {
>>> void *controller_data;
>>> char modalias[SPI_NAME_SIZE];
>>> const char *driver_override;
>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
>> desc
>>> */
>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
>> Chip
>>> select gpio desc */
>>> struct spi_delay word_delay; /* Inter-word delay */
>>> /* CS delays */
>>> struct spi_delay cs_setup;
>>> @@ -212,6 +218,13 @@ struct spi_device {
>>> /* The statistics */
>>> struct spi_statistics __percpu *pcpu_statistics;
>>>
>>> + /* Bit mask of the chipselect(s) that the driver need to use
>> from
>>> + * the chipselect array.When the controller is capable to
>> handle
>>> + * multiple chip selects & memories are connected in parallel
>>> + * then more than one bit need to be set in cs_index_mask.
>>> + */
>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>> +
>>> /*
>>> * likely need more hooks for more protocol options affecting how
>>> * the controller talks to each chip, like:
>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const struct
>>> spi_device *spi)
>>>
>>> static inline u8 spi_get_chipselect(const struct spi_device *spi,
>> u8 idx)
>>> {
>>> - return spi->chip_select;
>>> + return spi->chip_select[idx];
>>> }
>>>
>>> static inline void spi_set_chipselect(struct spi_device *spi, u8
>> idx, u8
>>> chipselect)
>>> {
>>> - spi->chip_select = chipselect;
>>> + spi->chip_select[idx] = chipselect;
>>> }
>>>
>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>> spi_device
>>> *spi, u8 idx)
>>> {
>>> - return spi->cs_gpiod;
>>> + return spi->cs_gpiod[idx];
>>> }
>>>
>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx,
>> struct
>>> gpio_desc *csgpiod)
>>> {
>>> - spi->cs_gpiod = csgpiod;
>>> + spi->cs_gpiod[idx] = csgpiod;
>>> }
>>>
>>> /**
>>> @@ -388,6 +401,8 @@ extern struct spi_device
>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>> exclusive use
>>> + * @multi_cs_cap: indicates that the SPI Controller can
>> assert/de-assert
>>> + * more than one chip select at once.
>>> * @setup: updates the device mode and clocking records used by a
>>> * device's SPI controller; protocol code may call this. This
>>> * must fail if an unrecognized or unsupported mode is requested.
>>> @@ -554,6 +569,11 @@ struct spi_controller {
>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
>>> */
>>>
>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
>> select
>>> slave */
>>> + /*
>>> + * The spi-controller has multi chip select capability and can
>>> + * assert/de-assert more than one chip select at once.
>>> + */
>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
>>>
>>> /* Flag indicating if the allocation of this struct is devres-
>>> managed */
>>> bool devm_allocated;
>>> --
>>> 2.17.1
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Wednesday, April 12, 2023 8:33 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
> in SPI core
>
> Hi,
>
> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Thursday, April 6, 2023 7:14 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]
> >> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal
> <[email protected]>;
> >> [email protected]; [email protected];
> >> [email protected]; [email protected]
> >> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >> support in SPI core
> >>
> >> Hi,
> >>
> >>> -----Original Message-----
> >>> From: Amit Kumar Mahapatra <[email protected]>
> >>> Sent: Thursday, April 6, 2023 7:54 AM
> >>> To: [email protected]; [email protected];
> >>> [email protected]; [email protected]; [email protected];
> >>> [email protected]; [email protected]
> >>> Cc: [email protected]; [email protected]; linux-
> >>> [email protected]; [email protected]; linux-
> >>> [email protected]; [email protected];
> >>> [email protected]; [email protected];
> >>> [email protected]; [email protected];
> >>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
> >>> [email protected]>
> >>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >> support
> >>> in SPI core
> >>>
> >>> For supporting multiple CS the SPI device need to be aware of all
> >> the CS
> >>> values. So, the "chip_select" member in the spi_device structure is
> >> now
> >>> an
> >>> array that holds all the CS values.
> >>>
> >>> spi_device structure now has a "cs_index_mask" member. This acts as
> >> an
> >>> index to the chip_select array. If nth bit of spi->cs_index_mask is
> >> set
> >>> then the driver would assert spi->chip_select[n].
> >>>
> >>> In parallel mode all the chip selects are asserted/de-asserted
> >>> simultaneously and each byte of data is stored in both devices, the
> >> even
> >>> bits in one, the odd bits in the other. The split is automatically
> >> handled
> >>> by the GQSPI controller. The GQSPI controller supports a maximum of
> >>> two flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS
> >>> flag bit is added in the spi controntroller flags, through
> >>> ctlr->flags the spi
> >> core
> >>> will make sure that the controller is capable of handling multiple
> >> chip
> >>> selects at once.
> >>>
> >>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>> spi_device structure is now an array that holds the gpio descriptor
> >>> for each chipselect.
> >>>
> >>> Multi CS support using GPIO is not tested due to unavailability of
> >>> necessary hardware setup.
> >>>
> >>> Multi CS configuration with one native CS and one GPIO CS is not
> >>> supported as this configuration could not be tested due to
> >>> unavailability of necessary hardware setup.
> >> I've tested this chain on a released laptop (HP EliteBook 840 G9)
> >> which uses SPI to interface to 2 amps, one amp uses a native CS and
> >> the other uses a GPIO CS, and I noticed that when using this chain,
> >> the second amp no longer works.
> > Thank you for testing this patch series on GPIO CS setup. As I don't
> > have a GPIO CS setup, is it possible for you debug the failure and
> > share more details/logs where the problem is?
> >
> > Regards,
> > Amit
>
> We are willing and able to debug this failure and share the failure logs.
> The first issue that I see is a kernel crash when trying to set the GPIO CS:
>
> [ 2.951658] general protection fault, probably for non-canonical address
> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771] CPU: 9
> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30
> [ 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
> [ 2.951882] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77 2c <48>
> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c [ 2.952043]
> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> 0000000000000000
> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> dead000000000122
> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> ffffc008c0deb868
> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> dead000000000122
> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
> 0000000000000000
> [ 2.952299] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
> knlGS:0000000000000000
> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> 0000000000770ee0
> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> 0000000000000400
> [ 2.952533] PKRU: 55555554
> [ 2.952561] Call Trace:
> [ 2.952579] <TASK>
> [ 2.952598] spi_set_cs+0x257/0x4a0
> [ 2.952630] spi_setup+0x1a2/0x500
> [ 2.952667] __spi_add_device+0x88/0x160
> [ 2.952710] spi_add_device+0x60/0x90
> [ 2.952738] smi_spi_probe+0x178/0x370 [serial_multi_instantiate]
> [ 2.952792] smi_probe+0xcf/0x110 [serial_multi_instantiate]
> [ 2.952854] platform_probe+0x42/0xb0
> [ 2.952885] really_probe+0x1b2/0x420
> [ 2.952914] __driver_probe_device+0x7e/0x180
> [ 2.952947] driver_probe_device+0x23/0xa0
> [ 2.952993] __driver_attach+0xe4/0x1e0 [ 2.953021] ?
> __pfx___driver_attach+0x10/0x10
> [ 2.953061] bus_for_each_dev+0x7a/0xd0
> [ 2.953088] driver_attach+0x1e/0x30
> [ 2.953123] bus_add_driver+0x11c/0x220
> [ 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
> __pfx_init_module+0x10/0x10 [serial_multi_instantiate]
> [ 2.953221] __platform_driver_register+0x1e/0x30
> [ 2.953251] smi_driver_init+0x1c/0xff0 [serial_multi_instantiate]
> [ 2.953310] do_one_initcall+0x46/0x220 [ 2.953339] ?
> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220
> [ 2.953411] load_module+0x223c/0x2460
> [ 2.953450] __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
> __do_sys_finit_module+0xc8/0x140
> [ 2.953510] __x64_sys_finit_module+0x18/0x20
> [ 2.953538] do_syscall_64+0x38/0x90
> [ 2.953574] entry_SYSCALL_64_after_hwframe+0x72/0xdc
> [ 2.953606] RIP: 0033:0x7f7fa5d7476d
> [ 2.953639] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
> [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246 ORIG_RAX:
> 0000000000000139
> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
> 00007f7fa5d7476d
> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
> 0000000000000006
> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
> 0000000000000000
> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
> 00007f7fa5c54ded
> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
> 000055d648654ab0
> [ 2.967668] resource: resource sanity check: requesting [mem
> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp 00:04
> [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [ 2.971615] caller
> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [ 2.975014]
> Modules linked in: igen6_edac(+) fjes(-)
> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel acpi_tad
> sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp parport drm
> ramoops reed_solomon efi_pstore ip_tables x_tables autofs4
> spi_pxa2xx_platform dw_dmac dw_dmac_core nvme intel_lpss_pci
> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64 nvme_core
> i2c_smbus virt_dma xhci_pci_renesas video wmi pinctrl_tigerlake
> [ 2.987901] ---[ end trace 0000000000000000 ]--- [ 3.157030] RIP:
> 0010:gpiod_set_value_cansleep+0x21/0xa0
> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77 2c <48>
> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c [ 3.161461]
> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> 0000000000000000
> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> dead000000000122
> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> ffffc008c0deb868
> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> dead000000000122
> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
> 0000000000000000
> [ 3.175335] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
> knlGS:0000000000000000
> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> 0000000000770ee0
> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> 0000000000000400
> [ 3.188647] PKRU: 55555554
Thank you for sharing the logs.
As per our analysis the spi->cs_gpiod[0] is getting messed up while
setting it in __spi_add_device( ).
Is it possible for you to do the following changes on top of this patch
series & re-run your test.
After applying this patch series, in drivers/spi/spi.c file replace the
following code snippet in __spi_add_device( ) function defination.
if (ctlr->cs_gpiods) {
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
}
with the below code snippet
if (ctlr->cs_gpiods) {
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
}
}
then re-run your test.
Regards,
Amit
>
> Thanks,
>
> Stefan
>
> >
> >> Thanks,
> >> Stefan Binding
> >>
> >>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> >> [email protected]>
> >>> ---
> >>> drivers/spi/spi.c | 226
> >> ++++++++++++++++++++++++++++------------
> >>> include/linux/spi/spi.h | 32 ++++--
> >>> 2 files changed, 183 insertions(+), 75 deletions(-)
> >>>
> >>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>> 9036d7a50674..04d7322170c4 100644
> >>> --- a/drivers/spi/spi.c
> >>> +++ b/drivers/spi/spi.c
> >>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
> >>> void *data) {
> >>> struct spi_device *spi = to_spi_device(dev);
> >>> struct spi_device *new_spi = data;
> >>> + int idx, nw_idx;
> >>>
> >>> - if (spi->controller == new_spi->controller &&
> >>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
> >> 0))
> >>> - return -EBUSY;
> >>> + if (spi->controller == new_spi->controller) {
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >>> nw_idx++) {
> >>> + if ((idx != 0 &&
> >> !spi_get_chipselect(spi,
> >>> idx)) ||
> >>> + (nw_idx != 0 &&
> >>> !spi_get_chipselect(spi, nw_idx))) {
> >>> + continue;
> >>> + } else if (spi_get_chipselect(spi,
> >> idx) ==
> >>> + spi_get_chipselect(new_spi,
> >> nw_idx))
> >>> {
> >>> + dev_err(dev,
> >>> + "chipselect %d already
> >>> in use\n",
> >>> +
> >>> spi_get_chipselect(new_spi, nw_idx));
> >>> + return -EBUSY;
> >>> + }
> >>> + }
> >>> + }
> >>> + }
> >>> return 0;
> >>> }
> >>>
> >>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
> >>> *spi)
> >>> {
> >>> struct spi_controller *ctlr = spi->controller;
> >>> struct device *dev = ctlr->dev.parent;
> >>> - int status;
> >>> + int status, idx;
> >>>
> >>> /*
> >>> * We need to make sure there's no other device with this @@
> >>> -638,8
> >>> +652,6 @@ static int __spi_add_device(struct spi_device
> >>> *spi)
> >>> */
> >>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> >> spi_dev_check);
> >>> if (status) {
> >>> - dev_err(dev, "chipselect %d already in use\n",
> >>> - spi_get_chipselect(spi, 0));
> >>> return status;
> >>> }
> >>>
> >>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
> >>> *spi)
> >>> return -ENODEV;
> >>> }
> >>>
> >>> - if (ctlr->cs_gpiods)
> >>> - spi_set_csgpiod(spi, 0, ctlr-
> >>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
> >>> + if (ctlr->cs_gpiods) {
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> + spi_set_csgpiod(spi, idx, ctlr-
> >>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
> >>> + }
> >>>
> >>> /*
> >>> * Drivers may modify this initial i/o setup, but will @@ -690,13
> >>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
> >>> struct spi_controller *ctlr = spi->controller;
> >>> struct device *dev = ctlr->dev.parent;
> >>> - int status;
> >>> + int status, idx;
> >>>
> >>> - /* Chipselects are numbered 0..max; validate. */
> >>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>> - dev_err(dev, "cs%d >= max %d\n",
> >>> spi_get_chipselect(spi, 0),
> >>> - ctlr->num_chipselect);
> >>> - return -EINVAL;
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + /* Chipselects are numbered 0..max; validate. */
> >>> + if (spi_get_chipselect(spi, idx) >=
> >> ctlr->num_chipselect) {
> >>> + dev_err(dev, "cs%d >= max %d\n",
> >>> spi_get_chipselect(spi, idx),
> >>> + ctlr->num_chipselect);
> >>> + return -EINVAL;
> >>> + }
> >>> }
> >>>
> >>> /* Set the bus ID string */
> >>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
> >>> spi_device *spi) {
> >>> struct spi_controller *ctlr = spi->controller;
> >>> struct device *dev = ctlr->dev.parent;
> >>> + int idx;
> >>>
> >>> - /* Chipselects are numbered 0..max; validate. */
> >>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>> - dev_err(dev, "cs%d >= max %d\n",
> >>> spi_get_chipselect(spi, 0),
> >>> - ctlr->num_chipselect);
> >>> - return -EINVAL;
> >>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> + /* Chipselects are numbered 0..max; validate. */
> >>> + if (spi_get_chipselect(spi, idx) >=
> >> ctlr->num_chipselect) {
> >>> + dev_err(dev, "cs%d >= max %d\n",
> >>> spi_get_chipselect(spi, idx),
> >>> + ctlr->num_chipselect);
> >>> + return -EINVAL;
> >>> + }
> >>> }
> >>>
> >>> /* Set the bus ID string */
> >>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
> >>> spi_controller *ctlr, struct spi_message *mes static void
> >>> spi_set_cs(struct spi_device *spi, bool enable, bool
> >> force)
> >>> {
> >>> bool activate = enable;
> >>> + u32 cs_num = __ffs(spi->cs_index_mask);
> >>> + int idx;
> >>>
> >>> /*
> >>> - * Avoid calling into the driver (or doing delays) if the chip
> >> select
> >>> - * isn't actually changing from the last time this was called.
> >>> + * In parallel mode all the chip selects are
> >> asserted/de-asserted
> >>> + * at once
> >>> */
> >>> - if (!force && ((enable && spi->controller->last_cs ==
> >>> spi_get_chipselect(spi, 0)) ||
> >>> - (!enable && spi->controller->last_cs !=
> >>> spi_get_chipselect(spi, 0))) &&
> >>> - (spi->controller->last_cs_mode_high == (spi->mode &
> >>> SPI_CS_HIGH)))
> >>> - return;
> >>> -
> >>> - trace_spi_set_cs(spi, activate);
> >>> -
> >>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
> >> : -1;
> >>> - spi->controller->last_cs_mode_high = spi->mode &
> >>> SPI_CS_HIGH;
> >>> -
> >>> - if ((spi_get_csgpiod(spi, 0) ||
> >> !spi->controller->set_cs_timing)
> >>> && !activate)
> >>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>> -
> >>> - if (spi->mode & SPI_CS_HIGH)
> >>> - enable = !enable;
> >>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
> >>> SPI_PARALLEL_CS_MASK) {
> >>> + spi->controller->last_cs_mode_high = spi->mode &
> >>> SPI_CS_HIGH;
> >>> +
> >>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> >>>> set_cs_timing) && !activate)
> >>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>> +
> >>> + if (spi->mode & SPI_CS_HIGH)
> >>> + enable = !enable;
> >>> +
> >>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
> >> 1)) {
> >>> + if (!(spi->mode & SPI_NO_CS)) {
> >>> + /*
> >>> + * Historically ACPI has no means of
> >> the
> >>> GPIO polarity and
> >>> + * thus the SPISerialBus() resource
> >>> defines it on the per-chip
> >>> + * basis. In order to avoid a chain of
> >>> negations, the GPIO
> >>> + * polarity is considered being Active
> >>> High. Even for the cases
> >>> + * when _DSD() is involved (in the
> >>> updated versions of ACPI)
> >>> + * the GPIO CS polarity must be
> >> defined
> >>> Active High to avoid
> >>> + * ambiguity. That's why we use
> >> enable,
> >>> that takes SPI_CS_HIGH
> >>> + * into account.
> >>> + */
> >>> + if (has_acpi_companion(&spi->dev)) {
> >>> + for (idx = 0; idx <
> >>> SPI_CS_CNT_MAX; idx++)
> >>> +
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>> +
> >>> !enable);
> >>> + } else {
> >>> + for (idx = 0; idx <
> >>> SPI_CS_CNT_MAX; idx++)
> >>> + /* Polarity handled by
> >>> GPIO library */
> >>> +
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>> +
> >>> activate);
> >>> + }
> >>> + }
> >>> + /* Some SPI masters need both GPIO CS &
> >>> slave_select */
> >>> + if ((spi->controller->flags &
> >>> SPI_MASTER_GPIO_SS) &&
> >>> + spi->controller->set_cs)
> >>> + spi->controller->set_cs(spi, !enable);
> >>> + } else if (spi->controller->set_cs) {
> >>> + spi->controller->set_cs(spi, !enable);
> >>> + }
> >>>
> >>> - if (spi_get_csgpiod(spi, 0)) {
> >>> - if (!(spi->mode & SPI_NO_CS)) {
> >>> - /*
> >>> - * Historically ACPI has no means of the GPIO
> >>> polarity and
> >>> - * thus the SPISerialBus() resource defines it
> >> on
> >>> the per-chip
> >>> - * basis. In order to avoid a chain of
> >> negations,
> >>> the GPIO
> >>> - * polarity is considered being Active High.
> >> Even
> >>> for the cases
> >>> - * when _DSD() is involved (in the updated
> >>> versions of ACPI)
> >>> - * the GPIO CS polarity must be defined Active
> >>> High to avoid
> >>> - * ambiguity. That's why we use enable, that
> >>> takes SPI_CS_HIGH
> >>> - * into account.
> >>> - */
> >>> - if (has_acpi_companion(&spi->dev))
> >>> -
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
> >> ||
> >>> + !spi->controller->set_cs_timing) {
> >>> + if (activate)
> >>> + spi_delay_exec(&spi->cs_setup, NULL);
> >>> else
> >>> - /* Polarity handled by GPIO library */
> >>> -
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>> + spi_delay_exec(&spi->cs_inactive,
> >>> NULL);
> >>> }
> >>> - /* Some SPI masters need both GPIO CS & slave_select
> >>> */
> >>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
> >>> - spi->controller->set_cs)
> >>> + } else {
> >>> + /*
> >>> + * Avoid calling into the driver (or doing delays) if
> >> the
> >>> chip select
> >>> + * isn't actually changing from the last time this was
> >>> called.
> >>> + */
> >>> + if (!force && ((enable && spi->controller->last_cs ==
> >>> + spi_get_chipselect(spi, cs_num)) ||
> >>> + (!enable && spi->controller->last_cs
> >> !=
> >>> + spi_get_chipselect(spi, cs_num))) &&
> >>> + (spi->controller->last_cs_mode_high ==
> >>> + (spi->mode & SPI_CS_HIGH)))
> >>> + return;
> >>> +
> >>> + trace_spi_set_cs(spi, activate);
> >>> +
> >>> + spi->controller->last_cs = enable ?
> >>> spi_get_chipselect(spi, cs_num) : -1;
> >>> + spi->controller->last_cs_mode_high = spi->mode &
> >>> SPI_CS_HIGH;
> >>> +
> >>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>> set_cs_timing) && !activate)
> >>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>> +
> >>> + if (spi->mode & SPI_CS_HIGH)
> >>> + enable = !enable;
> >>> +
> >>> + if (spi_get_csgpiod(spi, cs_num)) {
> >>> + if (!(spi->mode & SPI_NO_CS)) {
> >>> + /*
> >>> + * Historically ACPI has no means of
> >> the
> >>> GPIO polarity and
> >>> + * thus the SPISerialBus() resource
> >>> defines it on the per-chip
> >>> + * basis. In order to avoid a chain of
> >>> negations, the GPIO
> >>> + * polarity is considered being Active
> >>> High. Even for the cases
> >>> + * when _DSD() is involved (in the
> >>> updated versions of ACPI)
> >>> + * the GPIO CS polarity must be
> >> defined
> >>> Active High to avoid
> >>> + * ambiguity. That's why we use
> >> enable,
> >>> that takes SPI_CS_HIGH
> >>> + * into account.
> >>> + */
> >>> + if (has_acpi_companion(&spi->dev))
> >>> +
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>> +
> >>> !enable);
> >>> + else
> >>> + /* Polarity handled by GPIO
> >>> library */
> >>> +
> >>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>> +
> >>> activate);
> >>> + }
> >>> + /* Some SPI masters need both GPIO CS &
> >>> slave_select */
> >>> + if ((spi->controller->flags &
> >>> SPI_MASTER_GPIO_SS) &&
> >>> + spi->controller->set_cs)
> >>> + spi->controller->set_cs(spi, !enable);
> >>> + } else if (spi->controller->set_cs) {
> >>> spi->controller->set_cs(spi, !enable);
> >>> - } else if (spi->controller->set_cs) {
> >>> - spi->controller->set_cs(spi, !enable);
> >>> - }
> >>> + }
> >>>
> >>> - if (spi_get_csgpiod(spi, 0) ||
> >> !spi->controller->set_cs_timing) {
> >>> - if (activate)
> >>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>> - else
> >>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>> set_cs_timing) {
> >>> + if (activate)
> >>> + spi_delay_exec(&spi->cs_setup, NULL);
> >>> + else
> >>> + spi_delay_exec(&spi->cs_inactive,
> >>> NULL);
> >>> + }
> >>> }
> >>> }
> >>>
> >>> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
> >>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
> >>> *ctlr, struct
> >> spi_device
> >>> *spi,
> >>> struct device_node *nc)
> >>> {
> >>> - u32 value;
> >>> - int rc;
> >>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
> >>> + int rc, idx;
> >>>
> >>> /* Mode (clock phase/polarity/etc.) */
> >>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13 +2399,21
> >> @@
> >>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> >>> spi_device *spi,
> >>> }
> >>>
> >>> /* Device address */
> >>> - rc = of_property_read_u32(nc, "reg", &value);
> >>> - if (rc) {
> >>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
> >>> + SPI_CS_CNT_MAX);
> >>> + if (rc < 0 || rc > ctlr->num_chipselect) {
> >>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >> (%d)\n",
> >>> nc, rc);
> >>> return rc;
> >>> + } else if ((of_property_read_bool(nc, "parallel-memories")) &&
> >>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>> + dev_err(&ctlr->dev, "SPI controller doesn't support
> >> multi
> >>> CS\n");
> >>> + return -EINVAL;
> >>> }
> >>> - spi_set_chipselect(spi, 0, value);
> >>> + for (idx = 0; idx < rc; idx++)
> >>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>> + /* By default set the spi->cs_index_mask as 1 */
> >>> + spi->cs_index_mask = 0x01;
> >>>
> >>> /* Device speed */
> >>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
> >>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device *spi,
> >>> struct spi_message *message)
> >>> * cs_change is set for each transfer.
> >>> */
> >>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >>> SPI_CS_WORD) ||
> >>> - spi_get_csgpiod(spi, 0))) {
> >>> + spi_get_csgpiod(spi, 0) ||
> >>> + spi_get_csgpiod(spi, 1))) {
> >>> size_t maxsize;
> >>> int ret;
> >>>
> >>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
> >>> 873ced6ae4ca..6453b246e0af 100644
> >>> --- a/include/linux/spi/spi.h
> >>> +++ b/include/linux/spi/spi.h
> >>> @@ -19,6 +19,11 @@
> >>> #include <linux/acpi.h>
> >>> #include <linux/u64_stats_sync.h>
> >>>
> >>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX
> >>> +2
> >>> +
> >>> +/* chip select mask */
> >>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
> >>> struct dma_chan;
> >>> struct software_node;
> >>> struct ptp_system_timestamp;
> >>> @@ -166,6 +171,7 @@ extern void
> >>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>> * deasserted. If @cs_change_delay is used from @spi_transfer,
> >>> then the
> >>> * two delays will be added up.
> >>> * @pcpu_statistics: statistics for the spi_device
> >>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>> chipselect array
> >>> *
> >>> * A @spi_device is used to interchange data between an SPI slave
> >>> * (usually a discrete chip) and CPU memory.
> >>> @@ -181,7 +187,7 @@ struct spi_device {
> >>> struct spi_controller *controller;
> >>> struct spi_controller *master; /* Compatibility layer
> >> */
> >>> u32 max_speed_hz;
> >>> - u8 chip_select;
> >>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>> u8 bits_per_word;
> >>> bool rt;
> >>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>> @@ -202,7 +208,7 @@ struct spi_device {
> >>> void *controller_data;
> >>> char modalias[SPI_NAME_SIZE];
> >>> const char *driver_override;
> >>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
> >> desc
> >>> */
> >>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> >> Chip
> >>> select gpio desc */
> >>> struct spi_delay word_delay; /* Inter-word delay */
> >>> /* CS delays */
> >>> struct spi_delay cs_setup;
> >>> @@ -212,6 +218,13 @@ struct spi_device {
> >>> /* The statistics */
> >>> struct spi_statistics __percpu *pcpu_statistics;
> >>>
> >>> + /* Bit mask of the chipselect(s) that the driver need to use
> >> from
> >>> + * the chipselect array.When the controller is capable to
> >> handle
> >>> + * multiple chip selects & memories are connected in parallel
> >>> + * then more than one bit need to be set in cs_index_mask.
> >>> + */
> >>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>> +
> >>> /*
> >>> * likely need more hooks for more protocol options affecting how
> >>> * the controller talks to each chip, like:
> >>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
> >>> struct spi_device *spi)
> >>>
> >>> static inline u8 spi_get_chipselect(const struct spi_device *spi,
> >> u8 idx)
> >>> {
> >>> - return spi->chip_select;
> >>> + return spi->chip_select[idx];
> >>> }
> >>>
> >>> static inline void spi_set_chipselect(struct spi_device *spi, u8
> >> idx, u8
> >>> chipselect)
> >>> {
> >>> - spi->chip_select = chipselect;
> >>> + spi->chip_select[idx] = chipselect;
> >>> }
> >>>
> >>> static inline struct gpio_desc *spi_get_csgpiod(const struct
> >> spi_device
> >>> *spi, u8 idx)
> >>> {
> >>> - return spi->cs_gpiod;
> >>> + return spi->cs_gpiod[idx];
> >>> }
> >>>
> >>> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx,
> >> struct
> >>> gpio_desc *csgpiod)
> >>> {
> >>> - spi->cs_gpiod = csgpiod;
> >>> + spi->cs_gpiod[idx] = csgpiod;
> >>> }
> >>>
> >>> /**
> >>> @@ -388,6 +401,8 @@ extern struct spi_device
> >>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >> exclusive use
> >>> + * @multi_cs_cap: indicates that the SPI Controller can
> >> assert/de-assert
> >>> + * more than one chip select at once.
> >>> * @setup: updates the device mode and clocking records used by a
> >>> * device's SPI controller; protocol code may call this. This
> >>> * must fail if an unrecognized or unsupported mode is requested.
> >>> @@ -554,6 +569,11 @@ struct spi_controller {
> >>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> >>> */
> >>>
> >>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
> >> select
> >>> slave */
> >>> + /*
> >>> + * The spi-controller has multi chip select capability and can
> >>> + * assert/de-assert more than one chip select at once.
> >>> + */
> >>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
> >>>
> >>> /* Flag indicating if the allocation of this struct is devres-
> >>> managed */
> >>> bool devm_allocated;
> >>> --
> >>> 2.17.1
Hi,
On 20/04/2023 10:04, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Wednesday, April 12, 2023 8:33 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>;
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
>> in SPI core
>>
>> Hi,
>>
>> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
>>> Hello Stefan,
>>>
>>>> -----Original Message-----
>>>> From: Stefan Binding <[email protected]>
>>>> Sent: Thursday, April 6, 2023 7:14 PM
>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]
>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; Simek, Michal
>> <[email protected]>;
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected]
>>>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>> support in SPI core
>>>>
>>>> Hi,
>>>>
>>>>> -----Original Message-----
>>>>> From: Amit Kumar Mahapatra <[email protected]>
>>>>> Sent: Thursday, April 6, 2023 7:54 AM
>>>>> To: [email protected]; [email protected];
>>>>> [email protected]; [email protected]; [email protected];
>>>>> [email protected]; [email protected]
>>>>> Cc: [email protected]; [email protected]; linux-
>>>>> [email protected]; [email protected]; linux-
>>>>> [email protected]; [email protected];
>>>>> [email protected]; [email protected];
>>>>> [email protected]; [email protected];
>>>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
>>>>> [email protected]>
>>>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>> support
>>>>> in SPI core
>>>>>
>>>>> For supporting multiple CS the SPI device need to be aware of all
>>>> the CS
>>>>> values. So, the "chip_select" member in the spi_device structure is
>>>> now
>>>>> an
>>>>> array that holds all the CS values.
>>>>>
>>>>> spi_device structure now has a "cs_index_mask" member. This acts as
>>>> an
>>>>> index to the chip_select array. If nth bit of spi->cs_index_mask is
>>>> set
>>>>> then the driver would assert spi->chip_select[n].
>>>>>
>>>>> In parallel mode all the chip selects are asserted/de-asserted
>>>>> simultaneously and each byte of data is stored in both devices, the
>>>> even
>>>>> bits in one, the odd bits in the other. The split is automatically
>>>> handled
>>>>> by the GQSPI controller. The GQSPI controller supports a maximum of
>>>>> two flashes connected in parallel mode. A SPI_CONTROLLER_MULTI_CS
>>>>> flag bit is added in the spi controntroller flags, through
>>>>> ctlr->flags the spi
>>>> core
>>>>> will make sure that the controller is capable of handling multiple
>>>> chip
>>>>> selects at once.
>>>>>
>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>>>> spi_device structure is now an array that holds the gpio descriptor
>>>>> for each chipselect.
>>>>>
>>>>> Multi CS support using GPIO is not tested due to unavailability of
>>>>> necessary hardware setup.
>>>>>
>>>>> Multi CS configuration with one native CS and one GPIO CS is not
>>>>> supported as this configuration could not be tested due to
>>>>> unavailability of necessary hardware setup.
>>>> I've tested this chain on a released laptop (HP EliteBook 840 G9)
>>>> which uses SPI to interface to 2 amps, one amp uses a native CS and
>>>> the other uses a GPIO CS, and I noticed that when using this chain,
>>>> the second amp no longer works.
>>> Thank you for testing this patch series on GPIO CS setup. As I don't
>>> have a GPIO CS setup, is it possible for you debug the failure and
>>> share more details/logs where the problem is?
>>>
>>> Regards,
>>> Amit
>> We are willing and able to debug this failure and share the failure logs.
>> The first issue that I see is a kernel crash when trying to set the GPIO CS:
>>
>> [ 2.951658] general protection fault, probably for non-canonical address
>> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771] CPU: 9
>> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30
>> [ 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
>> [ 2.951882] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
>> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77 2c <48>
>> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c [ 2.952043]
>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>> 0000000000000000
>> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>> dead000000000122
>> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>> ffffc008c0deb868
>> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>> dead000000000122
>> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
>> 0000000000000000
>> [ 2.952299] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
>> knlGS:0000000000000000
>> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>> 0000000000770ee0
>> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>> 0000000000000000
>> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>> 0000000000000400
>> [ 2.952533] PKRU: 55555554
>> [ 2.952561] Call Trace:
>> [ 2.952579] <TASK>
>> [ 2.952598] spi_set_cs+0x257/0x4a0
>> [ 2.952630] spi_setup+0x1a2/0x500
>> [ 2.952667] __spi_add_device+0x88/0x160
>> [ 2.952710] spi_add_device+0x60/0x90
>> [ 2.952738] smi_spi_probe+0x178/0x370 [serial_multi_instantiate]
>> [ 2.952792] smi_probe+0xcf/0x110 [serial_multi_instantiate]
>> [ 2.952854] platform_probe+0x42/0xb0
>> [ 2.952885] really_probe+0x1b2/0x420
>> [ 2.952914] __driver_probe_device+0x7e/0x180
>> [ 2.952947] driver_probe_device+0x23/0xa0
>> [ 2.952993] __driver_attach+0xe4/0x1e0 [ 2.953021] ?
>> __pfx___driver_attach+0x10/0x10
>> [ 2.953061] bus_for_each_dev+0x7a/0xd0
>> [ 2.953088] driver_attach+0x1e/0x30
>> [ 2.953123] bus_add_driver+0x11c/0x220
>> [ 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
>> __pfx_init_module+0x10/0x10 [serial_multi_instantiate]
>> [ 2.953221] __platform_driver_register+0x1e/0x30
>> [ 2.953251] smi_driver_init+0x1c/0xff0 [serial_multi_instantiate]
>> [ 2.953310] do_one_initcall+0x46/0x220 [ 2.953339] ?
>> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220
>> [ 2.953411] load_module+0x223c/0x2460
>> [ 2.953450] __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
>> __do_sys_finit_module+0xc8/0x140
>> [ 2.953510] __x64_sys_finit_module+0x18/0x20
>> [ 2.953538] do_syscall_64+0x38/0x90
>> [ 2.953574] entry_SYSCALL_64_after_hwframe+0x72/0xdc
>> [ 2.953606] RIP: 0033:0x7f7fa5d7476d
>> [ 2.953639] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
>> [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246 ORIG_RAX:
>> 0000000000000139
>> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
>> 00007f7fa5d7476d
>> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
>> 0000000000000006
>> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
>> 0000000000000000
>> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
>> 00007f7fa5c54ded
>> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
>> 000055d648654ab0
>> [ 2.967668] resource: resource sanity check: requesting [mem
>> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp 00:04
>> [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [ 2.971615] caller
>> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [ 2.975014]
>> Modules linked in: igen6_edac(+) fjes(-)
>> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
>> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel acpi_tad
>> sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp parport drm
>> ramoops reed_solomon efi_pstore ip_tables x_tables autofs4
>> spi_pxa2xx_platform dw_dmac dw_dmac_core nvme intel_lpss_pci
>> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64 nvme_core
>> i2c_smbus virt_dma xhci_pci_renesas video wmi pinctrl_tigerlake
>> [ 2.987901] ---[ end trace 0000000000000000 ]--- [ 3.157030] RIP:
>> 0010:gpiod_set_value_cansleep+0x21/0xa0
>> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85 ff
>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff 77 2c <48>
>> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89 ee 4c [ 3.161461]
>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>> 0000000000000000
>> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>> dead000000000122
>> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>> ffffc008c0deb868
>> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>> dead000000000122
>> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
>> 0000000000000000
>> [ 3.175335] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
>> knlGS:0000000000000000
>> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>> 0000000000770ee0
>> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>> 0000000000000000
>> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>> 0000000000000400
>> [ 3.188647] PKRU: 55555554
> Thank you for sharing the logs.
> As per our analysis the spi->cs_gpiod[0] is getting messed up while
> setting it in __spi_add_device( ).
> Is it possible for you to do the following changes on top of this patch
> series & re-run your test.
>
> After applying this patch series, in drivers/spi/spi.c file replace the
> following code snippet in __spi_add_device( ) function defination.
>
> if (ctlr->cs_gpiods) {
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
> }
>
> with the below code snippet
>
> if (ctlr->cs_gpiods) {
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
> spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
> }
> }
>
> then re-run your test.
>
> Regards,
> Amit
I'm still seeing a crash on probe:
[ 3.265683] BUG: unable to handle page fault for address:
00000000fffedfdd
[ 3.265744] #PF: supervisor read access in kernel mode
[ 3.265781] #PF: error_code(0x0000) - not-present page
[ 3.265817] PGD 0 P4D 0
[ 3.265840] Oops: 0000 [#1] PREEMPT SMP NOPTI
[ 3.265865] CPU: 4 PID: 385 Comm: systemd-udevd Tainted: G
A 6.3.0-rc3+ #32
[ 3.265910] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
[ 3.265956] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
[ 3.266007] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
[ 3.266092] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03
[ 3.266121] RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
cccccccccccccccd
[ 3.266156] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
ffff9c8d4a5f6d40
[ 3.266192] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
0000000000000000
[ 3.266228] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
00000000fffedf7d
[ 3.266264] R13: 0000000000000000 R14: 0000000000000001 R15:
0000000000000001
[ 3.266299] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
knlGS:0000000000000000
[ 3.266358] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 3.266388] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
0000000000770ee0
[ 3.266422] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
0000000000000000
[ 3.266457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
0000000000000400
[ 3.266490] PKRU: 55555554
[ 3.266513] Call Trace:
[ 3.266530] <TASK>
[ 3.266546] gpiod_set_value_nocheck+0x5b/0x70
[ 3.266583] gpiod_set_value_cansleep+0x3e/0xa0
[ 3.266609] spi_set_cs+0x257/0x4a0
[ 3.266634] spi_transfer_one_message+0x49/0x740
[ 3.266672] __spi_pump_transfer_message+0x29b/0x620
[ 3.266712] __spi_sync+0x26f/0x3b0
[ 3.266735] spi_write_then_read+0x157/0x210
[ 3.266771] ? psi_group_change+0x175/0x3b0
[ 3.266802] regmap_spi_read+0xe/0x20
[ 3.266826] _regmap_raw_read+0xe1/0x210
[ 3.266861] _regmap_bus_read+0x3a/0x70
[ 3.266887] _regmap_read+0x66/0x140
[ 3.266918] regmap_read+0x3f/0x70
[ 3.266957] cs35l41_hda_probe+0x553/0xc10 [snd_hda_scodec_cs35l41]
[ 3.267027] cs35l41_hda_spi_probe+0x62/0x80 [snd_hda_scodec_cs35l41_spi]
[ 3.267096] spi_probe+0x55/0x90
[ 3.267145] really_probe+0x1b2/0x420
[ 3.267184] __driver_probe_device+0x7e/0x180
[ 3.267227] driver_probe_device+0x23/0xa0
[ 3.267287] __driver_attach+0xe4/0x1e0
[ 3.267326] ? __pfx___driver_attach+0x10/0x10
[ 3.267381] bus_for_each_dev+0x7a/0xd0
[ 3.267406] driver_attach+0x1e/0x30
[ 3.267437] bus_add_driver+0x11c/0x220
[ 3.267461] driver_register+0x64/0x130
[ 3.267483] ? __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
[ 3.267525] __spi_register_driver+0xa1/0xd0
[ 3.270712] ? __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
[ 3.273446] cs35l41_spi_driver_init+0x1c/0xff0
[snd_hda_scodec_cs35l41_spi]
[ 3.275119] do_one_initcall+0x46/0x220
[ 3.276828] ? kmalloc_trace+0x2a/0xa0
[ 3.279290] do_init_module+0x52/0x220
[ 3.283593] load_module+0x223c/0x2460
[ 3.283602] __do_sys_finit_module+0xc8/0x140
[ 3.287883] ? __do_sys_finit_module+0xc8/0x140
[ 3.287907] __x64_sys_finit_module+0x18/0x20
[ 3.293156] do_syscall_64+0x38/0x90
[ 3.298937] entry_SYSCALL_64_after_hwframe+0x72/0xdc
[ 3.298945] RIP: 0033:0x7f98d06f776d
[ 3.319574] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
[ 3.319579] RSP: 002b:00007ffd988f7a08 EFLAGS: 00000246 ORIG_RAX:
0000000000000139
[ 3.319585] RAX: ffffffffffffffda RBX: 000055af06a7d030 RCX:
00007f98d06f776d
[ 3.319589] RDX: 0000000000000000 RSI: 00007f98d05d7ded RDI:
0000000000000013
[ 3.329520] RBP: 0000000000020000 R08: 0000000000000000 R09:
0000000000000000
[ 3.329523] R10: 0000000000000013 R11: 0000000000000246 R12:
00007f98d05d7ded
[ 3.329525] R13: 0000000000000000 R14: 000055af06cdd040 R15:
000055af06a7d030
[ 3.329531] </TASK>
[ 3.329533] Modules linked in: snd_hda_intel(+) ttm snd_intel_dspcfg
btusb rapl snd_seq_midi snd_intel_sdw_acpi libarc4 intel_cstate
binfmt_misc uvcvideo(+) snd_seq_midi_event btrtl
snd_hda_scodec_cs35l41_spi(+) snd_hda_codec drm_display_helper
cdc_ncm(+) videobuf2_vmalloc snd_rawmidi btbcm uvc cdc_ether cec btintel
videobuf2_memops snd_hda_scodec_cs35l41_i2c snd_hda_core videobuf2_v4l2
uas usbnet rc_core snd_hwdep btmtk snd_hda_scodec_cs35l41 input_leds mii
wmi_bmof videodev snd_seq processor_thermal_device_pci bluetooth iwlwifi
drm_kms_helper snd_pcm snd_hda_cs_dsp_ctls processor_thermal_device
mei_me videobuf2_common snd_seq_device i2c_algo_bit cs_dsp
processor_thermal_rfim ecdh_generic usb_storage serio_raw mc syscopyarea
ecc processor_thermal_mbox ucsi_acpi snd_soc_cs35l41_lib 8250_dw mei
snd_timer cfg80211 sysfillrect typec_ucsi processor_thermal_rapl
igen6_edac sysimgblt intel_rapl_common typec snd soundcore
int3403_thermal int340x_thermal_zone serial_multi_instantiate
int3400_thermal intel_hid acpi_thermal_rel
[ 3.338475] sparse_keymap acpi_tad acpi_pad mac_hid sch_fq_codel msr
parport_pc ppdev lp parport drm ramoops reed_solomon efi_pstore
ip_tables x_tables autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core
intel_lpss_pci nvme intel_lpss i2c_i801 idma64 crc32_pclmul thunderbolt
i2c_smbus nvme_core xhci_pci virt_dma xhci_pci_renesas video wmi
pinctrl_tigerlake
[ 3.338514] CR2: 00000000fffedfdd
[ 3.338517] ---[ end trace 0000000000000000 ]---
[ 3.504965] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
[ 3.504973] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
[ 3.504975] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03
[ 3.504978] RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
cccccccccccccccd
[ 3.504979] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
ffff9c8d4a5f6d40
[ 3.504980] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
0000000000000000
[ 3.504982] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
00000000fffedf7d
[ 3.504983] R13: 0000000000000000 R14: 0000000000000001 R15:
0000000000000001
[ 3.504984] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
knlGS:0000000000000000
[ 3.504986] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
[ 3.504988] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
0000000000770ee0
[ 3.504989] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
0000000000000000
[ 3.504990] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
0000000000000400
[ 3.504992] PKRU: 55555554
Thanks,
Stefan
>> Thanks,
>>
>> Stefan
>>
>>>> Thanks,
>>>> Stefan Binding
>>>>
>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>>>> [email protected]>
>>>>> ---
>>>>> drivers/spi/spi.c | 226
>>>> ++++++++++++++++++++++++++++------------
>>>>> include/linux/spi/spi.h | 32 ++++--
>>>>> 2 files changed, 183 insertions(+), 75 deletions(-)
>>>>>
>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>>>> 9036d7a50674..04d7322170c4 100644
>>>>> --- a/drivers/spi/spi.c
>>>>> +++ b/drivers/spi/spi.c
>>>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
>>>>> void *data) {
>>>>> struct spi_device *spi = to_spi_device(dev);
>>>>> struct spi_device *new_spi = data;
>>>>> + int idx, nw_idx;
>>>>>
>>>>> - if (spi->controller == new_spi->controller &&
>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
>>>> 0))
>>>>> - return -EBUSY;
>>>>> + if (spi->controller == new_spi->controller) {
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>>>> nw_idx++) {
>>>>> + if ((idx != 0 &&
>>>> !spi_get_chipselect(spi,
>>>>> idx)) ||
>>>>> + (nw_idx != 0 &&
>>>>> !spi_get_chipselect(spi, nw_idx))) {
>>>>> + continue;
>>>>> + } else if (spi_get_chipselect(spi,
>>>> idx) ==
>>>>> + spi_get_chipselect(new_spi,
>>>> nw_idx))
>>>>> {
>>>>> + dev_err(dev,
>>>>> + "chipselect %d already
>>>>> in use\n",
>>>>> +
>>>>> spi_get_chipselect(new_spi, nw_idx));
>>>>> + return -EBUSY;
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> + }
>>>>> return 0;
>>>>> }
>>>>>
>>>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
>>>>> *spi)
>>>>> {
>>>>> struct spi_controller *ctlr = spi->controller;
>>>>> struct device *dev = ctlr->dev.parent;
>>>>> - int status;
>>>>> + int status, idx;
>>>>>
>>>>> /*
>>>>> * We need to make sure there's no other device with this @@
>>>>> -638,8
>>>>> +652,6 @@ static int __spi_add_device(struct spi_device
>>>>> *spi)
>>>>> */
>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
>>>> spi_dev_check);
>>>>> if (status) {
>>>>> - dev_err(dev, "chipselect %d already in use\n",
>>>>> - spi_get_chipselect(spi, 0));
>>>>> return status;
>>>>> }
>>>>>
>>>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
>>>>> *spi)
>>>>> return -ENODEV;
>>>>> }
>>>>>
>>>>> - if (ctlr->cs_gpiods)
>>>>> - spi_set_csgpiod(spi, 0, ctlr-
>>>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
>>>>> + if (ctlr->cs_gpiods) {
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>> + spi_set_csgpiod(spi, idx, ctlr-
>>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>>>> + }
>>>>>
>>>>> /*
>>>>> * Drivers may modify this initial i/o setup, but will @@ -690,13
>>>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
>>>>> struct spi_controller *ctlr = spi->controller;
>>>>> struct device *dev = ctlr->dev.parent;
>>>>> - int status;
>>>>> + int status, idx;
>>>>>
>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>> spi_get_chipselect(spi, 0),
>>>>> - ctlr->num_chipselect);
>>>>> - return -EINVAL;
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>> ctlr->num_chipselect) {
>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>> spi_get_chipselect(spi, idx),
>>>>> + ctlr->num_chipselect);
>>>>> + return -EINVAL;
>>>>> + }
>>>>> }
>>>>>
>>>>> /* Set the bus ID string */
>>>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
>>>>> spi_device *spi) {
>>>>> struct spi_controller *ctlr = spi->controller;
>>>>> struct device *dev = ctlr->dev.parent;
>>>>> + int idx;
>>>>>
>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>> spi_get_chipselect(spi, 0),
>>>>> - ctlr->num_chipselect);
>>>>> - return -EINVAL;
>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>> ctlr->num_chipselect) {
>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>> spi_get_chipselect(spi, idx),
>>>>> + ctlr->num_chipselect);
>>>>> + return -EINVAL;
>>>>> + }
>>>>> }
>>>>>
>>>>> /* Set the bus ID string */
>>>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
>>>>> spi_controller *ctlr, struct spi_message *mes static void
>>>>> spi_set_cs(struct spi_device *spi, bool enable, bool
>>>> force)
>>>>> {
>>>>> bool activate = enable;
>>>>> + u32 cs_num = __ffs(spi->cs_index_mask);
>>>>> + int idx;
>>>>>
>>>>> /*
>>>>> - * Avoid calling into the driver (or doing delays) if the chip
>>>> select
>>>>> - * isn't actually changing from the last time this was called.
>>>>> + * In parallel mode all the chip selects are
>>>> asserted/de-asserted
>>>>> + * at once
>>>>> */
>>>>> - if (!force && ((enable && spi->controller->last_cs ==
>>>>> spi_get_chipselect(spi, 0)) ||
>>>>> - (!enable && spi->controller->last_cs !=
>>>>> spi_get_chipselect(spi, 0))) &&
>>>>> - (spi->controller->last_cs_mode_high == (spi->mode &
>>>>> SPI_CS_HIGH)))
>>>>> - return;
>>>>> -
>>>>> - trace_spi_set_cs(spi, activate);
>>>>> -
>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
>>>> : -1;
>>>>> - spi->controller->last_cs_mode_high = spi->mode &
>>>>> SPI_CS_HIGH;
>>>>> -
>>>>> - if ((spi_get_csgpiod(spi, 0) ||
>>>> !spi->controller->set_cs_timing)
>>>>> && !activate)
>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>>>> -
>>>>> - if (spi->mode & SPI_CS_HIGH)
>>>>> - enable = !enable;
>>>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
>>>>> SPI_PARALLEL_CS_MASK) {
>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>> SPI_CS_HIGH;
>>>>> +
>>>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
>>>>>> set_cs_timing) && !activate)
>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>> +
>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>> + enable = !enable;
>>>>> +
>>>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
>>>> 1)) {
>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>> + /*
>>>>> + * Historically ACPI has no means of
>>>> the
>>>>> GPIO polarity and
>>>>> + * thus the SPISerialBus() resource
>>>>> defines it on the per-chip
>>>>> + * basis. In order to avoid a chain of
>>>>> negations, the GPIO
>>>>> + * polarity is considered being Active
>>>>> High. Even for the cases
>>>>> + * when _DSD() is involved (in the
>>>>> updated versions of ACPI)
>>>>> + * the GPIO CS polarity must be
>>>> defined
>>>>> Active High to avoid
>>>>> + * ambiguity. That's why we use
>>>> enable,
>>>>> that takes SPI_CS_HIGH
>>>>> + * into account.
>>>>> + */
>>>>> + if (has_acpi_companion(&spi->dev)) {
>>>>> + for (idx = 0; idx <
>>>>> SPI_CS_CNT_MAX; idx++)
>>>>> +
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>> +
>>>>> !enable);
>>>>> + } else {
>>>>> + for (idx = 0; idx <
>>>>> SPI_CS_CNT_MAX; idx++)
>>>>> + /* Polarity handled by
>>>>> GPIO library */
>>>>> +
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>> +
>>>>> activate);
>>>>> + }
>>>>> + }
>>>>> + /* Some SPI masters need both GPIO CS &
>>>>> slave_select */
>>>>> + if ((spi->controller->flags &
>>>>> SPI_MASTER_GPIO_SS) &&
>>>>> + spi->controller->set_cs)
>>>>> + spi->controller->set_cs(spi, !enable);
>>>>> + } else if (spi->controller->set_cs) {
>>>>> + spi->controller->set_cs(spi, !enable);
>>>>> + }
>>>>>
>>>>> - if (spi_get_csgpiod(spi, 0)) {
>>>>> - if (!(spi->mode & SPI_NO_CS)) {
>>>>> - /*
>>>>> - * Historically ACPI has no means of the GPIO
>>>>> polarity and
>>>>> - * thus the SPISerialBus() resource defines it
>>>> on
>>>>> the per-chip
>>>>> - * basis. In order to avoid a chain of
>>>> negations,
>>>>> the GPIO
>>>>> - * polarity is considered being Active High.
>>>> Even
>>>>> for the cases
>>>>> - * when _DSD() is involved (in the updated
>>>>> versions of ACPI)
>>>>> - * the GPIO CS polarity must be defined Active
>>>>> High to avoid
>>>>> - * ambiguity. That's why we use enable, that
>>>>> takes SPI_CS_HIGH
>>>>> - * into account.
>>>>> - */
>>>>> - if (has_acpi_companion(&spi->dev))
>>>>> -
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
>>>> ||
>>>>> + !spi->controller->set_cs_timing) {
>>>>> + if (activate)
>>>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>>>> else
>>>>> - /* Polarity handled by GPIO library */
>>>>> -
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>> NULL);
>>>>> }
>>>>> - /* Some SPI masters need both GPIO CS & slave_select
>>>>> */
>>>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
>>>>> - spi->controller->set_cs)
>>>>> + } else {
>>>>> + /*
>>>>> + * Avoid calling into the driver (or doing delays) if
>>>> the
>>>>> chip select
>>>>> + * isn't actually changing from the last time this was
>>>>> called.
>>>>> + */
>>>>> + if (!force && ((enable && spi->controller->last_cs ==
>>>>> + spi_get_chipselect(spi, cs_num)) ||
>>>>> + (!enable && spi->controller->last_cs
>>>> !=
>>>>> + spi_get_chipselect(spi, cs_num))) &&
>>>>> + (spi->controller->last_cs_mode_high ==
>>>>> + (spi->mode & SPI_CS_HIGH)))
>>>>> + return;
>>>>> +
>>>>> + trace_spi_set_cs(spi, activate);
>>>>> +
>>>>> + spi->controller->last_cs = enable ?
>>>>> spi_get_chipselect(spi, cs_num) : -1;
>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>> SPI_CS_HIGH;
>>>>> +
>>>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>> set_cs_timing) && !activate)
>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>> +
>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>> + enable = !enable;
>>>>> +
>>>>> + if (spi_get_csgpiod(spi, cs_num)) {
>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>> + /*
>>>>> + * Historically ACPI has no means of
>>>> the
>>>>> GPIO polarity and
>>>>> + * thus the SPISerialBus() resource
>>>>> defines it on the per-chip
>>>>> + * basis. In order to avoid a chain of
>>>>> negations, the GPIO
>>>>> + * polarity is considered being Active
>>>>> High. Even for the cases
>>>>> + * when _DSD() is involved (in the
>>>>> updated versions of ACPI)
>>>>> + * the GPIO CS polarity must be
>>>> defined
>>>>> Active High to avoid
>>>>> + * ambiguity. That's why we use
>>>> enable,
>>>>> that takes SPI_CS_HIGH
>>>>> + * into account.
>>>>> + */
>>>>> + if (has_acpi_companion(&spi->dev))
>>>>> +
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>> +
>>>>> !enable);
>>>>> + else
>>>>> + /* Polarity handled by GPIO
>>>>> library */
>>>>> +
>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>> +
>>>>> activate);
>>>>> + }
>>>>> + /* Some SPI masters need both GPIO CS &
>>>>> slave_select */
>>>>> + if ((spi->controller->flags &
>>>>> SPI_MASTER_GPIO_SS) &&
>>>>> + spi->controller->set_cs)
>>>>> + spi->controller->set_cs(spi, !enable);
>>>>> + } else if (spi->controller->set_cs) {
>>>>> spi->controller->set_cs(spi, !enable);
>>>>> - } else if (spi->controller->set_cs) {
>>>>> - spi->controller->set_cs(spi, !enable);
>>>>> - }
>>>>> + }
>>>>>
>>>>> - if (spi_get_csgpiod(spi, 0) ||
>>>> !spi->controller->set_cs_timing) {
>>>>> - if (activate)
>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>>>> - else
>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>> set_cs_timing) {
>>>>> + if (activate)
>>>>> + spi_delay_exec(&spi->cs_setup, NULL);
>>>>> + else
>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>> NULL);
>>>>> + }
>>>>> }
>>>>> }
>>>>>
>>>>> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
>>>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
>>>>> *ctlr, struct
>>>> spi_device
>>>>> *spi,
>>>>> struct device_node *nc)
>>>>> {
>>>>> - u32 value;
>>>>> - int rc;
>>>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
>>>>> + int rc, idx;
>>>>>
>>>>> /* Mode (clock phase/polarity/etc.) */
>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13 +2399,21
>>>> @@
>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
>>>>> spi_device *spi,
>>>>> }
>>>>>
>>>>> /* Device address */
>>>>> - rc = of_property_read_u32(nc, "reg", &value);
>>>>> - if (rc) {
>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0], 1,
>>>>> + SPI_CS_CNT_MAX);
>>>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>>>> (%d)\n",
>>>>> nc, rc);
>>>>> return rc;
>>>>> + } else if ((of_property_read_bool(nc, "parallel-memories")) &&
>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
>>>> multi
>>>>> CS\n");
>>>>> + return -EINVAL;
>>>>> }
>>>>> - spi_set_chipselect(spi, 0, value);
>>>>> + for (idx = 0; idx < rc; idx++)
>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>>>> + /* By default set the spi->cs_index_mask as 1 */
>>>>> + spi->cs_index_mask = 0x01;
>>>>>
>>>>> /* Device speed */
>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value)) @@
>>>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device *spi,
>>>>> struct spi_message *message)
>>>>> * cs_change is set for each transfer.
>>>>> */
>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>>>> SPI_CS_WORD) ||
>>>>> - spi_get_csgpiod(spi, 0))) {
>>>>> + spi_get_csgpiod(spi, 0) ||
>>>>> + spi_get_csgpiod(spi, 1))) {
>>>>> size_t maxsize;
>>>>> int ret;
>>>>>
>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h index
>>>>> 873ced6ae4ca..6453b246e0af 100644
>>>>> --- a/include/linux/spi/spi.h
>>>>> +++ b/include/linux/spi/spi.h
>>>>> @@ -19,6 +19,11 @@
>>>>> #include <linux/acpi.h>
>>>>> #include <linux/u64_stats_sync.h>
>>>>>
>>>>> +/* Max no. of CS supported per spi device */ #define SPI_CS_CNT_MAX
>>>>> +2
>>>>> +
>>>>> +/* chip select mask */
>>>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
>>>>> struct dma_chan;
>>>>> struct software_node;
>>>>> struct ptp_system_timestamp;
>>>>> @@ -166,6 +171,7 @@ extern void
>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>> * deasserted. If @cs_change_delay is used from @spi_transfer,
>>>>> then the
>>>>> * two delays will be added up.
>>>>> * @pcpu_statistics: statistics for the spi_device
>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>>>> chipselect array
>>>>> *
>>>>> * A @spi_device is used to interchange data between an SPI slave
>>>>> * (usually a discrete chip) and CPU memory.
>>>>> @@ -181,7 +187,7 @@ struct spi_device {
>>>>> struct spi_controller *controller;
>>>>> struct spi_controller *master; /* Compatibility layer
>>>> */
>>>>> u32 max_speed_hz;
>>>>> - u8 chip_select;
>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>>>> u8 bits_per_word;
>>>>> bool rt;
>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>>>> @@ -202,7 +208,7 @@ struct spi_device {
>>>>> void *controller_data;
>>>>> char modalias[SPI_NAME_SIZE];
>>>>> const char *driver_override;
>>>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
>>>> desc
>>>>> */
>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
>>>> Chip
>>>>> select gpio desc */
>>>>> struct spi_delay word_delay; /* Inter-word delay */
>>>>> /* CS delays */
>>>>> struct spi_delay cs_setup;
>>>>> @@ -212,6 +218,13 @@ struct spi_device {
>>>>> /* The statistics */
>>>>> struct spi_statistics __percpu *pcpu_statistics;
>>>>>
>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
>>>> from
>>>>> + * the chipselect array.When the controller is capable to
>>>> handle
>>>>> + * multiple chip selects & memories are connected in parallel
>>>>> + * then more than one bit need to be set in cs_index_mask.
>>>>> + */
>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>>>> +
>>>>> /*
>>>>> * likely need more hooks for more protocol options affecting how
>>>>> * the controller talks to each chip, like:
>>>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
>>>>> struct spi_device *spi)
>>>>>
>>>>> static inline u8 spi_get_chipselect(const struct spi_device *spi,
>>>> u8 idx)
>>>>> {
>>>>> - return spi->chip_select;
>>>>> + return spi->chip_select[idx];
>>>>> }
>>>>>
>>>>> static inline void spi_set_chipselect(struct spi_device *spi, u8
>>>> idx, u8
>>>>> chipselect)
>>>>> {
>>>>> - spi->chip_select = chipselect;
>>>>> + spi->chip_select[idx] = chipselect;
>>>>> }
>>>>>
>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>>>> spi_device
>>>>> *spi, u8 idx)
>>>>> {
>>>>> - return spi->cs_gpiod;
>>>>> + return spi->cs_gpiod[idx];
>>>>> }
>>>>>
>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8 idx,
>>>> struct
>>>>> gpio_desc *csgpiod)
>>>>> {
>>>>> - spi->cs_gpiod = csgpiod;
>>>>> + spi->cs_gpiod[idx] = csgpiod;
>>>>> }
>>>>>
>>>>> /**
>>>>> @@ -388,6 +401,8 @@ extern struct spi_device
>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>>> exclusive use
>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
>>>> assert/de-assert
>>>>> + * more than one chip select at once.
>>>>> * @setup: updates the device mode and clocking records used by a
>>>>> * device's SPI controller; protocol code may call this. This
>>>>> * must fail if an unrecognized or unsupported mode is requested.
>>>>> @@ -554,6 +569,11 @@ struct spi_controller {
>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
>>>>> */
>>>>>
>>>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
>>>> select
>>>>> slave */
>>>>> + /*
>>>>> + * The spi-controller has multi chip select capability and can
>>>>> + * assert/de-assert more than one chip select at once.
>>>>> + */
>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
>>>>>
>>>>> /* Flag indicating if the allocation of this struct is devres-
>>>>> managed */
>>>>> bool devm_allocated;
>>>>> --
>>>>> 2.17.1
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Tuesday, April 25, 2023 5:50 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
> in SPI core
>
> Hi,
>
> On 20/04/2023 10:04, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Wednesday, April 12, 2023 8:33 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]
> >> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal
> <[email protected]>;
> >> [email protected]; [email protected];
> >> [email protected]; [email protected]
> >> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >> support in SPI core
> >>
> >> Hi,
> >>
> >> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
> >>> Hello Stefan,
> >>>
> >>>> -----Original Message-----
> >>>> From: Stefan Binding <[email protected]>
> >>>> Sent: Thursday, April 6, 2023 7:14 PM
> >>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]
> >>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
> >>>> linux- [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; Simek, Michal
> >> <[email protected]>;
> >>>> [email protected]; [email protected];
> >>>> [email protected]; [email protected]
> >>>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >>>> support in SPI core
> >>>>
> >>>> Hi,
> >>>>
> >>>>> -----Original Message-----
> >>>>> From: Amit Kumar Mahapatra <[email protected]>
> >>>>> Sent: Thursday, April 6, 2023 7:54 AM
> >>>>> To: [email protected]; [email protected];
> >>>>> [email protected]; [email protected]; [email protected];
> >>>>> [email protected]; [email protected]
> >>>>> Cc: [email protected]; [email protected]; linux-
> >>>>> [email protected]; [email protected]; linux-
> >>>>> [email protected]; [email protected];
> >>>>> [email protected]; [email protected];
> >>>>> [email protected]; [email protected];
> >>>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
> >>>>> [email protected]>
> >>>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >>>> support
> >>>>> in SPI core
> >>>>>
> >>>>> For supporting multiple CS the SPI device need to be aware of all
> >>>> the CS
> >>>>> values. So, the "chip_select" member in the spi_device structure
> >>>>> is
> >>>> now
> >>>>> an
> >>>>> array that holds all the CS values.
> >>>>>
> >>>>> spi_device structure now has a "cs_index_mask" member. This acts
> >>>>> as
> >>>> an
> >>>>> index to the chip_select array. If nth bit of spi->cs_index_mask
> >>>>> is
> >>>> set
> >>>>> then the driver would assert spi->chip_select[n].
> >>>>>
> >>>>> In parallel mode all the chip selects are asserted/de-asserted
> >>>>> simultaneously and each byte of data is stored in both devices,
> >>>>> the
> >>>> even
> >>>>> bits in one, the odd bits in the other. The split is automatically
> >>>> handled
> >>>>> by the GQSPI controller. The GQSPI controller supports a maximum
> >>>>> of two flashes connected in parallel mode. A
> >>>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
> >>>>> controntroller flags, through
> >>>>> ctlr->flags the spi
> >>>> core
> >>>>> will make sure that the controller is capable of handling multiple
> >>>> chip
> >>>>> selects at once.
> >>>>>
> >>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>>>> spi_device structure is now an array that holds the gpio
> >>>>> descriptor for each chipselect.
> >>>>>
> >>>>> Multi CS support using GPIO is not tested due to unavailability of
> >>>>> necessary hardware setup.
> >>>>>
> >>>>> Multi CS configuration with one native CS and one GPIO CS is not
> >>>>> supported as this configuration could not be tested due to
> >>>>> unavailability of necessary hardware setup.
> >>>> I've tested this chain on a released laptop (HP EliteBook 840 G9)
> >>>> which uses SPI to interface to 2 amps, one amp uses a native CS and
> >>>> the other uses a GPIO CS, and I noticed that when using this chain,
> >>>> the second amp no longer works.
> >>> Thank you for testing this patch series on GPIO CS setup. As I don't
> >>> have a GPIO CS setup, is it possible for you debug the failure and
> >>> share more details/logs where the problem is?
> >>>
> >>> Regards,
> >>> Amit
> >> We are willing and able to debug this failure and share the failure logs.
> >> The first issue that I see is a kernel crash when trying to set the GPIO CS:
> >>
> >> [ 2.951658] general protection fault, probably for non-canonical
> >> address
> >> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771] CPU:
> 9
> >> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30 [
> >> 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
> >> [ 2.951882] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
> >> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85
> >> ff
> >> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff
> >> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
> >> ee 4c [ 2.952043]
> >> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
> >> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> >> 0000000000000000
> >> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> >> dead000000000122
> >> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> >> ffffc008c0deb868
> >> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> >> dead000000000122
> >> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
> >> 0000000000000000
> >> [ 2.952299] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
> >> knlGS:0000000000000000
> >> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >> 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> >> 0000000000770ee0
> >> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >> 0000000000000000
> >> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >> 0000000000000400
> >> [ 2.952533] PKRU: 55555554
> >> [ 2.952561] Call Trace:
> >> [ 2.952579] <TASK>
> >> [ 2.952598] spi_set_cs+0x257/0x4a0 [ 2.952630]
> >> spi_setup+0x1a2/0x500 [ 2.952667] __spi_add_device+0x88/0x160 [
> >> 2.952710] spi_add_device+0x60/0x90 [ 2.952738]
> >> smi_spi_probe+0x178/0x370 [serial_multi_instantiate] [ 2.952792]
> >> smi_probe+0xcf/0x110 [serial_multi_instantiate] [ 2.952854]
> >> platform_probe+0x42/0xb0 [ 2.952885] really_probe+0x1b2/0x420 [
> >> 2.952914] __driver_probe_device+0x7e/0x180 [ 2.952947]
> >> driver_probe_device+0x23/0xa0 [ 2.952993]
> >> __driver_attach+0xe4/0x1e0 [ 2.953021] ?
> >> __pfx___driver_attach+0x10/0x10
> >> [ 2.953061] bus_for_each_dev+0x7a/0xd0 [ 2.953088]
> >> driver_attach+0x1e/0x30 [ 2.953123] bus_add_driver+0x11c/0x220 [
> >> 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
> >> __pfx_init_module+0x10/0x10 [serial_multi_instantiate] [ 2.953221]
> >> __platform_driver_register+0x1e/0x30
> >> [ 2.953251] smi_driver_init+0x1c/0xff0 [serial_multi_instantiate]
> >> [ 2.953310] do_one_initcall+0x46/0x220 [ 2.953339] ?
> >> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220 [
> >> 2.953411] load_module+0x223c/0x2460 [ 2.953450]
> >> __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
> >> __do_sys_finit_module+0xc8/0x140
> >> [ 2.953510] __x64_sys_finit_module+0x18/0x20 [ 2.953538]
> >> do_syscall_64+0x38/0x90 [ 2.953574]
> >> entry_SYSCALL_64_after_hwframe+0x72/0xdc
> >> [ 2.953606] RIP: 0033:0x7f7fa5d7476d [ 2.953639] Code: 00 c3 66
> >> 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
> >> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08
> >> 0f
> >> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
> >> 48 [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246
> ORIG_RAX:
> >> 0000000000000139
> >> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
> >> 00007f7fa5d7476d
> >> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
> >> 0000000000000006
> >> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
> >> 0000000000000000
> >> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
> >> 00007f7fa5c54ded
> >> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
> >> 000055d648654ab0
> >> [ 2.967668] resource: resource sanity check: requesting [mem
> >> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp
> >> 00:04 [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [
> >> 2.971615] caller
> >> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [
> >> 2.975014] Modules linked in: igen6_edac(+) fjes(-)
> >> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
> >> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel
> >> acpi_tad sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp
> >> parport drm ramoops reed_solomon efi_pstore ip_tables x_tables
> >> autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core nvme
> intel_lpss_pci
> >> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64
> >> nvme_core i2c_smbus virt_dma xhci_pci_renesas video wmi
> >> pinctrl_tigerlake [ 2.987901] ---[ end trace 0000000000000000 ]---
> [ 3.157030] RIP:
> >> 0010:gpiod_set_value_cansleep+0x21/0xa0
> >> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85
> >> ff
> >> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff
> >> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
> >> ee 4c [ 3.161461]
> >> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
> >> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> >> 0000000000000000
> >> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> >> dead000000000122
> >> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> >> ffffc008c0deb868
> >> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> >> dead000000000122
> >> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
> >> 0000000000000000
> >> [ 3.175335] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
> >> knlGS:0000000000000000
> >> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >> 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> >> 0000000000770ee0
> >> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >> 0000000000000000
> >> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >> 0000000000000400
> >> [ 3.188647] PKRU: 55555554
> > Thank you for sharing the logs.
> > As per our analysis the spi->cs_gpiod[0] is getting messed up while
> > setting it in __spi_add_device( ).
> > Is it possible for you to do the following changes on top of this
> > patch series & re-run your test.
> >
> > After applying this patch series, in drivers/spi/spi.c file replace
> > the following code snippet in __spi_add_device( ) function defination.
> >
> > if (ctlr->cs_gpiods) {
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > spi_set_csgpiod(spi, idx,
> > ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
> >
> > with the below code snippet
> >
> > if (ctlr->cs_gpiods) {
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
> > spi_set_csgpiod(spi, idx, ctlr-
> >cs_gpiods[spi_get_chipselect(spi, idx)]);
> > }
> > }
> >
> > then re-run your test.
> >
> > Regards,
> > Amit
>
> I'm still seeing a crash on probe:
>
> [ 3.265683] BUG: unable to handle page fault for address:
> 00000000fffedfdd
> [ 3.265744] #PF: supervisor read access in kernel mode [ 3.265781] #PF:
> error_code(0x0000) - not-present page [ 3.265817] PGD 0 P4D 0
> [ 3.265840] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 3.265865] CPU: 4 PID:
> 385 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #32 [ 3.265910]
> Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021 [ 3.265956]
> RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
> [ 3.266007] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
> [ 3.266092] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [ 3.266121]
> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
> cccccccccccccccd
> [ 3.266156] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
> ffff9c8d4a5f6d40
> [ 3.266192] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
> 0000000000000000
> [ 3.266228] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
> 00000000fffedf7d
> [ 3.266264] R13: 0000000000000000 R14: 0000000000000001 R15:
> 0000000000000001
> [ 3.266299] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
> knlGS:0000000000000000
> [ 3.266358] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 3.266388] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
> 0000000000770ee0
> [ 3.266422] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> [ 3.266457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> 0000000000000400
> [ 3.266490] PKRU: 55555554
> [ 3.266513] Call Trace:
> [ 3.266530] <TASK>
> [ 3.266546] gpiod_set_value_nocheck+0x5b/0x70
> [ 3.266583] gpiod_set_value_cansleep+0x3e/0xa0
> [ 3.266609] spi_set_cs+0x257/0x4a0
> [ 3.266634] spi_transfer_one_message+0x49/0x740
> [ 3.266672] __spi_pump_transfer_message+0x29b/0x620
> [ 3.266712] __spi_sync+0x26f/0x3b0
> [ 3.266735] spi_write_then_read+0x157/0x210 [ 3.266771] ?
> psi_group_change+0x175/0x3b0 [ 3.266802] regmap_spi_read+0xe/0x20
> [ 3.266826] _regmap_raw_read+0xe1/0x210
> [ 3.266861] _regmap_bus_read+0x3a/0x70
> [ 3.266887] _regmap_read+0x66/0x140
> [ 3.266918] regmap_read+0x3f/0x70
> [ 3.266957] cs35l41_hda_probe+0x553/0xc10 [snd_hda_scodec_cs35l41]
> [ 3.267027] cs35l41_hda_spi_probe+0x62/0x80
> [snd_hda_scodec_cs35l41_spi] [ 3.267096] spi_probe+0x55/0x90
> [ 3.267145] really_probe+0x1b2/0x420
> [ 3.267184] __driver_probe_device+0x7e/0x180
> [ 3.267227] driver_probe_device+0x23/0xa0
> [ 3.267287] __driver_attach+0xe4/0x1e0 [ 3.267326] ?
> __pfx___driver_attach+0x10/0x10
> [ 3.267381] bus_for_each_dev+0x7a/0xd0
> [ 3.267406] driver_attach+0x1e/0x30
> [ 3.267437] bus_add_driver+0x11c/0x220
> [ 3.267461] driver_register+0x64/0x130 [ 3.267483] ?
> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
> [ 3.267525] __spi_register_driver+0xa1/0xd0 [ 3.270712] ?
> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
> [ 3.273446] cs35l41_spi_driver_init+0x1c/0xff0
> [snd_hda_scodec_cs35l41_spi]
> [ 3.275119] do_one_initcall+0x46/0x220 [ 3.276828] ?
> kmalloc_trace+0x2a/0xa0 [ 3.279290] do_init_module+0x52/0x220
> [ 3.283593] load_module+0x223c/0x2460
> [ 3.283602] __do_sys_finit_module+0xc8/0x140 [ 3.287883] ?
> __do_sys_finit_module+0xc8/0x140
> [ 3.287907] __x64_sys_finit_module+0x18/0x20
> [ 3.293156] do_syscall_64+0x38/0x90
> [ 3.298937] entry_SYSCALL_64_after_hwframe+0x72/0xdc
> [ 3.298945] RIP: 0033:0x7f98d06f776d
> [ 3.319574] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
> [ 3.319579] RSP: 002b:00007ffd988f7a08 EFLAGS: 00000246 ORIG_RAX:
> 0000000000000139
> [ 3.319585] RAX: ffffffffffffffda RBX: 000055af06a7d030 RCX:
> 00007f98d06f776d
> [ 3.319589] RDX: 0000000000000000 RSI: 00007f98d05d7ded RDI:
> 0000000000000013
> [ 3.329520] RBP: 0000000000020000 R08: 0000000000000000 R09:
> 0000000000000000
> [ 3.329523] R10: 0000000000000013 R11: 0000000000000246 R12:
> 00007f98d05d7ded
> [ 3.329525] R13: 0000000000000000 R14: 000055af06cdd040 R15:
> 000055af06a7d030
> [ 3.329531] </TASK>
> [ 3.329533] Modules linked in: snd_hda_intel(+) ttm snd_intel_dspcfg btusb
> rapl snd_seq_midi snd_intel_sdw_acpi libarc4 intel_cstate binfmt_misc
> uvcvideo(+) snd_seq_midi_event btrtl
> snd_hda_scodec_cs35l41_spi(+) snd_hda_codec drm_display_helper
> cdc_ncm(+) videobuf2_vmalloc snd_rawmidi btbcm uvc cdc_ether cec btintel
> videobuf2_memops snd_hda_scodec_cs35l41_i2c snd_hda_core
> videobuf2_v4l2 uas usbnet rc_core snd_hwdep btmtk
> snd_hda_scodec_cs35l41 input_leds mii wmi_bmof videodev snd_seq
> processor_thermal_device_pci bluetooth iwlwifi drm_kms_helper snd_pcm
> snd_hda_cs_dsp_ctls processor_thermal_device mei_me
> videobuf2_common snd_seq_device i2c_algo_bit cs_dsp
> processor_thermal_rfim ecdh_generic usb_storage serio_raw mc
> syscopyarea ecc processor_thermal_mbox ucsi_acpi snd_soc_cs35l41_lib
> 8250_dw mei snd_timer cfg80211 sysfillrect typec_ucsi
> processor_thermal_rapl igen6_edac sysimgblt intel_rapl_common typec snd
> soundcore int3403_thermal int340x_thermal_zone serial_multi_instantiate
> int3400_thermal intel_hid acpi_thermal_rel [ 3.338475] sparse_keymap
> acpi_tad acpi_pad mac_hid sch_fq_codel msr parport_pc ppdev lp parport
> drm ramoops reed_solomon efi_pstore ip_tables x_tables autofs4
> spi_pxa2xx_platform dw_dmac dw_dmac_core intel_lpss_pci nvme
> intel_lpss i2c_i801 idma64 crc32_pclmul thunderbolt i2c_smbus nvme_core
> xhci_pci virt_dma xhci_pci_renesas video wmi pinctrl_tigerlake [ 3.338514]
> CR2: 00000000fffedfdd [ 3.338517] ---[ end trace 0000000000000000 ]---
> [ 3.504965] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
> [ 3.504973] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
> [ 3.504975] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [ 3.504978]
> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
> cccccccccccccccd
> [ 3.504979] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
> ffff9c8d4a5f6d40
> [ 3.504980] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
> 0000000000000000
> [ 3.504982] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
> 00000000fffedf7d
> [ 3.504983] R13: 0000000000000000 R14: 0000000000000001 R15:
> 0000000000000001
> [ 3.504984] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
> knlGS:0000000000000000
> [ 3.504986] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
> [ 3.504988] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
> 0000000000770ee0
> [ 3.504989] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> 0000000000000000
> [ 3.504990] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> 0000000000000400
> [ 3.504992] PKRU: 55555554
>
> Thanks,
> Stefan
Thanks for the logs.
Could you please confirm that your test case was passing with
https://github.com/torvalds/linux/commit/303feb3cc06ac0665d0ee9c1414941200e60e8a3 patch
but it is failing with the current patch series ?
Regarding the failure
The logs suggest that we are trying to access an invalid pointer while
calling the gpiod_set_value_cansleep( ) API.
This could be possible if the cs_num is corrupted and we are trying to
access an invalid spi->cs_gpiod[ ].
To confirm the same could you please do the following changes in the
code and re-test.
After applying this patch series, in drivers/spi/spi.c file replace the
following code snippet in __spi_add_device( ) function definition.
if (ctlr->cs_gpiods) {
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
}
with the below code snippet
if (ctlr->cs_gpiods) {
for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
if (!(idx != 0 && !spi_get_chipselect(spi, idx))) {
printk("%s( ) [%d] cs[%d] = [%d]\n", __func__, __LINE__, idx, spi_get_chipselect(spi, idx));
spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
}
}
}
And at the start of spi_set_cs( ) function in drivers/spi/spi.c file add
the following print statements.
printk("%s( ) [%d] spi->cs_index_mask == [%d]\n", __func__, __LINE__, spi->cs_index_mask);
printk("%s( ) [%d] cs_num == [%d]\n", __func__, __LINE__, cs_num);
Thanks,
Amit
>
> >> Thanks,
> >>
> >> Stefan
> >>
> >>>> Thanks,
> >>>> Stefan Binding
> >>>>
> >>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> >>>> [email protected]>
> >>>>> ---
> >>>>> drivers/spi/spi.c | 226
> >>>> ++++++++++++++++++++++++++++------------
> >>>>> include/linux/spi/spi.h | 32 ++++--
> >>>>> 2 files changed, 183 insertions(+), 75 deletions(-)
> >>>>>
> >>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>>>> 9036d7a50674..04d7322170c4 100644
> >>>>> --- a/drivers/spi/spi.c
> >>>>> +++ b/drivers/spi/spi.c
> >>>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
> >>>>> void *data) {
> >>>>> struct spi_device *spi = to_spi_device(dev);
> >>>>> struct spi_device *new_spi = data;
> >>>>> + int idx, nw_idx;
> >>>>>
> >>>>> - if (spi->controller == new_spi->controller &&
> >>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
> >>>> 0))
> >>>>> - return -EBUSY;
> >>>>> + if (spi->controller == new_spi->controller) {
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >>>>> nw_idx++) {
> >>>>> + if ((idx != 0 &&
> >>>> !spi_get_chipselect(spi,
> >>>>> idx)) ||
> >>>>> + (nw_idx != 0 &&
> >>>>> !spi_get_chipselect(spi, nw_idx))) {
> >>>>> + continue;
> >>>>> + } else if (spi_get_chipselect(spi,
> >>>> idx) ==
> >>>>> + spi_get_chipselect(new_spi,
> >>>> nw_idx))
> >>>>> {
> >>>>> + dev_err(dev,
> >>>>> + "chipselect %d
> already
> >>>>> in use\n",
> >>>>> +
> >>>>> spi_get_chipselect(new_spi, nw_idx));
> >>>>> + return -EBUSY;
> >>>>> + }
> >>>>> + }
> >>>>> + }
> >>>>> + }
> >>>>> return 0;
> >>>>> }
> >>>>>
> >>>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
> >>>>> *spi)
> >>>>> {
> >>>>> struct spi_controller *ctlr = spi->controller;
> >>>>> struct device *dev = ctlr->dev.parent;
> >>>>> - int status;
> >>>>> + int status, idx;
> >>>>>
> >>>>> /*
> >>>>> * We need to make sure there's no other device with this
> @@
> >>>>> -638,8
> >>>>> +652,6 @@ static int __spi_add_device(struct spi_device
> >>>>> *spi)
> >>>>> */
> >>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> >>>> spi_dev_check);
> >>>>> if (status) {
> >>>>> - dev_err(dev, "chipselect %d already in use\n",
> >>>>> - spi_get_chipselect(spi, 0));
> >>>>> return status;
> >>>>> }
> >>>>>
> >>>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
> >>>>> *spi)
> >>>>> return -ENODEV;
> >>>>> }
> >>>>>
> >>>>> - if (ctlr->cs_gpiods)
> >>>>> - spi_set_csgpiod(spi, 0, ctlr-
> >>>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
> >>>>> + if (ctlr->cs_gpiods) {
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>> + spi_set_csgpiod(spi, idx, ctlr-
> >>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
> >>>>> + }
> >>>>>
> >>>>> /*
> >>>>> * Drivers may modify this initial i/o setup, but will @@
> >>>>> -690,13
> >>>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
> >>>>> struct spi_controller *ctlr = spi->controller;
> >>>>> struct device *dev = ctlr->dev.parent;
> >>>>> - int status;
> >>>>> + int status, idx;
> >>>>>
> >>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>> - dev_err(dev, "cs%d >= max %d\n",
> >>>>> spi_get_chipselect(spi, 0),
> >>>>> - ctlr->num_chipselect);
> >>>>> - return -EINVAL;
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>> + if (spi_get_chipselect(spi, idx) >=
> >>>> ctlr->num_chipselect) {
> >>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>>> spi_get_chipselect(spi, idx),
> >>>>> + ctlr->num_chipselect);
> >>>>> + return -EINVAL;
> >>>>> + }
> >>>>> }
> >>>>>
> >>>>> /* Set the bus ID string */
> >>>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
> >>>>> spi_device *spi) {
> >>>>> struct spi_controller *ctlr = spi->controller;
> >>>>> struct device *dev = ctlr->dev.parent;
> >>>>> + int idx;
> >>>>>
> >>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>> - dev_err(dev, "cs%d >= max %d\n",
> >>>>> spi_get_chipselect(spi, 0),
> >>>>> - ctlr->num_chipselect);
> >>>>> - return -EINVAL;
> >>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>> + if (spi_get_chipselect(spi, idx) >=
> >>>> ctlr->num_chipselect) {
> >>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>>> spi_get_chipselect(spi, idx),
> >>>>> + ctlr->num_chipselect);
> >>>>> + return -EINVAL;
> >>>>> + }
> >>>>> }
> >>>>>
> >>>>> /* Set the bus ID string */
> >>>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
> >>>>> spi_controller *ctlr, struct spi_message *mes static void
> >>>>> spi_set_cs(struct spi_device *spi, bool enable, bool
> >>>> force)
> >>>>> {
> >>>>> bool activate = enable;
> >>>>> + u32 cs_num = __ffs(spi->cs_index_mask);
> >>>>> + int idx;
> >>>>>
> >>>>> /*
> >>>>> - * Avoid calling into the driver (or doing delays) if the chip
> >>>> select
> >>>>> - * isn't actually changing from the last time this was called.
> >>>>> + * In parallel mode all the chip selects are
> >>>> asserted/de-asserted
> >>>>> + * at once
> >>>>> */
> >>>>> - if (!force && ((enable && spi->controller->last_cs ==
> >>>>> spi_get_chipselect(spi, 0)) ||
> >>>>> - (!enable && spi->controller->last_cs !=
> >>>>> spi_get_chipselect(spi, 0))) &&
> >>>>> - (spi->controller->last_cs_mode_high == (spi->mode &
> >>>>> SPI_CS_HIGH)))
> >>>>> - return;
> >>>>> -
> >>>>> - trace_spi_set_cs(spi, activate);
> >>>>> -
> >>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
> >>>> : -1;
> >>>>> - spi->controller->last_cs_mode_high = spi->mode &
> >>>>> SPI_CS_HIGH;
> >>>>> -
> >>>>> - if ((spi_get_csgpiod(spi, 0) ||
> >>>> !spi->controller->set_cs_timing)
> >>>>> && !activate)
> >>>>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>>>> -
> >>>>> - if (spi->mode & SPI_CS_HIGH)
> >>>>> - enable = !enable;
> >>>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
> >>>>> SPI_PARALLEL_CS_MASK) {
> >>>>> + spi->controller->last_cs_mode_high = spi->mode &
> >>>>> SPI_CS_HIGH;
> >>>>> +
> >>>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> >>>>>> set_cs_timing) && !activate)
> >>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>> +
> >>>>> + if (spi->mode & SPI_CS_HIGH)
> >>>>> + enable = !enable;
> >>>>> +
> >>>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
> >>>> 1)) {
> >>>>> + if (!(spi->mode & SPI_NO_CS)) {
> >>>>> + /*
> >>>>> + * Historically ACPI has no means of
> >>>> the
> >>>>> GPIO polarity and
> >>>>> + * thus the SPISerialBus() resource
> >>>>> defines it on the per-chip
> >>>>> + * basis. In order to avoid a chain of
> >>>>> negations, the GPIO
> >>>>> + * polarity is considered being Active
> >>>>> High. Even for the cases
> >>>>> + * when _DSD() is involved (in the
> >>>>> updated versions of ACPI)
> >>>>> + * the GPIO CS polarity must be
> >>>> defined
> >>>>> Active High to avoid
> >>>>> + * ambiguity. That's why we use
> >>>> enable,
> >>>>> that takes SPI_CS_HIGH
> >>>>> + * into account.
> >>>>> + */
> >>>>> + if (has_acpi_companion(&spi->dev)) {
> >>>>> + for (idx = 0; idx <
> >>>>> SPI_CS_CNT_MAX; idx++)
> >>>>> +
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>> +
> >>>>> !enable);
> >>>>> + } else {
> >>>>> + for (idx = 0; idx <
> >>>>> SPI_CS_CNT_MAX; idx++)
> >>>>> + /* Polarity handled by
> >>>>> GPIO library */
> >>>>> +
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>> +
> >>>>> activate);
> >>>>> + }
> >>>>> + }
> >>>>> + /* Some SPI masters need both GPIO CS &
> >>>>> slave_select */
> >>>>> + if ((spi->controller->flags &
> >>>>> SPI_MASTER_GPIO_SS) &&
> >>>>> + spi->controller->set_cs)
> >>>>> + spi->controller->set_cs(spi, !enable);
> >>>>> + } else if (spi->controller->set_cs) {
> >>>>> + spi->controller->set_cs(spi, !enable);
> >>>>> + }
> >>>>>
> >>>>> - if (spi_get_csgpiod(spi, 0)) {
> >>>>> - if (!(spi->mode & SPI_NO_CS)) {
> >>>>> - /*
> >>>>> - * Historically ACPI has no means of the GPIO
> >>>>> polarity and
> >>>>> - * thus the SPISerialBus() resource defines it
> >>>> on
> >>>>> the per-chip
> >>>>> - * basis. In order to avoid a chain of
> >>>> negations,
> >>>>> the GPIO
> >>>>> - * polarity is considered being Active High.
> >>>> Even
> >>>>> for the cases
> >>>>> - * when _DSD() is involved (in the updated
> >>>>> versions of ACPI)
> >>>>> - * the GPIO CS polarity must be defined Active
> >>>>> High to avoid
> >>>>> - * ambiguity. That's why we use enable, that
> >>>>> takes SPI_CS_HIGH
> >>>>> - * into account.
> >>>>> - */
> >>>>> - if (has_acpi_companion(&spi->dev))
> >>>>> -
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
> >>>> ||
> >>>>> + !spi->controller->set_cs_timing) {
> >>>>> + if (activate)
> >>>>> + spi_delay_exec(&spi->cs_setup,
> NULL);
> >>>>> else
> >>>>> - /* Polarity handled by GPIO library */
> >>>>> -
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>>>> + spi_delay_exec(&spi->cs_inactive,
> >>>>> NULL);
> >>>>> }
> >>>>> - /* Some SPI masters need both GPIO CS & slave_select
> >>>>> */
> >>>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
> >>>>> - spi->controller->set_cs)
> >>>>> + } else {
> >>>>> + /*
> >>>>> + * Avoid calling into the driver (or doing delays) if
> >>>> the
> >>>>> chip select
> >>>>> + * isn't actually changing from the last time this was
> >>>>> called.
> >>>>> + */
> >>>>> + if (!force && ((enable && spi->controller->last_cs ==
> >>>>> + spi_get_chipselect(spi, cs_num)) ||
> >>>>> + (!enable && spi->controller->last_cs
> >>>> !=
> >>>>> + spi_get_chipselect(spi, cs_num))) &&
> >>>>> + (spi->controller->last_cs_mode_high ==
> >>>>> + (spi->mode & SPI_CS_HIGH)))
> >>>>> + return;
> >>>>> +
> >>>>> + trace_spi_set_cs(spi, activate);
> >>>>> +
> >>>>> + spi->controller->last_cs = enable ?
> >>>>> spi_get_chipselect(spi, cs_num) : -1;
> >>>>> + spi->controller->last_cs_mode_high = spi->mode &
> >>>>> SPI_CS_HIGH;
> >>>>> +
> >>>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>>>> set_cs_timing) && !activate)
> >>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>> +
> >>>>> + if (spi->mode & SPI_CS_HIGH)
> >>>>> + enable = !enable;
> >>>>> +
> >>>>> + if (spi_get_csgpiod(spi, cs_num)) {
> >>>>> + if (!(spi->mode & SPI_NO_CS)) {
> >>>>> + /*
> >>>>> + * Historically ACPI has no means of
> >>>> the
> >>>>> GPIO polarity and
> >>>>> + * thus the SPISerialBus() resource
> >>>>> defines it on the per-chip
> >>>>> + * basis. In order to avoid a chain of
> >>>>> negations, the GPIO
> >>>>> + * polarity is considered being Active
> >>>>> High. Even for the cases
> >>>>> + * when _DSD() is involved (in the
> >>>>> updated versions of ACPI)
> >>>>> + * the GPIO CS polarity must be
> >>>> defined
> >>>>> Active High to avoid
> >>>>> + * ambiguity. That's why we use
> >>>> enable,
> >>>>> that takes SPI_CS_HIGH
> >>>>> + * into account.
> >>>>> + */
> >>>>> + if (has_acpi_companion(&spi->dev))
> >>>>> +
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>>>> +
> >>>>> !enable);
> >>>>> + else
> >>>>> + /* Polarity handled by GPIO
> >>>>> library */
> >>>>> +
> >>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>>>> +
> >>>>> activate);
> >>>>> + }
> >>>>> + /* Some SPI masters need both GPIO CS &
> >>>>> slave_select */
> >>>>> + if ((spi->controller->flags &
> >>>>> SPI_MASTER_GPIO_SS) &&
> >>>>> + spi->controller->set_cs)
> >>>>> + spi->controller->set_cs(spi, !enable);
> >>>>> + } else if (spi->controller->set_cs) {
> >>>>> spi->controller->set_cs(spi, !enable);
> >>>>> - } else if (spi->controller->set_cs) {
> >>>>> - spi->controller->set_cs(spi, !enable);
> >>>>> - }
> >>>>> + }
> >>>>>
> >>>>> - if (spi_get_csgpiod(spi, 0) ||
> >>>> !spi->controller->set_cs_timing) {
> >>>>> - if (activate)
> >>>>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>>>> - else
> >>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>>>> set_cs_timing) {
> >>>>> + if (activate)
> >>>>> + spi_delay_exec(&spi->cs_setup,
> NULL);
> >>>>> + else
> >>>>> + spi_delay_exec(&spi->cs_inactive,
> >>>>> NULL);
> >>>>> + }
> >>>>> }
> >>>>> }
> >>>>>
> >>>>> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
> >>>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
> >>>>> *ctlr, struct
> >>>> spi_device
> >>>>> *spi,
> >>>>> struct device_node *nc)
> >>>>> {
> >>>>> - u32 value;
> >>>>> - int rc;
> >>>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
> >>>>> + int rc, idx;
> >>>>>
> >>>>> /* Mode (clock phase/polarity/etc.) */
> >>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13
> >>>>> +2399,21
> >>>> @@
> >>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> >>>>> spi_device *spi,
> >>>>> }
> >>>>>
> >>>>> /* Device address */
> >>>>> - rc = of_property_read_u32(nc, "reg", &value);
> >>>>> - if (rc) {
> >>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
> 1,
> >>>>> + SPI_CS_CNT_MAX);
> >>>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
> >>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >>>> (%d)\n",
> >>>>> nc, rc);
> >>>>> return rc;
> >>>>> + } else if ((of_property_read_bool(nc, "parallel-memories"))
> &&
> >>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
> >>>> multi
> >>>>> CS\n");
> >>>>> + return -EINVAL;
> >>>>> }
> >>>>> - spi_set_chipselect(spi, 0, value);
> >>>>> + for (idx = 0; idx < rc; idx++)
> >>>>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>>>> + /* By default set the spi->cs_index_mask as 1 */
> >>>>> + spi->cs_index_mask = 0x01;
> >>>>>
> >>>>> /* Device speed */
> >>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> @@
> >>>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device
> >>>>> *spi, struct spi_message *message)
> >>>>> * cs_change is set for each transfer.
> >>>>> */
> >>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >>>>> SPI_CS_WORD) ||
> >>>>> - spi_get_csgpiod(spi, 0))) {
> >>>>> + spi_get_csgpiod(spi, 0) ||
> >>>>> + spi_get_csgpiod(spi, 1))) {
> >>>>> size_t maxsize;
> >>>>> int ret;
> >>>>>
> >>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> >>>>> index 873ced6ae4ca..6453b246e0af 100644
> >>>>> --- a/include/linux/spi/spi.h
> >>>>> +++ b/include/linux/spi/spi.h
> >>>>> @@ -19,6 +19,11 @@
> >>>>> #include <linux/acpi.h>
> >>>>> #include <linux/u64_stats_sync.h>
> >>>>>
> >>>>> +/* Max no. of CS supported per spi device */ #define
> >>>>> +SPI_CS_CNT_MAX
> >>>>> +2
> >>>>> +
> >>>>> +/* chip select mask */
> >>>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
> >>>>> struct dma_chan;
> >>>>> struct software_node;
> >>>>> struct ptp_system_timestamp;
> >>>>> @@ -166,6 +171,7 @@ extern void
> >>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>> * deasserted. If @cs_change_delay is used from
> @spi_transfer,
> >>>>> then the
> >>>>> * two delays will be added up.
> >>>>> * @pcpu_statistics: statistics for the spi_device
> >>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>>>> chipselect array
> >>>>> *
> >>>>> * A @spi_device is used to interchange data between an SPI slave
> >>>>> * (usually a discrete chip) and CPU memory.
> >>>>> @@ -181,7 +187,7 @@ struct spi_device {
> >>>>> struct spi_controller *controller;
> >>>>> struct spi_controller *master; /* Compatibility layer
> >>>> */
> >>>>> u32 max_speed_hz;
> >>>>> - u8 chip_select;
> >>>>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>>>> u8 bits_per_word;
> >>>>> bool rt;
> >>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>>>> @@ -202,7 +208,7 @@ struct spi_device {
> >>>>> void *controller_data;
> >>>>> char modalias[SPI_NAME_SIZE];
> >>>>> const char *driver_override;
> >>>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
> >>>> desc
> >>>>> */
> >>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> >>>> Chip
> >>>>> select gpio desc */
> >>>>> struct spi_delay word_delay; /* Inter-word delay */
> >>>>> /* CS delays */
> >>>>> struct spi_delay cs_setup;
> >>>>> @@ -212,6 +218,13 @@ struct spi_device {
> >>>>> /* The statistics */
> >>>>> struct spi_statistics __percpu *pcpu_statistics;
> >>>>>
> >>>>> + /* Bit mask of the chipselect(s) that the driver need to use
> >>>> from
> >>>>> + * the chipselect array.When the controller is capable to
> >>>> handle
> >>>>> + * multiple chip selects & memories are connected in parallel
> >>>>> + * then more than one bit need to be set in cs_index_mask.
> >>>>> + */
> >>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>>>> +
> >>>>> /*
> >>>>> * likely need more hooks for more protocol options affecting
> how
> >>>>> * the controller talks to each chip, like:
> >>>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
> >>>>> struct spi_device *spi)
> >>>>>
> >>>>> static inline u8 spi_get_chipselect(const struct spi_device
> >>>>> *spi,
> >>>> u8 idx)
> >>>>> {
> >>>>> - return spi->chip_select;
> >>>>> + return spi->chip_select[idx];
> >>>>> }
> >>>>>
> >>>>> static inline void spi_set_chipselect(struct spi_device *spi,
> >>>>> u8
> >>>> idx, u8
> >>>>> chipselect)
> >>>>> {
> >>>>> - spi->chip_select = chipselect;
> >>>>> + spi->chip_select[idx] = chipselect;
> >>>>> }
> >>>>>
> >>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
> >>>> spi_device
> >>>>> *spi, u8 idx)
> >>>>> {
> >>>>> - return spi->cs_gpiod;
> >>>>> + return spi->cs_gpiod[idx];
> >>>>> }
> >>>>>
> >>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
> >>>>> idx,
> >>>> struct
> >>>>> gpio_desc *csgpiod)
> >>>>> {
> >>>>> - spi->cs_gpiod = csgpiod;
> >>>>> + spi->cs_gpiod[idx] = csgpiod;
> >>>>> }
> >>>>>
> >>>>> /**
> >>>>> @@ -388,6 +401,8 @@ extern struct spi_device
> >>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >>>> exclusive use
> >>>>> + * @multi_cs_cap: indicates that the SPI Controller can
> >>>> assert/de-assert
> >>>>> + * more than one chip select at once.
> >>>>> * @setup: updates the device mode and clocking records used by a
> >>>>> * device's SPI controller; protocol code may call this. This
> >>>>> * must fail if an unrecognized or unsupported mode is
> requested.
> >>>>> @@ -554,6 +569,11 @@ struct spi_controller {
> >>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
> >>>>> */
> >>>>>
> >>>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
> >>>> select
> >>>>> slave */
> >>>>> + /*
> >>>>> + * The spi-controller has multi chip select capability and can
> >>>>> + * assert/de-assert more than one chip select at once.
> >>>>> + */
> >>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
> >>>>>
> >>>>> /* Flag indicating if the allocation of this struct is devres-
> >>>>> managed */
> >>>>> bool devm_allocated;
> >>>>> --
> >>>>> 2.17.1
Hi,
On 27/04/2023 18:09, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Tuesday, April 25, 2023 5:50 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>;
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
>> in SPI core
>>
>> Hi,
>>
>> On 20/04/2023 10:04, Mahapatra, Amit Kumar wrote:
>>> Hello Stefan,
>>>
>>>> -----Original Message-----
>>>> From: Stefan Binding <[email protected]>
>>>> Sent: Wednesday, April 12, 2023 8:33 PM
>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]
>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; Simek, Michal
>> <[email protected]>;
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected]
>>>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>> support in SPI core
>>>>
>>>> Hi,
>>>>
>>>> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
>>>>> Hello Stefan,
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Stefan Binding <[email protected]>
>>>>>> Sent: Thursday, April 6, 2023 7:14 PM
>>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]
>>>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
>>>>>> linux- [email protected]; [email protected];
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; Simek, Michal
>>>> <[email protected]>;
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; [email protected]
>>>>>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>>>> support in SPI core
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>>> -----Original Message-----
>>>>>>> From: Amit Kumar Mahapatra <[email protected]>
>>>>>>> Sent: Thursday, April 6, 2023 7:54 AM
>>>>>>> To: [email protected]; [email protected];
>>>>>>> [email protected]; [email protected]; [email protected];
>>>>>>> [email protected]; [email protected]
>>>>>>> Cc: [email protected]; [email protected]; linux-
>>>>>>> [email protected]; [email protected]; linux-
>>>>>>> [email protected]; [email protected];
>>>>>>> [email protected]; [email protected];
>>>>>>> [email protected]; [email protected];
>>>>>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
>>>>>>> [email protected]>
>>>>>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>>>> support
>>>>>>> in SPI core
>>>>>>>
>>>>>>> For supporting multiple CS the SPI device need to be aware of all
>>>>>> the CS
>>>>>>> values. So, the "chip_select" member in the spi_device structure
>>>>>>> is
>>>>>> now
>>>>>>> an
>>>>>>> array that holds all the CS values.
>>>>>>>
>>>>>>> spi_device structure now has a "cs_index_mask" member. This acts
>>>>>>> as
>>>>>> an
>>>>>>> index to the chip_select array. If nth bit of spi->cs_index_mask
>>>>>>> is
>>>>>> set
>>>>>>> then the driver would assert spi->chip_select[n].
>>>>>>>
>>>>>>> In parallel mode all the chip selects are asserted/de-asserted
>>>>>>> simultaneously and each byte of data is stored in both devices,
>>>>>>> the
>>>>>> even
>>>>>>> bits in one, the odd bits in the other. The split is automatically
>>>>>> handled
>>>>>>> by the GQSPI controller. The GQSPI controller supports a maximum
>>>>>>> of two flashes connected in parallel mode. A
>>>>>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
>>>>>>> controntroller flags, through
>>>>>>> ctlr->flags the spi
>>>>>> core
>>>>>>> will make sure that the controller is capable of handling multiple
>>>>>> chip
>>>>>>> selects at once.
>>>>>>>
>>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>>>>>> spi_device structure is now an array that holds the gpio
>>>>>>> descriptor for each chipselect.
>>>>>>>
>>>>>>> Multi CS support using GPIO is not tested due to unavailability of
>>>>>>> necessary hardware setup.
>>>>>>>
>>>>>>> Multi CS configuration with one native CS and one GPIO CS is not
>>>>>>> supported as this configuration could not be tested due to
>>>>>>> unavailability of necessary hardware setup.
>>>>>> I've tested this chain on a released laptop (HP EliteBook 840 G9)
>>>>>> which uses SPI to interface to 2 amps, one amp uses a native CS and
>>>>>> the other uses a GPIO CS, and I noticed that when using this chain,
>>>>>> the second amp no longer works.
>>>>> Thank you for testing this patch series on GPIO CS setup. As I don't
>>>>> have a GPIO CS setup, is it possible for you debug the failure and
>>>>> share more details/logs where the problem is?
>>>>>
>>>>> Regards,
>>>>> Amit
>>>> We are willing and able to debug this failure and share the failure logs.
>>>> The first issue that I see is a kernel crash when trying to set the GPIO CS:
>>>>
>>>> [ 2.951658] general protection fault, probably for non-canonical
>>>> address
>>>> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771] CPU:
>> 9
>>>> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30 [
>>>> 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
>>>> [ 2.951882] RIP: 0010:gpiod_set_value_cansleep+0x21/0xa0
>>>> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85
>>>> ff
>>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff
>>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
>>>> ee 4c [ 2.952043]
>>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
>>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>>>> 0000000000000000
>>>> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>>>> dead000000000122
>>>> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>>>> ffffc008c0deb868
>>>> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>>>> dead000000000122
>>>> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
>>>> 0000000000000000
>>>> [ 2.952299] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
>>>> knlGS:0000000000000000
>>>> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>> 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>>>> 0000000000770ee0
>>>> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>> 0000000000000000
>>>> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>> 0000000000000400
>>>> [ 2.952533] PKRU: 55555554
>>>> [ 2.952561] Call Trace:
>>>> [ 2.952579] <TASK>
>>>> [ 2.952598] spi_set_cs+0x257/0x4a0 [ 2.952630]
>>>> spi_setup+0x1a2/0x500 [ 2.952667] __spi_add_device+0x88/0x160 [
>>>> 2.952710] spi_add_device+0x60/0x90 [ 2.952738]
>>>> smi_spi_probe+0x178/0x370 [serial_multi_instantiate] [ 2.952792]
>>>> smi_probe+0xcf/0x110 [serial_multi_instantiate] [ 2.952854]
>>>> platform_probe+0x42/0xb0 [ 2.952885] really_probe+0x1b2/0x420 [
>>>> 2.952914] __driver_probe_device+0x7e/0x180 [ 2.952947]
>>>> driver_probe_device+0x23/0xa0 [ 2.952993]
>>>> __driver_attach+0xe4/0x1e0 [ 2.953021] ?
>>>> __pfx___driver_attach+0x10/0x10
>>>> [ 2.953061] bus_for_each_dev+0x7a/0xd0 [ 2.953088]
>>>> driver_attach+0x1e/0x30 [ 2.953123] bus_add_driver+0x11c/0x220 [
>>>> 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
>>>> __pfx_init_module+0x10/0x10 [serial_multi_instantiate] [ 2.953221]
>>>> __platform_driver_register+0x1e/0x30
>>>> [ 2.953251] smi_driver_init+0x1c/0xff0 [serial_multi_instantiate]
>>>> [ 2.953310] do_one_initcall+0x46/0x220 [ 2.953339] ?
>>>> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220 [
>>>> 2.953411] load_module+0x223c/0x2460 [ 2.953450]
>>>> __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
>>>> __do_sys_finit_module+0xc8/0x140
>>>> [ 2.953510] __x64_sys_finit_module+0x18/0x20 [ 2.953538]
>>>> do_syscall_64+0x38/0x90 [ 2.953574]
>>>> entry_SYSCALL_64_after_hwframe+0x72/0xdc
>>>> [ 2.953606] RIP: 0033:0x7f7fa5d7476d [ 2.953639] Code: 00 c3 66
>>>> 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
>>>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08
>>>> 0f
>>>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
>>>> 48 [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246
>> ORIG_RAX:
>>>> 0000000000000139
>>>> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
>>>> 00007f7fa5d7476d
>>>> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
>>>> 0000000000000006
>>>> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
>>>> 0000000000000000
>>>> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
>>>> 00007f7fa5c54ded
>>>> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
>>>> 000055d648654ab0
>>>> [ 2.967668] resource: resource sanity check: requesting [mem
>>>> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp
>>>> 00:04 [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [
>>>> 2.971615] caller
>>>> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [
>>>> 2.975014] Modules linked in: igen6_edac(+) fjes(-)
>>>> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
>>>> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel
>>>> acpi_tad sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp
>>>> parport drm ramoops reed_solomon efi_pstore ip_tables x_tables
>>>> autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core nvme
>> intel_lpss_pci
>>>> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64
>>>> nvme_core i2c_smbus virt_dma xhci_pci_renesas video wmi
>>>> pinctrl_tigerlake [ 2.987901] ---[ end trace 0000000000000000 ]---
>> [ 3.157030] RIP:
>>>> 0010:gpiod_set_value_cansleep+0x21/0xa0
>>>> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48 85
>>>> ff
>>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff ff
>>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
>>>> ee 4c [ 3.161461]
>>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
>>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>>>> 0000000000000000
>>>> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>>>> dead000000000122
>>>> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>>>> ffffc008c0deb868
>>>> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>>>> dead000000000122
>>>> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
>>>> 0000000000000000
>>>> [ 3.175335] FS: 00007f7fa5b5b880(0000) GS:ffffa0a81f840000(0000)
>>>> knlGS:0000000000000000
>>>> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>> 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>>>> 0000000000770ee0
>>>> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>> 0000000000000000
>>>> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>> 0000000000000400
>>>> [ 3.188647] PKRU: 55555554
>>> Thank you for sharing the logs.
>>> As per our analysis the spi->cs_gpiod[0] is getting messed up while
>>> setting it in __spi_add_device( ).
>>> Is it possible for you to do the following changes on top of this
>>> patch series & re-run your test.
>>>
>>> After applying this patch series, in drivers/spi/spi.c file replace
>>> the following code snippet in __spi_add_device( ) function defination.
>>>
>>> if (ctlr->cs_gpiods) {
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> spi_set_csgpiod(spi, idx,
>>> ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
>>>
>>> with the below code snippet
>>>
>>> if (ctlr->cs_gpiods) {
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
>>> spi_set_csgpiod(spi, idx, ctlr-
>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>> }
>>> }
>>>
>>> then re-run your test.
>>>
>>> Regards,
>>> Amit
>> I'm still seeing a crash on probe:
>>
>> [ 3.265683] BUG: unable to handle page fault for address:
>> 00000000fffedfdd
>> [ 3.265744] #PF: supervisor read access in kernel mode [ 3.265781] #PF:
>> error_code(0x0000) - not-present page [ 3.265817] PGD 0 P4D 0
>> [ 3.265840] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 3.265865] CPU: 4 PID:
>> 385 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #32 [ 3.265910]
>> Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021 [ 3.265956]
>> RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
>> [ 3.266007] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
>> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
>> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
>> [ 3.266092] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [ 3.266121]
>> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
>> cccccccccccccccd
>> [ 3.266156] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
>> ffff9c8d4a5f6d40
>> [ 3.266192] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
>> 0000000000000000
>> [ 3.266228] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
>> 00000000fffedf7d
>> [ 3.266264] R13: 0000000000000000 R14: 0000000000000001 R15:
>> 0000000000000001
>> [ 3.266299] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
>> knlGS:0000000000000000
>> [ 3.266358] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 3.266388] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
>> 0000000000770ee0
>> [ 3.266422] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>> 0000000000000000
>> [ 3.266457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>> 0000000000000400
>> [ 3.266490] PKRU: 55555554
>> [ 3.266513] Call Trace:
>> [ 3.266530] <TASK>
>> [ 3.266546] gpiod_set_value_nocheck+0x5b/0x70
>> [ 3.266583] gpiod_set_value_cansleep+0x3e/0xa0
>> [ 3.266609] spi_set_cs+0x257/0x4a0
>> [ 3.266634] spi_transfer_one_message+0x49/0x740
>> [ 3.266672] __spi_pump_transfer_message+0x29b/0x620
>> [ 3.266712] __spi_sync+0x26f/0x3b0
>> [ 3.266735] spi_write_then_read+0x157/0x210 [ 3.266771] ?
>> psi_group_change+0x175/0x3b0 [ 3.266802] regmap_spi_read+0xe/0x20
>> [ 3.266826] _regmap_raw_read+0xe1/0x210
>> [ 3.266861] _regmap_bus_read+0x3a/0x70
>> [ 3.266887] _regmap_read+0x66/0x140
>> [ 3.266918] regmap_read+0x3f/0x70
>> [ 3.266957] cs35l41_hda_probe+0x553/0xc10 [snd_hda_scodec_cs35l41]
>> [ 3.267027] cs35l41_hda_spi_probe+0x62/0x80
>> [snd_hda_scodec_cs35l41_spi] [ 3.267096] spi_probe+0x55/0x90
>> [ 3.267145] really_probe+0x1b2/0x420
>> [ 3.267184] __driver_probe_device+0x7e/0x180
>> [ 3.267227] driver_probe_device+0x23/0xa0
>> [ 3.267287] __driver_attach+0xe4/0x1e0 [ 3.267326] ?
>> __pfx___driver_attach+0x10/0x10
>> [ 3.267381] bus_for_each_dev+0x7a/0xd0
>> [ 3.267406] driver_attach+0x1e/0x30
>> [ 3.267437] bus_add_driver+0x11c/0x220
>> [ 3.267461] driver_register+0x64/0x130 [ 3.267483] ?
>> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
>> [ 3.267525] __spi_register_driver+0xa1/0xd0 [ 3.270712] ?
>> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi]
>> [ 3.273446] cs35l41_spi_driver_init+0x1c/0xff0
>> [snd_hda_scodec_cs35l41_spi]
>> [ 3.275119] do_one_initcall+0x46/0x220 [ 3.276828] ?
>> kmalloc_trace+0x2a/0xa0 [ 3.279290] do_init_module+0x52/0x220
>> [ 3.283593] load_module+0x223c/0x2460
>> [ 3.283602] __do_sys_finit_module+0xc8/0x140 [ 3.287883] ?
>> __do_sys_finit_module+0xc8/0x140
>> [ 3.287907] __x64_sys_finit_module+0x18/0x20
>> [ 3.293156] do_syscall_64+0x38/0x90
>> [ 3.298937] entry_SYSCALL_64_after_hwframe+0x72/0xdc
>> [ 3.298945] RIP: 0033:0x7f98d06f776d
>> [ 3.319574] Code: 00 c3 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08 0f
>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01 48
>> [ 3.319579] RSP: 002b:00007ffd988f7a08 EFLAGS: 00000246 ORIG_RAX:
>> 0000000000000139
>> [ 3.319585] RAX: ffffffffffffffda RBX: 000055af06a7d030 RCX:
>> 00007f98d06f776d
>> [ 3.319589] RDX: 0000000000000000 RSI: 00007f98d05d7ded RDI:
>> 0000000000000013
>> [ 3.329520] RBP: 0000000000020000 R08: 0000000000000000 R09:
>> 0000000000000000
>> [ 3.329523] R10: 0000000000000013 R11: 0000000000000246 R12:
>> 00007f98d05d7ded
>> [ 3.329525] R13: 0000000000000000 R14: 000055af06cdd040 R15:
>> 000055af06a7d030
>> [ 3.329531] </TASK>
>> [ 3.329533] Modules linked in: snd_hda_intel(+) ttm snd_intel_dspcfg btusb
>> rapl snd_seq_midi snd_intel_sdw_acpi libarc4 intel_cstate binfmt_misc
>> uvcvideo(+) snd_seq_midi_event btrtl
>> snd_hda_scodec_cs35l41_spi(+) snd_hda_codec drm_display_helper
>> cdc_ncm(+) videobuf2_vmalloc snd_rawmidi btbcm uvc cdc_ether cec btintel
>> videobuf2_memops snd_hda_scodec_cs35l41_i2c snd_hda_core
>> videobuf2_v4l2 uas usbnet rc_core snd_hwdep btmtk
>> snd_hda_scodec_cs35l41 input_leds mii wmi_bmof videodev snd_seq
>> processor_thermal_device_pci bluetooth iwlwifi drm_kms_helper snd_pcm
>> snd_hda_cs_dsp_ctls processor_thermal_device mei_me
>> videobuf2_common snd_seq_device i2c_algo_bit cs_dsp
>> processor_thermal_rfim ecdh_generic usb_storage serio_raw mc
>> syscopyarea ecc processor_thermal_mbox ucsi_acpi snd_soc_cs35l41_lib
>> 8250_dw mei snd_timer cfg80211 sysfillrect typec_ucsi
>> processor_thermal_rapl igen6_edac sysimgblt intel_rapl_common typec snd
>> soundcore int3403_thermal int340x_thermal_zone serial_multi_instantiate
>> int3400_thermal intel_hid acpi_thermal_rel [ 3.338475] sparse_keymap
>> acpi_tad acpi_pad mac_hid sch_fq_codel msr parport_pc ppdev lp parport
>> drm ramoops reed_solomon efi_pstore ip_tables x_tables autofs4
>> spi_pxa2xx_platform dw_dmac dw_dmac_core intel_lpss_pci nvme
>> intel_lpss i2c_i801 idma64 crc32_pclmul thunderbolt i2c_smbus nvme_core
>> xhci_pci virt_dma xhci_pci_renesas video wmi pinctrl_tigerlake [ 3.338514]
>> CR2: 00000000fffedfdd [ 3.338517] ---[ end trace 0000000000000000 ]---
>> [ 3.504965] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
>> [ 3.504973] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48 2b
>> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48 89
>> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d 5d
>> [ 3.504975] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [ 3.504978]
>> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
>> cccccccccccccccd
>> [ 3.504979] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
>> ffff9c8d4a5f6d40
>> [ 3.504980] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
>> 0000000000000000
>> [ 3.504982] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
>> 00000000fffedf7d
>> [ 3.504983] R13: 0000000000000000 R14: 0000000000000001 R15:
>> 0000000000000001
>> [ 3.504984] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
>> knlGS:0000000000000000
>> [ 3.504986] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033
>> [ 3.504988] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
>> 0000000000770ee0
>> [ 3.504989] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>> 0000000000000000
>> [ 3.504990] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>> 0000000000000400
>> [ 3.504992] PKRU: 55555554
>>
>> Thanks,
>> Stefan
> Thanks for the logs.
>
> Could you please confirm that your test case was passing with
> https://github.com/torvalds/linux/commit/303feb3cc06ac0665d0ee9c1414941200e60e8a3 patch
> but it is failing with the current patch series ?
I retested with the latest master kernel
https://github.com/torvalds/linux/commit/33afd4b76393627477e878b3b195d606e585d816
and I could see it worked fine. I attached a dmesg log of this.
That particular commit id you posted does not work, due to a different
issue which was fixed in a later commit.
>
> Regarding the failure
> The logs suggest that we are trying to access an invalid pointer while
> calling the gpiod_set_value_cansleep( ) API.
> This could be possible if the cs_num is corrupted and we are trying to
> access an invalid spi->cs_gpiod[ ].
> To confirm the same could you please do the following changes in the
> code and re-test.
>
> After applying this patch series, in drivers/spi/spi.c file replace the
> following code snippet in __spi_add_device( ) function definition.
> if (ctlr->cs_gpiods) {
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
> }
>
> with the below code snippet
>
> if (ctlr->cs_gpiods) {
> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> if (!(idx != 0 && !spi_get_chipselect(spi, idx))) {
> printk("%s( ) [%d] cs[%d] = [%d]\n", __func__, __LINE__, idx, spi_get_chipselect(spi, idx));
> spi_set_csgpiod(spi, idx, ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]);
> }
> }
> }
>
> And at the start of spi_set_cs( ) function in drivers/spi/spi.c file add
> the following print statements.
>
> printk("%s( ) [%d] spi->cs_index_mask == [%d]\n", __func__, __LINE__, spi->cs_index_mask);
> printk("%s( ) [%d] cs_num == [%d]\n", __func__, __LINE__, cs_num);
I've attached dmesg log of this. It no longer crashes when using the
prints (I am unsure why), but it still does not work.
For sanity, I retested these changes with the print lines commented out,
and the crash returned.
>
> Thanks,
> Amit
>>>> Thanks,
>>>>
>>>> Stefan
>>>>
>>>>>> Thanks,
>>>>>> Stefan Binding
>>>>>>
>>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>>>>>> [email protected]>
>>>>>>> ---
>>>>>>> drivers/spi/spi.c | 226
>>>>>> ++++++++++++++++++++++++++++------------
>>>>>>> include/linux/spi/spi.h | 32 ++++--
>>>>>>> 2 files changed, 183 insertions(+), 75 deletions(-)
>>>>>>>
>>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>>>>>> 9036d7a50674..04d7322170c4 100644
>>>>>>> --- a/drivers/spi/spi.c
>>>>>>> +++ b/drivers/spi/spi.c
>>>>>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device *dev,
>>>>>>> void *data) {
>>>>>>> struct spi_device *spi = to_spi_device(dev);
>>>>>>> struct spi_device *new_spi = data;
>>>>>>> + int idx, nw_idx;
>>>>>>>
>>>>>>> - if (spi->controller == new_spi->controller &&
>>>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
>>>>>> 0))
>>>>>>> - return -EBUSY;
>>>>>>> + if (spi->controller == new_spi->controller) {
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>>>>>> nw_idx++) {
>>>>>>> + if ((idx != 0 &&
>>>>>> !spi_get_chipselect(spi,
>>>>>>> idx)) ||
>>>>>>> + (nw_idx != 0 &&
>>>>>>> !spi_get_chipselect(spi, nw_idx))) {
>>>>>>> + continue;
>>>>>>> + } else if (spi_get_chipselect(spi,
>>>>>> idx) ==
>>>>>>> + spi_get_chipselect(new_spi,
>>>>>> nw_idx))
>>>>>>> {
>>>>>>> + dev_err(dev,
>>>>>>> + "chipselect %d
>> already
>>>>>>> in use\n",
>>>>>>> +
>>>>>>> spi_get_chipselect(new_spi, nw_idx));
>>>>>>> + return -EBUSY;
>>>>>>> + }
>>>>>>> + }
>>>>>>> + }
>>>>>>> + }
>>>>>>> return 0;
>>>>>>> }
>>>>>>>
>>>>>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
>>>>>>> *spi)
>>>>>>> {
>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>> - int status;
>>>>>>> + int status, idx;
>>>>>>>
>>>>>>> /*
>>>>>>> * We need to make sure there's no other device with this
>> @@
>>>>>>> -638,8
>>>>>>> +652,6 @@ static int __spi_add_device(struct spi_device
>>>>>>> *spi)
>>>>>>> */
>>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
>>>>>> spi_dev_check);
>>>>>>> if (status) {
>>>>>>> - dev_err(dev, "chipselect %d already in use\n",
>>>>>>> - spi_get_chipselect(spi, 0));
>>>>>>> return status;
>>>>>>> }
>>>>>>>
>>>>>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct spi_device
>>>>>>> *spi)
>>>>>>> return -ENODEV;
>>>>>>> }
>>>>>>>
>>>>>>> - if (ctlr->cs_gpiods)
>>>>>>> - spi_set_csgpiod(spi, 0, ctlr-
>>>>>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
>>>>>>> + if (ctlr->cs_gpiods) {
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
>>>>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>>>>>> + }
>>>>>>>
>>>>>>> /*
>>>>>>> * Drivers may modify this initial i/o setup, but will @@
>>>>>>> -690,13
>>>>>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>> - int status;
>>>>>>> + int status, idx;
>>>>>>>
>>>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>>>> spi_get_chipselect(spi, 0),
>>>>>>> - ctlr->num_chipselect);
>>>>>>> - return -EINVAL;
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>>>> ctlr->num_chipselect) {
>>>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>>>> spi_get_chipselect(spi, idx),
>>>>>>> + ctlr->num_chipselect);
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> }
>>>>>>>
>>>>>>> /* Set the bus ID string */
>>>>>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
>>>>>>> spi_device *spi) {
>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>> + int idx;
>>>>>>>
>>>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>>>> spi_get_chipselect(spi, 0),
>>>>>>> - ctlr->num_chipselect);
>>>>>>> - return -EINVAL;
>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>>>> ctlr->num_chipselect) {
>>>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>>>> spi_get_chipselect(spi, idx),
>>>>>>> + ctlr->num_chipselect);
>>>>>>> + return -EINVAL;
>>>>>>> + }
>>>>>>> }
>>>>>>>
>>>>>>> /* Set the bus ID string */
>>>>>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
>>>>>>> spi_controller *ctlr, struct spi_message *mes static void
>>>>>>> spi_set_cs(struct spi_device *spi, bool enable, bool
>>>>>> force)
>>>>>>> {
>>>>>>> bool activate = enable;
>>>>>>> + u32 cs_num = __ffs(spi->cs_index_mask);
>>>>>>> + int idx;
>>>>>>>
>>>>>>> /*
>>>>>>> - * Avoid calling into the driver (or doing delays) if the chip
>>>>>> select
>>>>>>> - * isn't actually changing from the last time this was called.
>>>>>>> + * In parallel mode all the chip selects are
>>>>>> asserted/de-asserted
>>>>>>> + * at once
>>>>>>> */
>>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
>>>>>>> spi_get_chipselect(spi, 0)) ||
>>>>>>> - (!enable && spi->controller->last_cs !=
>>>>>>> spi_get_chipselect(spi, 0))) &&
>>>>>>> - (spi->controller->last_cs_mode_high == (spi->mode &
>>>>>>> SPI_CS_HIGH)))
>>>>>>> - return;
>>>>>>> -
>>>>>>> - trace_spi_set_cs(spi, activate);
>>>>>>> -
>>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
>>>>>> : -1;
>>>>>>> - spi->controller->last_cs_mode_high = spi->mode &
>>>>>>> SPI_CS_HIGH;
>>>>>>> -
>>>>>>> - if ((spi_get_csgpiod(spi, 0) ||
>>>>>> !spi->controller->set_cs_timing)
>>>>>>> && !activate)
>>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>> -
>>>>>>> - if (spi->mode & SPI_CS_HIGH)
>>>>>>> - enable = !enable;
>>>>>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
>>>>>>> SPI_PARALLEL_CS_MASK) {
>>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>>>> SPI_CS_HIGH;
>>>>>>> +
>>>>>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
>>>>>>>> set_cs_timing) && !activate)
>>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>> +
>>>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>>>> + enable = !enable;
>>>>>>> +
>>>>>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
>>>>>> 1)) {
>>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>>>> + /*
>>>>>>> + * Historically ACPI has no means of
>>>>>> the
>>>>>>> GPIO polarity and
>>>>>>> + * thus the SPISerialBus() resource
>>>>>>> defines it on the per-chip
>>>>>>> + * basis. In order to avoid a chain of
>>>>>>> negations, the GPIO
>>>>>>> + * polarity is considered being Active
>>>>>>> High. Even for the cases
>>>>>>> + * when _DSD() is involved (in the
>>>>>>> updated versions of ACPI)
>>>>>>> + * the GPIO CS polarity must be
>>>>>> defined
>>>>>>> Active High to avoid
>>>>>>> + * ambiguity. That's why we use
>>>>>> enable,
>>>>>>> that takes SPI_CS_HIGH
>>>>>>> + * into account.
>>>>>>> + */
>>>>>>> + if (has_acpi_companion(&spi->dev)) {
>>>>>>> + for (idx = 0; idx <
>>>>>>> SPI_CS_CNT_MAX; idx++)
>>>>>>> +
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>> +
>>>>>>> !enable);
>>>>>>> + } else {
>>>>>>> + for (idx = 0; idx <
>>>>>>> SPI_CS_CNT_MAX; idx++)
>>>>>>> + /* Polarity handled by
>>>>>>> GPIO library */
>>>>>>> +
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>> +
>>>>>>> activate);
>>>>>>> + }
>>>>>>> + }
>>>>>>> + /* Some SPI masters need both GPIO CS &
>>>>>>> slave_select */
>>>>>>> + if ((spi->controller->flags &
>>>>>>> SPI_MASTER_GPIO_SS) &&
>>>>>>> + spi->controller->set_cs)
>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>> + } else if (spi->controller->set_cs) {
>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>> + }
>>>>>>>
>>>>>>> - if (spi_get_csgpiod(spi, 0)) {
>>>>>>> - if (!(spi->mode & SPI_NO_CS)) {
>>>>>>> - /*
>>>>>>> - * Historically ACPI has no means of the GPIO
>>>>>>> polarity and
>>>>>>> - * thus the SPISerialBus() resource defines it
>>>>>> on
>>>>>>> the per-chip
>>>>>>> - * basis. In order to avoid a chain of
>>>>>> negations,
>>>>>>> the GPIO
>>>>>>> - * polarity is considered being Active High.
>>>>>> Even
>>>>>>> for the cases
>>>>>>> - * when _DSD() is involved (in the updated
>>>>>>> versions of ACPI)
>>>>>>> - * the GPIO CS polarity must be defined Active
>>>>>>> High to avoid
>>>>>>> - * ambiguity. That's why we use enable, that
>>>>>>> takes SPI_CS_HIGH
>>>>>>> - * into account.
>>>>>>> - */
>>>>>>> - if (has_acpi_companion(&spi->dev))
>>>>>>> -
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>>>>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
>>>>>> ||
>>>>>>> + !spi->controller->set_cs_timing) {
>>>>>>> + if (activate)
>>>>>>> + spi_delay_exec(&spi->cs_setup,
>> NULL);
>>>>>>> else
>>>>>>> - /* Polarity handled by GPIO library */
>>>>>>> -
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>>>> NULL);
>>>>>>> }
>>>>>>> - /* Some SPI masters need both GPIO CS & slave_select
>>>>>>> */
>>>>>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS) &&
>>>>>>> - spi->controller->set_cs)
>>>>>>> + } else {
>>>>>>> + /*
>>>>>>> + * Avoid calling into the driver (or doing delays) if
>>>>>> the
>>>>>>> chip select
>>>>>>> + * isn't actually changing from the last time this was
>>>>>>> called.
>>>>>>> + */
>>>>>>> + if (!force && ((enable && spi->controller->last_cs ==
>>>>>>> + spi_get_chipselect(spi, cs_num)) ||
>>>>>>> + (!enable && spi->controller->last_cs
>>>>>> !=
>>>>>>> + spi_get_chipselect(spi, cs_num))) &&
>>>>>>> + (spi->controller->last_cs_mode_high ==
>>>>>>> + (spi->mode & SPI_CS_HIGH)))
>>>>>>> + return;
>>>>>>> +
>>>>>>> + trace_spi_set_cs(spi, activate);
>>>>>>> +
>>>>>>> + spi->controller->last_cs = enable ?
>>>>>>> spi_get_chipselect(spi, cs_num) : -1;
>>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>>>> SPI_CS_HIGH;
>>>>>>> +
>>>>>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>>>> set_cs_timing) && !activate)
>>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>> +
>>>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>>>> + enable = !enable;
>>>>>>> +
>>>>>>> + if (spi_get_csgpiod(spi, cs_num)) {
>>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>>>> + /*
>>>>>>> + * Historically ACPI has no means of
>>>>>> the
>>>>>>> GPIO polarity and
>>>>>>> + * thus the SPISerialBus() resource
>>>>>>> defines it on the per-chip
>>>>>>> + * basis. In order to avoid a chain of
>>>>>>> negations, the GPIO
>>>>>>> + * polarity is considered being Active
>>>>>>> High. Even for the cases
>>>>>>> + * when _DSD() is involved (in the
>>>>>>> updated versions of ACPI)
>>>>>>> + * the GPIO CS polarity must be
>>>>>> defined
>>>>>>> Active High to avoid
>>>>>>> + * ambiguity. That's why we use
>>>>>> enable,
>>>>>>> that takes SPI_CS_HIGH
>>>>>>> + * into account.
>>>>>>> + */
>>>>>>> + if (has_acpi_companion(&spi->dev))
>>>>>>> +
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>>>> +
>>>>>>> !enable);
>>>>>>> + else
>>>>>>> + /* Polarity handled by GPIO
>>>>>>> library */
>>>>>>> +
>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>>>> +
>>>>>>> activate);
>>>>>>> + }
>>>>>>> + /* Some SPI masters need both GPIO CS &
>>>>>>> slave_select */
>>>>>>> + if ((spi->controller->flags &
>>>>>>> SPI_MASTER_GPIO_SS) &&
>>>>>>> + spi->controller->set_cs)
>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>> + } else if (spi->controller->set_cs) {
>>>>>>> spi->controller->set_cs(spi, !enable);
>>>>>>> - } else if (spi->controller->set_cs) {
>>>>>>> - spi->controller->set_cs(spi, !enable);
>>>>>>> - }
>>>>>>> + }
>>>>>>>
>>>>>>> - if (spi_get_csgpiod(spi, 0) ||
>>>>>> !spi->controller->set_cs_timing) {
>>>>>>> - if (activate)
>>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>>>>>> - else
>>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>>>>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>>>> set_cs_timing) {
>>>>>>> + if (activate)
>>>>>>> + spi_delay_exec(&spi->cs_setup,
>> NULL);
>>>>>>> + else
>>>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>>>> NULL);
>>>>>>> + }
>>>>>>> }
>>>>>>> }
>>>>>>>
>>>>>>> @@ -2246,8 +2325,8 @@ static void of_spi_parse_dt_cs_delay(struct
>>>>>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
>>>>>>> *ctlr, struct
>>>>>> spi_device
>>>>>>> *spi,
>>>>>>> struct device_node *nc)
>>>>>>> {
>>>>>>> - u32 value;
>>>>>>> - int rc;
>>>>>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
>>>>>>> + int rc, idx;
>>>>>>>
>>>>>>> /* Mode (clock phase/polarity/etc.) */
>>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13
>>>>>>> +2399,21
>>>>>> @@
>>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
>>>>>>> spi_device *spi,
>>>>>>> }
>>>>>>>
>>>>>>> /* Device address */
>>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
>>>>>>> - if (rc) {
>>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
>> 1,
>>>>>>> + SPI_CS_CNT_MAX);
>>>>>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
>>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>>>>>> (%d)\n",
>>>>>>> nc, rc);
>>>>>>> return rc;
>>>>>>> + } else if ((of_property_read_bool(nc, "parallel-memories"))
>> &&
>>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
>>>>>> multi
>>>>>>> CS\n");
>>>>>>> + return -EINVAL;
>>>>>>> }
>>>>>>> - spi_set_chipselect(spi, 0, value);
>>>>>>> + for (idx = 0; idx < rc; idx++)
>>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>>>>>> + /* By default set the spi->cs_index_mask as 1 */
>>>>>>> + spi->cs_index_mask = 0x01;
>>>>>>>
>>>>>>> /* Device speed */
>>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
>> @@
>>>>>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device
>>>>>>> *spi, struct spi_message *message)
>>>>>>> * cs_change is set for each transfer.
>>>>>>> */
>>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>>>>>> SPI_CS_WORD) ||
>>>>>>> - spi_get_csgpiod(spi, 0))) {
>>>>>>> + spi_get_csgpiod(spi, 0) ||
>>>>>>> + spi_get_csgpiod(spi, 1))) {
>>>>>>> size_t maxsize;
>>>>>>> int ret;
>>>>>>>
>>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
>>>>>>> index 873ced6ae4ca..6453b246e0af 100644
>>>>>>> --- a/include/linux/spi/spi.h
>>>>>>> +++ b/include/linux/spi/spi.h
>>>>>>> @@ -19,6 +19,11 @@
>>>>>>> #include <linux/acpi.h>
>>>>>>> #include <linux/u64_stats_sync.h>
>>>>>>>
>>>>>>> +/* Max no. of CS supported per spi device */ #define
>>>>>>> +SPI_CS_CNT_MAX
>>>>>>> +2
>>>>>>> +
>>>>>>> +/* chip select mask */
>>>>>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
>>>>>>> struct dma_chan;
>>>>>>> struct software_node;
>>>>>>> struct ptp_system_timestamp;
>>>>>>> @@ -166,6 +171,7 @@ extern void
>>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>>>> * deasserted. If @cs_change_delay is used from
>> @spi_transfer,
>>>>>>> then the
>>>>>>> * two delays will be added up.
>>>>>>> * @pcpu_statistics: statistics for the spi_device
>>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>>>>>> chipselect array
>>>>>>> *
>>>>>>> * A @spi_device is used to interchange data between an SPI slave
>>>>>>> * (usually a discrete chip) and CPU memory.
>>>>>>> @@ -181,7 +187,7 @@ struct spi_device {
>>>>>>> struct spi_controller *controller;
>>>>>>> struct spi_controller *master; /* Compatibility layer
>>>>>> */
>>>>>>> u32 max_speed_hz;
>>>>>>> - u8 chip_select;
>>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>>>>>> u8 bits_per_word;
>>>>>>> bool rt;
>>>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>>>>>> @@ -202,7 +208,7 @@ struct spi_device {
>>>>>>> void *controller_data;
>>>>>>> char modalias[SPI_NAME_SIZE];
>>>>>>> const char *driver_override;
>>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
>>>>>> desc
>>>>>>> */
>>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
>>>>>> Chip
>>>>>>> select gpio desc */
>>>>>>> struct spi_delay word_delay; /* Inter-word delay */
>>>>>>> /* CS delays */
>>>>>>> struct spi_delay cs_setup;
>>>>>>> @@ -212,6 +218,13 @@ struct spi_device {
>>>>>>> /* The statistics */
>>>>>>> struct spi_statistics __percpu *pcpu_statistics;
>>>>>>>
>>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
>>>>>> from
>>>>>>> + * the chipselect array.When the controller is capable to
>>>>>> handle
>>>>>>> + * multiple chip selects & memories are connected in parallel
>>>>>>> + * then more than one bit need to be set in cs_index_mask.
>>>>>>> + */
>>>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>>>>>> +
>>>>>>> /*
>>>>>>> * likely need more hooks for more protocol options affecting
>> how
>>>>>>> * the controller talks to each chip, like:
>>>>>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
>>>>>>> struct spi_device *spi)
>>>>>>>
>>>>>>> static inline u8 spi_get_chipselect(const struct spi_device
>>>>>>> *spi,
>>>>>> u8 idx)
>>>>>>> {
>>>>>>> - return spi->chip_select;
>>>>>>> + return spi->chip_select[idx];
>>>>>>> }
>>>>>>>
>>>>>>> static inline void spi_set_chipselect(struct spi_device *spi,
>>>>>>> u8
>>>>>> idx, u8
>>>>>>> chipselect)
>>>>>>> {
>>>>>>> - spi->chip_select = chipselect;
>>>>>>> + spi->chip_select[idx] = chipselect;
>>>>>>> }
>>>>>>>
>>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>>>>>> spi_device
>>>>>>> *spi, u8 idx)
>>>>>>> {
>>>>>>> - return spi->cs_gpiod;
>>>>>>> + return spi->cs_gpiod[idx];
>>>>>>> }
>>>>>>>
>>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
>>>>>>> idx,
>>>>>> struct
>>>>>>> gpio_desc *csgpiod)
>>>>>>> {
>>>>>>> - spi->cs_gpiod = csgpiod;
>>>>>>> + spi->cs_gpiod[idx] = csgpiod;
>>>>>>> }
>>>>>>>
>>>>>>> /**
>>>>>>> @@ -388,6 +401,8 @@ extern struct spi_device
>>>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>>>>> exclusive use
>>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
>>>>>> assert/de-assert
>>>>>>> + * more than one chip select at once.
>>>>>>> * @setup: updates the device mode and clocking records used by a
>>>>>>> * device's SPI controller; protocol code may call this. This
>>>>>>> * must fail if an unrecognized or unsupported mode is
>> requested.
>>>>>>> @@ -554,6 +569,11 @@ struct spi_controller {
>>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /* Requires tx
>>>>>>> */
>>>>>>>
>>>>>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS must
>>>>>> select
>>>>>>> slave */
>>>>>>> + /*
>>>>>>> + * The spi-controller has multi chip select capability and can
>>>>>>> + * assert/de-assert more than one chip select at once.
>>>>>>> + */
>>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
>>>>>>>
>>>>>>> /* Flag indicating if the allocation of this struct is devres-
>>>>>>> managed */
>>>>>>> bool devm_allocated;
>>>>>>> --
>>>>>>> 2.17.1
Hello Stefan,
> -----Original Message-----
> From: Stefan Binding <[email protected]>
> Sent: Friday, April 28, 2023 7:38 PM
> To: Mahapatra, Amit Kumar <[email protected]>;
> [email protected]; [email protected]; [email protected];
> [email protected]; [email protected]; [email protected];
> [email protected]
> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; Simek, Michal <[email protected]>;
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
> in SPI core
>
> Hi,
>
> On 27/04/2023 18:09, Mahapatra, Amit Kumar wrote:
> > Hello Stefan,
> >
> >> -----Original Message-----
> >> From: Stefan Binding <[email protected]>
> >> Sent: Tuesday, April 25, 2023 5:50 PM
> >> To: Mahapatra, Amit Kumar <[email protected]>;
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]; [email protected]; [email protected];
> >> [email protected]
> >> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
> >> [email protected]; [email protected];
> >> [email protected]; [email protected];
> >> [email protected]; Simek, Michal
> <[email protected]>;
> >> [email protected]; [email protected];
> >> [email protected]; [email protected]
> >> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >> support in SPI core
> >>
> >> Hi,
> >>
> >> On 20/04/2023 10:04, Mahapatra, Amit Kumar wrote:
> >>> Hello Stefan,
> >>>
> >>>> -----Original Message-----
> >>>> From: Stefan Binding <[email protected]>
> >>>> Sent: Wednesday, April 12, 2023 8:33 PM
> >>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]; [email protected]; [email protected];
> >>>> [email protected]
> >>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
> >>>> linux- [email protected]; [email protected];
> >>>> [email protected]; [email protected];
> >>>> [email protected]; Simek, Michal
> >> <[email protected]>;
> >>>> [email protected]; [email protected];
> >>>> [email protected]; [email protected]
> >>>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >>>> support in SPI core
> >>>>
> >>>> Hi,
> >>>>
> >>>> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
> >>>>> Hello Stefan,
> >>>>>
> >>>>>> -----Original Message-----
> >>>>>> From: Stefan Binding <[email protected]>
> >>>>>> Sent: Thursday, April 6, 2023 7:14 PM
> >>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; [email protected];
> [email protected];
> >>>>>> [email protected]; [email protected]
> >>>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
> >>>>>> linux- [email protected]; [email protected];
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; Simek, Michal
> >>>> <[email protected]>;
> >>>>>> [email protected]; [email protected];
> >>>>>> [email protected]; [email protected]
> >>>>>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel
> >>>>>> memories support in SPI core
> >>>>>>
> >>>>>> Hi,
> >>>>>>
> >>>>>>> -----Original Message-----
> >>>>>>> From: Amit Kumar Mahapatra <[email protected]>
> >>>>>>> Sent: Thursday, April 6, 2023 7:54 AM
> >>>>>>> To: [email protected]; [email protected];
> >>>>>>> [email protected]; [email protected];
> >>>>>>> [email protected]; [email protected]; [email protected]
> >>>>>>> Cc: [email protected]; [email protected]; linux-
> >>>>>>> [email protected]; [email protected]; linux-
> >>>>>>> [email protected]; [email protected];
> >>>>>>> [email protected]; [email protected];
> >>>>>>> [email protected]; [email protected];
> >>>>>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
> >>>>>>> [email protected]>
> >>>>>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
> >>>>>> support
> >>>>>>> in SPI core
> >>>>>>>
> >>>>>>> For supporting multiple CS the SPI device need to be aware of
> >>>>>>> all
> >>>>>> the CS
> >>>>>>> values. So, the "chip_select" member in the spi_device structure
> >>>>>>> is
> >>>>>> now
> >>>>>>> an
> >>>>>>> array that holds all the CS values.
> >>>>>>>
> >>>>>>> spi_device structure now has a "cs_index_mask" member. This acts
> >>>>>>> as
> >>>>>> an
> >>>>>>> index to the chip_select array. If nth bit of spi->cs_index_mask
> >>>>>>> is
> >>>>>> set
> >>>>>>> then the driver would assert spi->chip_select[n].
> >>>>>>>
> >>>>>>> In parallel mode all the chip selects are asserted/de-asserted
> >>>>>>> simultaneously and each byte of data is stored in both devices,
> >>>>>>> the
> >>>>>> even
> >>>>>>> bits in one, the odd bits in the other. The split is
> >>>>>>> automatically
> >>>>>> handled
> >>>>>>> by the GQSPI controller. The GQSPI controller supports a maximum
> >>>>>>> of two flashes connected in parallel mode. A
> >>>>>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
> >>>>>>> controntroller flags, through
> >>>>>>> ctlr->flags the spi
> >>>>>> core
> >>>>>>> will make sure that the controller is capable of handling
> >>>>>>> multiple
> >>>>>> chip
> >>>>>>> selects at once.
> >>>>>>>
> >>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
> >>>>>>> spi_device structure is now an array that holds the gpio
> >>>>>>> descriptor for each chipselect.
> >>>>>>>
> >>>>>>> Multi CS support using GPIO is not tested due to unavailability
> >>>>>>> of necessary hardware setup.
> >>>>>>>
> >>>>>>> Multi CS configuration with one native CS and one GPIO CS is not
> >>>>>>> supported as this configuration could not be tested due to
> >>>>>>> unavailability of necessary hardware setup.
> >>>>>> I've tested this chain on a released laptop (HP EliteBook 840 G9)
> >>>>>> which uses SPI to interface to 2 amps, one amp uses a native CS
> >>>>>> and the other uses a GPIO CS, and I noticed that when using this
> >>>>>> chain, the second amp no longer works.
> >>>>> Thank you for testing this patch series on GPIO CS setup. As I
> >>>>> don't have a GPIO CS setup, is it possible for you debug the
> >>>>> failure and share more details/logs where the problem is?
> >>>>>
> >>>>> Regards,
> >>>>> Amit
> >>>> We are willing and able to debug this failure and share the failure logs.
> >>>> The first issue that I see is a kernel crash when trying to set the GPIO CS:
> >>>>
> >>>> [ 2.951658] general protection fault, probably for non-canonical
> >>>> address
> >>>> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771]
> CPU:
> >> 9
> >>>> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30
> >>>> [ 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02
> >>>> 10/29/2021 [ 2.951882] RIP:
> >>>> 0010:gpiod_set_value_cansleep+0x21/0xa0
> >>>> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48
> >>>> 85 ff
> >>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff
> >>>> ff
> >>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
> >>>> ee 4c [ 2.952043]
> >>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
> >>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> >>>> 0000000000000000
> >>>> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> >>>> dead000000000122
> >>>> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> >>>> ffffc008c0deb868
> >>>> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> >>>> dead000000000122
> >>>> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
> >>>> 0000000000000000
> >>>> [ 2.952299] FS: 00007f7fa5b5b880(0000)
> >>>> GS:ffffa0a81f840000(0000)
> >>>> knlGS:0000000000000000
> >>>> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >>>> 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> >>>> 0000000000770ee0
> >>>> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >>>> 0000000000000000
> >>>> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >>>> 0000000000000400
> >>>> [ 2.952533] PKRU: 55555554
> >>>> [ 2.952561] Call Trace:
> >>>> [ 2.952579] <TASK>
> >>>> [ 2.952598] spi_set_cs+0x257/0x4a0 [ 2.952630]
> >>>> spi_setup+0x1a2/0x500 [ 2.952667] __spi_add_device+0x88/0x160 [
> >>>> 2.952710] spi_add_device+0x60/0x90 [ 2.952738]
> >>>> smi_spi_probe+0x178/0x370 [serial_multi_instantiate] [ 2.952792]
> >>>> smi_probe+0xcf/0x110 [serial_multi_instantiate] [ 2.952854]
> >>>> platform_probe+0x42/0xb0 [ 2.952885] really_probe+0x1b2/0x420 [
> >>>> 2.952914] __driver_probe_device+0x7e/0x180 [ 2.952947]
> >>>> driver_probe_device+0x23/0xa0 [ 2.952993]
> >>>> __driver_attach+0xe4/0x1e0 [ 2.953021] ?
> >>>> __pfx___driver_attach+0x10/0x10
> >>>> [ 2.953061] bus_for_each_dev+0x7a/0xd0 [ 2.953088]
> >>>> driver_attach+0x1e/0x30 [ 2.953123] bus_add_driver+0x11c/0x220
> >>>> [ 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
> >>>> __pfx_init_module+0x10/0x10 [serial_multi_instantiate] [
> >>>> 2.953221]
> >>>> __platform_driver_register+0x1e/0x30
> >>>> [ 2.953251] smi_driver_init+0x1c/0xff0
> >>>> [serial_multi_instantiate] [ 2.953310] do_one_initcall+0x46/0x220
> [ 2.953339] ?
> >>>> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220 [
> >>>> 2.953411] load_module+0x223c/0x2460 [ 2.953450]
> >>>> __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
> >>>> __do_sys_finit_module+0xc8/0x140
> >>>> [ 2.953510] __x64_sys_finit_module+0x18/0x20 [ 2.953538]
> >>>> do_syscall_64+0x38/0x90 [ 2.953574]
> >>>> entry_SYSCALL_64_after_hwframe+0x72/0xdc
> >>>> [ 2.953606] RIP: 0033:0x7f7fa5d7476d [ 2.953639] Code: 00 c3
> >>>> 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
> >>>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24
> >>>> 08 0f
> >>>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
> >>>> 48 [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246
> >> ORIG_RAX:
> >>>> 0000000000000139
> >>>> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
> >>>> 00007f7fa5d7476d
> >>>> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
> >>>> 0000000000000006
> >>>> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
> >>>> 0000000000000000
> >>>> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
> >>>> 00007f7fa5c54ded
> >>>> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
> >>>> 000055d648654ab0
> >>>> [ 2.967668] resource: resource sanity check: requesting [mem
> >>>> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp
> >>>> 00:04 [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [
> >>>> 2.971615] caller
> >>>> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [
> >>>> 2.975014] Modules linked in: igen6_edac(+) fjes(-)
> >>>> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
> >>>> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel
> >>>> acpi_tad sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp
> >>>> parport drm ramoops reed_solomon efi_pstore ip_tables x_tables
> >>>> autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core nvme
> >> intel_lpss_pci
> >>>> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64
> >>>> nvme_core i2c_smbus virt_dma xhci_pci_renesas video wmi
> >>>> pinctrl_tigerlake [ 2.987901] ---[ end trace 0000000000000000
> >>>> ]---
> >> [ 3.157030] RIP:
> >>>> 0010:gpiod_set_value_cansleep+0x21/0xa0
> >>>> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48
> >>>> 85 ff
> >>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff
> >>>> ff
> >>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
> >>>> ee 4c [ 3.161461]
> >>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
> >>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
> >>>> 0000000000000000
> >>>> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
> >>>> dead000000000122
> >>>> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
> >>>> ffffc008c0deb868
> >>>> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
> >>>> dead000000000122
> >>>> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
> >>>> 0000000000000000
> >>>> [ 3.175335] FS: 00007f7fa5b5b880(0000)
> >>>> GS:ffffa0a81f840000(0000)
> >>>> knlGS:0000000000000000
> >>>> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >>>> 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
> >>>> 0000000000770ee0
> >>>> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >>>> 0000000000000000
> >>>> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >>>> 0000000000000400
> >>>> [ 3.188647] PKRU: 55555554
> >>> Thank you for sharing the logs.
> >>> As per our analysis the spi->cs_gpiod[0] is getting messed up while
> >>> setting it in __spi_add_device( ).
> >>> Is it possible for you to do the following changes on top of this
> >>> patch series & re-run your test.
> >>>
> >>> After applying this patch series, in drivers/spi/spi.c file replace
> >>> the following code snippet in __spi_add_device( ) function defination.
> >>>
> >>> if (ctlr->cs_gpiods) {
> >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>> spi_set_csgpiod(spi, idx,
> >>> ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
> >>>
> >>> with the below code snippet
> >>>
> >>> if (ctlr->cs_gpiods) {
> >>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>> if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
> >>> spi_set_csgpiod(spi, idx, ctlr-
> >>> cs_gpiods[spi_get_chipselect(spi, idx)]);
> >>> }
> >>> }
> >>>
> >>> then re-run your test.
> >>>
> >>> Regards,
> >>> Amit
> >> I'm still seeing a crash on probe:
> >>
> >> [ 3.265683] BUG: unable to handle page fault for address:
> >> 00000000fffedfdd
> >> [ 3.265744] #PF: supervisor read access in kernel mode [ 3.265781] #PF:
> >> error_code(0x0000) - not-present page [ 3.265817] PGD 0 P4D 0 [
> >> 3.265840] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 3.265865] CPU: 4 PID:
> >> 385 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #32 [
> >> 3.265910] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
> >> [ 3.265956]
> >> RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
> >> [ 3.266007] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48
> >> 2b
> >> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48
> >> 89
> >> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d
> >> 5d [ 3.266092] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [
> >> 3.266121]
> >> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
> >> cccccccccccccccd
> >> [ 3.266156] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
> >> ffff9c8d4a5f6d40
> >> [ 3.266192] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
> >> 0000000000000000
> >> [ 3.266228] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
> >> 00000000fffedf7d
> >> [ 3.266264] R13: 0000000000000000 R14: 0000000000000001 R15:
> >> 0000000000000001
> >> [ 3.266299] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
> >> knlGS:0000000000000000
> >> [ 3.266358] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >> 3.266388] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
> >> 0000000000770ee0
> >> [ 3.266422] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >> 0000000000000000
> >> [ 3.266457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >> 0000000000000400
> >> [ 3.266490] PKRU: 55555554
> >> [ 3.266513] Call Trace:
> >> [ 3.266530] <TASK>
> >> [ 3.266546] gpiod_set_value_nocheck+0x5b/0x70 [ 3.266583]
> >> gpiod_set_value_cansleep+0x3e/0xa0
> >> [ 3.266609] spi_set_cs+0x257/0x4a0 [ 3.266634]
> >> spi_transfer_one_message+0x49/0x740
> >> [ 3.266672] __spi_pump_transfer_message+0x29b/0x620
> >> [ 3.266712] __spi_sync+0x26f/0x3b0 [ 3.266735]
> >> spi_write_then_read+0x157/0x210 [ 3.266771] ?
> >> psi_group_change+0x175/0x3b0
> [ 3.266802] regmap_spi_read+0xe/0x20
> >> [ 3.266826] _regmap_raw_read+0xe1/0x210 [ 3.266861]
> >> _regmap_bus_read+0x3a/0x70 [ 3.266887] _regmap_read+0x66/0x140
> [
> >> 3.266918] regmap_read+0x3f/0x70 [ 3.266957]
> >> cs35l41_hda_probe+0x553/0xc10 [snd_hda_scodec_cs35l41]
> [ 3.267027]
> >> cs35l41_hda_spi_probe+0x62/0x80 [snd_hda_scodec_cs35l41_spi] [
> >> 3.267096] spi_probe+0x55/0x90 [ 3.267145]
> >> really_probe+0x1b2/0x420 [ 3.267184]
> >> __driver_probe_device+0x7e/0x180 [ 3.267227]
> >> driver_probe_device+0x23/0xa0 [ 3.267287]
> >> __driver_attach+0xe4/0x1e0 [ 3.267326] ?
> >> __pfx___driver_attach+0x10/0x10
> >> [ 3.267381] bus_for_each_dev+0x7a/0xd0 [ 3.267406]
> >> driver_attach+0x1e/0x30 [ 3.267437] bus_add_driver+0x11c/0x220 [
> >> 3.267461] driver_register+0x64/0x130 [ 3.267483] ?
> >> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi] [
> >> 3.267525] __spi_register_driver+0xa1/0xd0 [ 3.270712] ?
> >> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi] [
> >> 3.273446] cs35l41_spi_driver_init+0x1c/0xff0
> >> [snd_hda_scodec_cs35l41_spi]
> >> [ 3.275119] do_one_initcall+0x46/0x220 [ 3.276828] ?
> >> kmalloc_trace+0x2a/0xa0 [ 3.279290] do_init_module+0x52/0x220 [
> >> 3.283593] load_module+0x223c/0x2460 [ 3.283602]
> >> __do_sys_finit_module+0xc8/0x140 [ 3.287883] ?
> >> __do_sys_finit_module+0xc8/0x140
> >> [ 3.287907] __x64_sys_finit_module+0x18/0x20 [ 3.293156]
> >> do_syscall_64+0x38/0x90 [ 3.298937]
> >> entry_SYSCALL_64_after_hwframe+0x72/0xdc
> >> [ 3.298945] RIP: 0033:0x7f98d06f776d [ 3.319574] Code: 00 c3 66
> >> 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
> >> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08
> >> 0f
> >> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
> >> 48 [ 3.319579] RSP: 002b:00007ffd988f7a08 EFLAGS: 00000246
> ORIG_RAX:
> >> 0000000000000139
> >> [ 3.319585] RAX: ffffffffffffffda RBX: 000055af06a7d030 RCX:
> >> 00007f98d06f776d
> >> [ 3.319589] RDX: 0000000000000000 RSI: 00007f98d05d7ded RDI:
> >> 0000000000000013
> >> [ 3.329520] RBP: 0000000000020000 R08: 0000000000000000 R09:
> >> 0000000000000000
> >> [ 3.329523] R10: 0000000000000013 R11: 0000000000000246 R12:
> >> 00007f98d05d7ded
> >> [ 3.329525] R13: 0000000000000000 R14: 000055af06cdd040 R15:
> >> 000055af06a7d030
> >> [ 3.329531] </TASK>
> >> [ 3.329533] Modules linked in: snd_hda_intel(+) ttm
> >> snd_intel_dspcfg btusb rapl snd_seq_midi snd_intel_sdw_acpi libarc4
> >> intel_cstate binfmt_misc
> >> uvcvideo(+) snd_seq_midi_event btrtl
> >> snd_hda_scodec_cs35l41_spi(+) snd_hda_codec drm_display_helper
> >> cdc_ncm(+) videobuf2_vmalloc snd_rawmidi btbcm uvc cdc_ether cec
> >> btintel videobuf2_memops snd_hda_scodec_cs35l41_i2c snd_hda_core
> >> videobuf2_v4l2 uas usbnet rc_core snd_hwdep btmtk
> >> snd_hda_scodec_cs35l41 input_leds mii wmi_bmof videodev snd_seq
> >> processor_thermal_device_pci bluetooth iwlwifi drm_kms_helper
> snd_pcm
> >> snd_hda_cs_dsp_ctls processor_thermal_device mei_me
> videobuf2_common
> >> snd_seq_device i2c_algo_bit cs_dsp processor_thermal_rfim
> >> ecdh_generic usb_storage serio_raw mc syscopyarea ecc
> >> processor_thermal_mbox ucsi_acpi snd_soc_cs35l41_lib 8250_dw mei
> >> snd_timer cfg80211 sysfillrect typec_ucsi processor_thermal_rapl
> >> igen6_edac sysimgblt intel_rapl_common typec snd soundcore
> >> int3403_thermal int340x_thermal_zone serial_multi_instantiate
> >> int3400_thermal intel_hid acpi_thermal_rel [ 3.338475]
> >> sparse_keymap acpi_tad acpi_pad mac_hid sch_fq_codel msr parport_pc
> >> ppdev lp parport drm ramoops reed_solomon efi_pstore ip_tables
> >> x_tables autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core
> >> intel_lpss_pci nvme intel_lpss i2c_i801 idma64 crc32_pclmul
> >> thunderbolt i2c_smbus nvme_core xhci_pci virt_dma xhci_pci_renesas
> >> video wmi pinctrl_tigerlake [ 3.338514]
> >> CR2: 00000000fffedfdd [ 3.338517] ---[ end trace 0000000000000000
> >> ]--- [ 3.504965] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
> >> [ 3.504973] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48
> >> 2b
> >> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48
> >> 89
> >> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d
> >> 5d [ 3.504975] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [
> >> 3.504978]
> >> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
> >> cccccccccccccccd
> >> [ 3.504979] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
> >> ffff9c8d4a5f6d40
> >> [ 3.504980] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
> >> 0000000000000000
> >> [ 3.504982] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
> >> 00000000fffedf7d
> >> [ 3.504983] R13: 0000000000000000 R14: 0000000000000001 R15:
> >> 0000000000000001
> >> [ 3.504984] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
> >> knlGS:0000000000000000
> >> [ 3.504986] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
> >> 3.504988] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
> >> 0000000000770ee0
> >> [ 3.504989] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
> >> 0000000000000000
> >> [ 3.504990] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
> >> 0000000000000400
> >> [ 3.504992] PKRU: 55555554
> >>
> >> Thanks,
> >> Stefan
> > Thanks for the logs.
> >
> > Could you please confirm that your test case was passing with
> >
> https://github.com/torvalds/linux/commit/303feb3cc06ac0665d0ee9c14149
> 4
> > 1200e60e8a3 patch but it is failing with the current patch series ?
>
> I retested with the latest master kernel
> https://github.com/torvalds/linux/commit/33afd4b76393627477e878b3b195
> d606e585d816
> and I could see it worked fine. I attached a dmesg log of this.
>
> That particular commit id you posted does not work, due to a different issue
> which was fixed in a later commit.
Thank you for the confirmation.
>
> >
> > Regarding the failure
> > The logs suggest that we are trying to access an invalid pointer while
> > calling the gpiod_set_value_cansleep( ) API.
> > This could be possible if the cs_num is corrupted and we are trying to
> > access an invalid spi->cs_gpiod[ ].
> > To confirm the same could you please do the following changes in the
> > code and re-test.
> >
> > After applying this patch series, in drivers/spi/spi.c file replace
> > the following code snippet in __spi_add_device( ) function definition.
> > if (ctlr->cs_gpiods) {
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> > spi_set_csgpiod(spi, idx,
> > ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
> >
> > with the below code snippet
> >
> > if (ctlr->cs_gpiods) {
> > for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> > if (!(idx != 0 && !spi_get_chipselect(spi, idx))) {
> > printk("%s( ) [%d] cs[%d] = [%d]\n", __func__, __LINE__, idx,
> spi_get_chipselect(spi, idx));
> > spi_set_csgpiod(spi, idx, ctlr-
> >cs_gpiods[spi_get_chipselect(spi, idx)]);
> > }
> > }
> > }
> >
> > And at the start of spi_set_cs( ) function in drivers/spi/spi.c file
> > add the following print statements.
> >
> > printk("%s( ) [%d] spi->cs_index_mask == [%d]\n", __func__, __LINE__,
> > spi->cs_index_mask); printk("%s( ) [%d] cs_num == [%d]\n", __func__,
> > __LINE__, cs_num);
>
> I've attached dmesg log of this. It no longer crashes when using the prints (I
> am unsure why), but it still does not work.
> For sanity, I retested these changes with the print lines commented out, and
> the crash returned.
Thanks a lot for the dmesg log.
Here the __ffs() is creating the issue. __ffs() behavior is undefined if
no set bits exist in spi->cs_index_mask , as a result random value
(i.e, 64) is assigned to cs_num.
I think this could be fixed by replacing __ffs() with ffs() calls.
To confirm the same could you please apply the attached patch on top of
this patch series and re-test. If it works fine, then for sanity kindly
rerun by removing the printk lines.
Thanks,
Amit
>
> >
> > Thanks,
> > Amit
> >>>> Thanks,
> >>>>
> >>>> Stefan
> >>>>
> >>>>>> Thanks,
> >>>>>> Stefan Binding
> >>>>>>
> >>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
> >>>>>> [email protected]>
> >>>>>>> ---
> >>>>>>> drivers/spi/spi.c | 226
> >>>>>> ++++++++++++++++++++++++++++------------
> >>>>>>> include/linux/spi/spi.h | 32 ++++--
> >>>>>>> 2 files changed, 183 insertions(+), 75 deletions(-)
> >>>>>>>
> >>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
> >>>>>>> 9036d7a50674..04d7322170c4 100644
> >>>>>>> --- a/drivers/spi/spi.c
> >>>>>>> +++ b/drivers/spi/spi.c
> >>>>>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device
> *dev,
> >>>>>>> void *data) {
> >>>>>>> struct spi_device *spi = to_spi_device(dev);
> >>>>>>> struct spi_device *new_spi = data;
> >>>>>>> + int idx, nw_idx;
> >>>>>>>
> >>>>>>> - if (spi->controller == new_spi->controller &&
> >>>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
> >>>>>> 0))
> >>>>>>> - return -EBUSY;
> >>>>>>> + if (spi->controller == new_spi->controller) {
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
> >>>>>>> nw_idx++) {
> >>>>>>> + if ((idx != 0 &&
> >>>>>> !spi_get_chipselect(spi,
> >>>>>>> idx)) ||
> >>>>>>> + (nw_idx != 0 &&
> >>>>>>> !spi_get_chipselect(spi, nw_idx))) {
> >>>>>>> + continue;
> >>>>>>> + } else if (spi_get_chipselect(spi,
> >>>>>> idx) ==
> >>>>>>> + spi_get_chipselect(new_spi,
> >>>>>> nw_idx))
> >>>>>>> {
> >>>>>>> + dev_err(dev,
> >>>>>>> + "chipselect %d
> >> already
> >>>>>>> in use\n",
> >>>>>>> +
> >>>>>>> spi_get_chipselect(new_spi, nw_idx));
> >>>>>>> + return -EBUSY;
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> return 0;
> >>>>>>> }
> >>>>>>>
> >>>>>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
> >>>>>>> *spi)
> >>>>>>> {
> >>>>>>> struct spi_controller *ctlr = spi->controller;
> >>>>>>> struct device *dev = ctlr->dev.parent;
> >>>>>>> - int status;
> >>>>>>> + int status, idx;
> >>>>>>>
> >>>>>>> /*
> >>>>>>> * We need to make sure there's no other device with this
> >> @@
> >>>>>>> -638,8
> >>>>>>> +652,6 @@ static int __spi_add_device(struct spi_device
> >>>>>>> *spi)
> >>>>>>> */
> >>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
> >>>>>> spi_dev_check);
> >>>>>>> if (status) {
> >>>>>>> - dev_err(dev, "chipselect %d already in use\n",
> >>>>>>> - spi_get_chipselect(spi, 0));
> >>>>>>> return status;
> >>>>>>> }
> >>>>>>>
> >>>>>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct
> spi_device
> >>>>>>> *spi)
> >>>>>>> return -ENODEV;
> >>>>>>> }
> >>>>>>>
> >>>>>>> - if (ctlr->cs_gpiods)
> >>>>>>> - spi_set_csgpiod(spi, 0, ctlr-
> >>>>>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
> >>>>>>> + if (ctlr->cs_gpiods) {
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
> >>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
> >>>>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
> >>>>>>> + }
> >>>>>>>
> >>>>>>> /*
> >>>>>>> * Drivers may modify this initial i/o setup, but will @@
> >>>>>>> -690,13
> >>>>>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
> >>>>>>> struct spi_controller *ctlr = spi->controller;
> >>>>>>> struct device *dev = ctlr->dev.parent;
> >>>>>>> - int status;
> >>>>>>> + int status, idx;
> >>>>>>>
> >>>>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>>>> - dev_err(dev, "cs%d >= max %d\n",
> >>>>>>> spi_get_chipselect(spi, 0),
> >>>>>>> - ctlr->num_chipselect);
> >>>>>>> - return -EINVAL;
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>>>> + if (spi_get_chipselect(spi, idx) >=
> >>>>>> ctlr->num_chipselect) {
> >>>>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>>>>> spi_get_chipselect(spi, idx),
> >>>>>>> + ctlr->num_chipselect);
> >>>>>>> + return -EINVAL;
> >>>>>>> + }
> >>>>>>> }
> >>>>>>>
> >>>>>>> /* Set the bus ID string */
> >>>>>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
> >>>>>>> spi_device *spi) {
> >>>>>>> struct spi_controller *ctlr = spi->controller;
> >>>>>>> struct device *dev = ctlr->dev.parent;
> >>>>>>> + int idx;
> >>>>>>>
> >>>>>>> - /* Chipselects are numbered 0..max; validate. */
> >>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
> >>>>>>> - dev_err(dev, "cs%d >= max %d\n",
> >>>>>>> spi_get_chipselect(spi, 0),
> >>>>>>> - ctlr->num_chipselect);
> >>>>>>> - return -EINVAL;
> >>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
> >>>>>>> + /* Chipselects are numbered 0..max; validate. */
> >>>>>>> + if (spi_get_chipselect(spi, idx) >=
> >>>>>> ctlr->num_chipselect) {
> >>>>>>> + dev_err(dev, "cs%d >= max %d\n",
> >>>>>>> spi_get_chipselect(spi, idx),
> >>>>>>> + ctlr->num_chipselect);
> >>>>>>> + return -EINVAL;
> >>>>>>> + }
> >>>>>>> }
> >>>>>>>
> >>>>>>> /* Set the bus ID string */
> >>>>>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
> >>>>>>> spi_controller *ctlr, struct spi_message *mes static void
> >>>>>>> spi_set_cs(struct spi_device *spi, bool enable, bool
> >>>>>> force)
> >>>>>>> {
> >>>>>>> bool activate = enable;
> >>>>>>> + u32 cs_num = __ffs(spi->cs_index_mask);
> >>>>>>> + int idx;
> >>>>>>>
> >>>>>>> /*
> >>>>>>> - * Avoid calling into the driver (or doing delays) if the chip
> >>>>>> select
> >>>>>>> - * isn't actually changing from the last time this was called.
> >>>>>>> + * In parallel mode all the chip selects are
> >>>>>> asserted/de-asserted
> >>>>>>> + * at once
> >>>>>>> */
> >>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
> >>>>>>> spi_get_chipselect(spi, 0)) ||
> >>>>>>> - (!enable && spi->controller->last_cs !=
> >>>>>>> spi_get_chipselect(spi, 0))) &&
> >>>>>>> - (spi->controller->last_cs_mode_high == (spi->mode &
> >>>>>>> SPI_CS_HIGH)))
> >>>>>>> - return;
> >>>>>>> -
> >>>>>>> - trace_spi_set_cs(spi, activate);
> >>>>>>> -
> >>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
> >>>>>> : -1;
> >>>>>>> - spi->controller->last_cs_mode_high = spi->mode &
> >>>>>>> SPI_CS_HIGH;
> >>>>>>> -
> >>>>>>> - if ((spi_get_csgpiod(spi, 0) ||
> >>>>>> !spi->controller->set_cs_timing)
> >>>>>>> && !activate)
> >>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
> >>>>>>> -
> >>>>>>> - if (spi->mode & SPI_CS_HIGH)
> >>>>>>> - enable = !enable;
> >>>>>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
> >>>>>>> SPI_PARALLEL_CS_MASK) {
> >>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
> >>>>>>> SPI_CS_HIGH;
> >>>>>>> +
> >>>>>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
> >>>>>>>> set_cs_timing) && !activate)
> >>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>>>> +
> >>>>>>> + if (spi->mode & SPI_CS_HIGH)
> >>>>>>> + enable = !enable;
> >>>>>>> +
> >>>>>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
> >>>>>> 1)) {
> >>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
> >>>>>>> + /*
> >>>>>>> + * Historically ACPI has no means of
> >>>>>> the
> >>>>>>> GPIO polarity and
> >>>>>>> + * thus the SPISerialBus() resource
> >>>>>>> defines it on the per-chip
> >>>>>>> + * basis. In order to avoid a chain of
> >>>>>>> negations, the GPIO
> >>>>>>> + * polarity is considered being Active
> >>>>>>> High. Even for the cases
> >>>>>>> + * when _DSD() is involved (in the
> >>>>>>> updated versions of ACPI)
> >>>>>>> + * the GPIO CS polarity must be
> >>>>>> defined
> >>>>>>> Active High to avoid
> >>>>>>> + * ambiguity. That's why we use
> >>>>>> enable,
> >>>>>>> that takes SPI_CS_HIGH
> >>>>>>> + * into account.
> >>>>>>> + */
> >>>>>>> + if (has_acpi_companion(&spi->dev)) {
> >>>>>>> + for (idx = 0; idx <
> >>>>>>> SPI_CS_CNT_MAX; idx++)
> >>>>>>> +
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>>>> +
> >>>>>>> !enable);
> >>>>>>> + } else {
> >>>>>>> + for (idx = 0; idx <
> >>>>>>> SPI_CS_CNT_MAX; idx++)
> >>>>>>> + /* Polarity handled by
> >>>>>>> GPIO library */
> >>>>>>> +
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
> >>>>>>> +
> >>>>>>> activate);
> >>>>>>> + }
> >>>>>>> + }
> >>>>>>> + /* Some SPI masters need both GPIO CS &
> >>>>>>> slave_select */
> >>>>>>> + if ((spi->controller->flags &
> >>>>>>> SPI_MASTER_GPIO_SS) &&
> >>>>>>> + spi->controller->set_cs)
> >>>>>>> + spi->controller->set_cs(spi, !enable);
> >>>>>>> + } else if (spi->controller->set_cs) {
> >>>>>>> + spi->controller->set_cs(spi, !enable);
> >>>>>>> + }
> >>>>>>>
> >>>>>>> - if (spi_get_csgpiod(spi, 0)) {
> >>>>>>> - if (!(spi->mode & SPI_NO_CS)) {
> >>>>>>> - /*
> >>>>>>> - * Historically ACPI has no means of the GPIO
> >>>>>>> polarity and
> >>>>>>> - * thus the SPISerialBus() resource defines it
> >>>>>> on
> >>>>>>> the per-chip
> >>>>>>> - * basis. In order to avoid a chain of
> >>>>>> negations,
> >>>>>>> the GPIO
> >>>>>>> - * polarity is considered being Active High.
> >>>>>> Even
> >>>>>>> for the cases
> >>>>>>> - * when _DSD() is involved (in the updated
> >>>>>>> versions of ACPI)
> >>>>>>> - * the GPIO CS polarity must be defined
> Active
> >>>>>>> High to avoid
> >>>>>>> - * ambiguity. That's why we use enable, that
> >>>>>>> takes SPI_CS_HIGH
> >>>>>>> - * into account.
> >>>>>>> - */
> >>>>>>> - if (has_acpi_companion(&spi->dev))
> >>>>>>> -
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
> >>>>>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
> >>>>>> ||
> >>>>>>> + !spi->controller->set_cs_timing) {
> >>>>>>> + if (activate)
> >>>>>>> + spi_delay_exec(&spi->cs_setup,
> >> NULL);
> >>>>>>> else
> >>>>>>> - /* Polarity handled by GPIO library */
> >>>>>>> -
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
> >>>>>>> + spi_delay_exec(&spi->cs_inactive,
> >>>>>>> NULL);
> >>>>>>> }
> >>>>>>> - /* Some SPI masters need both GPIO CS &
> slave_select
> >>>>>>> */
> >>>>>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS)
> &&
> >>>>>>> - spi->controller->set_cs)
> >>>>>>> + } else {
> >>>>>>> + /*
> >>>>>>> + * Avoid calling into the driver (or doing delays) if
> >>>>>> the
> >>>>>>> chip select
> >>>>>>> + * isn't actually changing from the last time this was
> >>>>>>> called.
> >>>>>>> + */
> >>>>>>> + if (!force && ((enable && spi->controller->last_cs ==
> >>>>>>> + spi_get_chipselect(spi, cs_num)) ||
> >>>>>>> + (!enable && spi->controller->last_cs
> >>>>>> !=
> >>>>>>> + spi_get_chipselect(spi, cs_num))) &&
> >>>>>>> + (spi->controller->last_cs_mode_high ==
> >>>>>>> + (spi->mode & SPI_CS_HIGH)))
> >>>>>>> + return;
> >>>>>>> +
> >>>>>>> + trace_spi_set_cs(spi, activate);
> >>>>>>> +
> >>>>>>> + spi->controller->last_cs = enable ?
> >>>>>>> spi_get_chipselect(spi, cs_num) : -1;
> >>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
> >>>>>>> SPI_CS_HIGH;
> >>>>>>> +
> >>>>>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>>>>>> set_cs_timing) && !activate)
> >>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
> >>>>>>> +
> >>>>>>> + if (spi->mode & SPI_CS_HIGH)
> >>>>>>> + enable = !enable;
> >>>>>>> +
> >>>>>>> + if (spi_get_csgpiod(spi, cs_num)) {
> >>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
> >>>>>>> + /*
> >>>>>>> + * Historically ACPI has no means of
> >>>>>> the
> >>>>>>> GPIO polarity and
> >>>>>>> + * thus the SPISerialBus() resource
> >>>>>>> defines it on the per-chip
> >>>>>>> + * basis. In order to avoid a chain of
> >>>>>>> negations, the GPIO
> >>>>>>> + * polarity is considered being Active
> >>>>>>> High. Even for the cases
> >>>>>>> + * when _DSD() is involved (in the
> >>>>>>> updated versions of ACPI)
> >>>>>>> + * the GPIO CS polarity must be
> >>>>>> defined
> >>>>>>> Active High to avoid
> >>>>>>> + * ambiguity. That's why we use
> >>>>>> enable,
> >>>>>>> that takes SPI_CS_HIGH
> >>>>>>> + * into account.
> >>>>>>> + */
> >>>>>>> + if (has_acpi_companion(&spi->dev))
> >>>>>>> +
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>>>>>> +
> >>>>>>> !enable);
> >>>>>>> + else
> >>>>>>> + /* Polarity handled by GPIO
> >>>>>>> library */
> >>>>>>> +
> >>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
> >>>>>>> +
> >>>>>>> activate);
> >>>>>>> + }
> >>>>>>> + /* Some SPI masters need both GPIO CS &
> >>>>>>> slave_select */
> >>>>>>> + if ((spi->controller->flags &
> >>>>>>> SPI_MASTER_GPIO_SS) &&
> >>>>>>> + spi->controller->set_cs)
> >>>>>>> + spi->controller->set_cs(spi, !enable);
> >>>>>>> + } else if (spi->controller->set_cs) {
> >>>>>>> spi->controller->set_cs(spi, !enable);
> >>>>>>> - } else if (spi->controller->set_cs) {
> >>>>>>> - spi->controller->set_cs(spi, !enable);
> >>>>>>> - }
> >>>>>>> + }
> >>>>>>>
> >>>>>>> - if (spi_get_csgpiod(spi, 0) ||
> >>>>>> !spi->controller->set_cs_timing) {
> >>>>>>> - if (activate)
> >>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
> >>>>>>> - else
> >>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
> >>>>>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
> >>>>>>>> set_cs_timing) {
> >>>>>>> + if (activate)
> >>>>>>> + spi_delay_exec(&spi->cs_setup,
> >> NULL);
> >>>>>>> + else
> >>>>>>> + spi_delay_exec(&spi->cs_inactive,
> >>>>>>> NULL);
> >>>>>>> + }
> >>>>>>> }
> >>>>>>> }
> >>>>>>>
> >>>>>>> @@ -2246,8 +2325,8 @@ static void
> of_spi_parse_dt_cs_delay(struct
> >>>>>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
> >>>>>>> *ctlr, struct
> >>>>>> spi_device
> >>>>>>> *spi,
> >>>>>>> struct device_node *nc)
> >>>>>>> {
> >>>>>>> - u32 value;
> >>>>>>> - int rc;
> >>>>>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
> >>>>>>> + int rc, idx;
> >>>>>>>
> >>>>>>> /* Mode (clock phase/polarity/etc.) */
> >>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13
> >>>>>>> +2399,21
> >>>>>> @@
> >>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
> >>>>>>> spi_device *spi,
> >>>>>>> }
> >>>>>>>
> >>>>>>> /* Device address */
> >>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
> >>>>>>> - if (rc) {
> >>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
> >> 1,
> >>>>>>> + SPI_CS_CNT_MAX);
> >>>>>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
> >>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
> >>>>>> (%d)\n",
> >>>>>>> nc, rc);
> >>>>>>> return rc;
> >>>>>>> + } else if ((of_property_read_bool(nc, "parallel-memories"))
> >> &&
> >>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
> >>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
> >>>>>> multi
> >>>>>>> CS\n");
> >>>>>>> + return -EINVAL;
> >>>>>>> }
> >>>>>>> - spi_set_chipselect(spi, 0, value);
> >>>>>>> + for (idx = 0; idx < rc; idx++)
> >>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
> >>>>>>> + /* By default set the spi->cs_index_mask as 1 */
> >>>>>>> + spi->cs_index_mask = 0x01;
> >>>>>>>
> >>>>>>> /* Device speed */
> >>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
> >> @@
> >>>>>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device
> >>>>>>> *spi, struct spi_message *message)
> >>>>>>> * cs_change is set for each transfer.
> >>>>>>> */
> >>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
> >>>>>>> SPI_CS_WORD) ||
> >>>>>>> - spi_get_csgpiod(spi, 0))) {
> >>>>>>> + spi_get_csgpiod(spi, 0) ||
> >>>>>>> + spi_get_csgpiod(spi, 1))) {
> >>>>>>> size_t maxsize;
> >>>>>>> int ret;
> >>>>>>>
> >>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
> >>>>>>> index 873ced6ae4ca..6453b246e0af 100644
> >>>>>>> --- a/include/linux/spi/spi.h
> >>>>>>> +++ b/include/linux/spi/spi.h
> >>>>>>> @@ -19,6 +19,11 @@
> >>>>>>> #include <linux/acpi.h>
> >>>>>>> #include <linux/u64_stats_sync.h>
> >>>>>>>
> >>>>>>> +/* Max no. of CS supported per spi device */ #define
> >>>>>>> +SPI_CS_CNT_MAX
> >>>>>>> +2
> >>>>>>> +
> >>>>>>> +/* chip select mask */
> >>>>>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
> >>>>>>> struct dma_chan;
> >>>>>>> struct software_node;
> >>>>>>> struct ptp_system_timestamp;
> >>>>>>> @@ -166,6 +171,7 @@ extern void
> >>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
> >>>>>>> * deasserted. If @cs_change_delay is used from
> >> @spi_transfer,
> >>>>>>> then the
> >>>>>>> * two delays will be added up.
> >>>>>>> * @pcpu_statistics: statistics for the spi_device
> >>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
> >>>>>>> chipselect array
> >>>>>>> *
> >>>>>>> * A @spi_device is used to interchange data between an SPI slave
> >>>>>>> * (usually a discrete chip) and CPU memory.
> >>>>>>> @@ -181,7 +187,7 @@ struct spi_device {
> >>>>>>> struct spi_controller *controller;
> >>>>>>> struct spi_controller *master; /* Compatibility layer
> >>>>>> */
> >>>>>>> u32 max_speed_hz;
> >>>>>>> - u8 chip_select;
> >>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
> >>>>>>> u8 bits_per_word;
> >>>>>>> bool rt;
> >>>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
> >>>>>>> @@ -202,7 +208,7 @@ struct spi_device {
> >>>>>>> void *controller_data;
> >>>>>>> char modalias[SPI_NAME_SIZE];
> >>>>>>> const char *driver_override;
> >>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
> >>>>>> desc
> >>>>>>> */
> >>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
> >>>>>> Chip
> >>>>>>> select gpio desc */
> >>>>>>> struct spi_delay word_delay; /* Inter-word delay */
> >>>>>>> /* CS delays */
> >>>>>>> struct spi_delay cs_setup;
> >>>>>>> @@ -212,6 +218,13 @@ struct spi_device {
> >>>>>>> /* The statistics */
> >>>>>>> struct spi_statistics __percpu *pcpu_statistics;
> >>>>>>>
> >>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
> >>>>>> from
> >>>>>>> + * the chipselect array.When the controller is capable to
> >>>>>> handle
> >>>>>>> + * multiple chip selects & memories are connected in parallel
> >>>>>>> + * then more than one bit need to be set in cs_index_mask.
> >>>>>>> + */
> >>>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
> >>>>>>> +
> >>>>>>> /*
> >>>>>>> * likely need more hooks for more protocol options affecting
> >> how
> >>>>>>> * the controller talks to each chip, like:
> >>>>>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
> >>>>>>> struct spi_device *spi)
> >>>>>>>
> >>>>>>> static inline u8 spi_get_chipselect(const struct spi_device
> >>>>>>> *spi,
> >>>>>> u8 idx)
> >>>>>>> {
> >>>>>>> - return spi->chip_select;
> >>>>>>> + return spi->chip_select[idx];
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline void spi_set_chipselect(struct spi_device *spi,
> >>>>>>> u8
> >>>>>> idx, u8
> >>>>>>> chipselect)
> >>>>>>> {
> >>>>>>> - spi->chip_select = chipselect;
> >>>>>>> + spi->chip_select[idx] = chipselect;
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
> >>>>>> spi_device
> >>>>>>> *spi, u8 idx)
> >>>>>>> {
> >>>>>>> - return spi->cs_gpiod;
> >>>>>>> + return spi->cs_gpiod[idx];
> >>>>>>> }
> >>>>>>>
> >>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
> >>>>>>> idx,
> >>>>>> struct
> >>>>>>> gpio_desc *csgpiod)
> >>>>>>> {
> >>>>>>> - spi->cs_gpiod = csgpiod;
> >>>>>>> + spi->cs_gpiod[idx] = csgpiod;
> >>>>>>> }
> >>>>>>>
> >>>>>>> /**
> >>>>>>> @@ -388,6 +401,8 @@ extern struct spi_device
> >>>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
> >>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
> >>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
> >>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
> >>>>>> exclusive use
> >>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
> >>>>>> assert/de-assert
> >>>>>>> + * more than one chip select at once.
> >>>>>>> * @setup: updates the device mode and clocking records used by
> a
> >>>>>>> * device's SPI controller; protocol code may call this. This
> >>>>>>> * must fail if an unrecognized or unsupported mode is
> >> requested.
> >>>>>>> @@ -554,6 +569,11 @@ struct spi_controller {
> >>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /*
> Requires tx
> >>>>>>> */
> >>>>>>>
> >>>>>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS
> must
> >>>>>> select
> >>>>>>> slave */
> >>>>>>> + /*
> >>>>>>> + * The spi-controller has multi chip select capability and can
> >>>>>>> + * assert/de-assert more than one chip select at once.
> >>>>>>> + */
> >>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
> >>>>>>>
> >>>>>>> /* Flag indicating if the allocation of this struct is devres-
> >>>>>>> managed */
> >>>>>>> bool devm_allocated;
> >>>>>>> --
> >>>>>>> 2.17.1
Hi,
On 02/05/2023 12:40, Mahapatra, Amit Kumar wrote:
> Hello Stefan,
>
>> -----Original Message-----
>> From: Stefan Binding <[email protected]>
>> Sent: Friday, April 28, 2023 7:38 PM
>> To: Mahapatra, Amit Kumar <[email protected]>;
>> [email protected]; [email protected]; [email protected];
>> [email protected]; [email protected]; [email protected];
>> [email protected]
>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>> [email protected]; [email protected];
>> [email protected]; [email protected];
>> [email protected]; Simek, Michal <[email protected]>;
>> [email protected]; [email protected];
>> [email protected]; [email protected]
>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories support
>> in SPI core
>>
>> Hi,
>>
>> On 27/04/2023 18:09, Mahapatra, Amit Kumar wrote:
>>> Hello Stefan,
>>>
>>>> -----Original Message-----
>>>> From: Stefan Binding <[email protected]>
>>>> Sent: Tuesday, April 25, 2023 5:50 PM
>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]; [email protected]; [email protected];
>>>> [email protected]
>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected]; linux-
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected];
>>>> [email protected]; Simek, Michal
>> <[email protected]>;
>>>> [email protected]; [email protected];
>>>> [email protected]; [email protected]
>>>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>> support in SPI core
>>>>
>>>> Hi,
>>>>
>>>> On 20/04/2023 10:04, Mahapatra, Amit Kumar wrote:
>>>>> Hello Stefan,
>>>>>
>>>>>> -----Original Message-----
>>>>>> From: Stefan Binding <[email protected]>
>>>>>> Sent: Wednesday, April 12, 2023 8:33 PM
>>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]; [email protected]; [email protected];
>>>>>> [email protected]
>>>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
>>>>>> linux- [email protected]; [email protected];
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; Simek, Michal
>>>> <[email protected]>;
>>>>>> [email protected]; [email protected];
>>>>>> [email protected]; [email protected]
>>>>>> Subject: Re: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>>>> support in SPI core
>>>>>>
>>>>>> Hi,
>>>>>>
>>>>>> On 11/04/2023 10:07, Mahapatra, Amit Kumar wrote:
>>>>>>> Hello Stefan,
>>>>>>>
>>>>>>>> -----Original Message-----
>>>>>>>> From: Stefan Binding <[email protected]>
>>>>>>>> Sent: Thursday, April 6, 2023 7:14 PM
>>>>>>>> To: Mahapatra, Amit Kumar <[email protected]>;
>>>>>>>> [email protected]; [email protected];
>>>>>>>> [email protected]; [email protected];
>> [email protected];
>>>>>>>> [email protected]; [email protected]
>>>>>>>> Cc: git (AMD-Xilinx) <[email protected]>; [email protected];
>>>>>>>> linux- [email protected]; [email protected];
>>>>>>>> [email protected]; [email protected];
>>>>>>>> [email protected]; Simek, Michal
>>>>>> <[email protected]>;
>>>>>>>> [email protected]; [email protected];
>>>>>>>> [email protected]; [email protected]
>>>>>>>> Subject: RE: [PATCH V7 1/7] spi: Add stacked and parallel
>>>>>>>> memories support in SPI core
>>>>>>>>
>>>>>>>> Hi,
>>>>>>>>
>>>>>>>>> -----Original Message-----
>>>>>>>>> From: Amit Kumar Mahapatra <[email protected]>
>>>>>>>>> Sent: Thursday, April 6, 2023 7:54 AM
>>>>>>>>> To: [email protected]; [email protected];
>>>>>>>>> [email protected]; [email protected];
>>>>>>>>> [email protected]; [email protected]; [email protected]
>>>>>>>>> Cc: [email protected]; [email protected]; linux-
>>>>>>>>> [email protected]; [email protected]; linux-
>>>>>>>>> [email protected]; [email protected];
>>>>>>>>> [email protected]; [email protected];
>>>>>>>>> [email protected]; [email protected];
>>>>>>>>> [email protected]; Amit Kumar Mahapatra <amit.kumar-
>>>>>>>>> [email protected]>
>>>>>>>>> Subject: [PATCH V7 1/7] spi: Add stacked and parallel memories
>>>>>>>> support
>>>>>>>>> in SPI core
>>>>>>>>>
>>>>>>>>> For supporting multiple CS the SPI device need to be aware of
>>>>>>>>> all
>>>>>>>> the CS
>>>>>>>>> values. So, the "chip_select" member in the spi_device structure
>>>>>>>>> is
>>>>>>>> now
>>>>>>>>> an
>>>>>>>>> array that holds all the CS values.
>>>>>>>>>
>>>>>>>>> spi_device structure now has a "cs_index_mask" member. This acts
>>>>>>>>> as
>>>>>>>> an
>>>>>>>>> index to the chip_select array. If nth bit of spi->cs_index_mask
>>>>>>>>> is
>>>>>>>> set
>>>>>>>>> then the driver would assert spi->chip_select[n].
>>>>>>>>>
>>>>>>>>> In parallel mode all the chip selects are asserted/de-asserted
>>>>>>>>> simultaneously and each byte of data is stored in both devices,
>>>>>>>>> the
>>>>>>>> even
>>>>>>>>> bits in one, the odd bits in the other. The split is
>>>>>>>>> automatically
>>>>>>>> handled
>>>>>>>>> by the GQSPI controller. The GQSPI controller supports a maximum
>>>>>>>>> of two flashes connected in parallel mode. A
>>>>>>>>> SPI_CONTROLLER_MULTI_CS flag bit is added in the spi
>>>>>>>>> controntroller flags, through
>>>>>>>>> ctlr->flags the spi
>>>>>>>> core
>>>>>>>>> will make sure that the controller is capable of handling
>>>>>>>>> multiple
>>>>>>>> chip
>>>>>>>>> selects at once.
>>>>>>>>>
>>>>>>>>> For supporting multiple CS via GPIO the cs_gpiod member of the
>>>>>>>>> spi_device structure is now an array that holds the gpio
>>>>>>>>> descriptor for each chipselect.
>>>>>>>>>
>>>>>>>>> Multi CS support using GPIO is not tested due to unavailability
>>>>>>>>> of necessary hardware setup.
>>>>>>>>>
>>>>>>>>> Multi CS configuration with one native CS and one GPIO CS is not
>>>>>>>>> supported as this configuration could not be tested due to
>>>>>>>>> unavailability of necessary hardware setup.
>>>>>>>> I've tested this chain on a released laptop (HP EliteBook 840 G9)
>>>>>>>> which uses SPI to interface to 2 amps, one amp uses a native CS
>>>>>>>> and the other uses a GPIO CS, and I noticed that when using this
>>>>>>>> chain, the second amp no longer works.
>>>>>>> Thank you for testing this patch series on GPIO CS setup. As I
>>>>>>> don't have a GPIO CS setup, is it possible for you debug the
>>>>>>> failure and share more details/logs where the problem is?
>>>>>>>
>>>>>>> Regards,
>>>>>>> Amit
>>>>>> We are willing and able to debug this failure and share the failure logs.
>>>>>> The first issue that I see is a kernel crash when trying to set the GPIO CS:
>>>>>>
>>>>>> [ 2.951658] general protection fault, probably for non-canonical
>>>>>> address
>>>>>> 0xdead000000000122: 0000 [#1] PREEMPT SMP NOPTI [ 2.951771]
>> CPU:
>>>> 9
>>>>>> PID: 379 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #30
>>>>>> [ 2.951826] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02
>>>>>> 10/29/2021 [ 2.951882] RIP:
>>>>>> 0010:gpiod_set_value_cansleep+0x21/0xa0
>>>>>> [ 2.951941] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48
>>>>>> 85 ff
>>>>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff
>>>>>> ff
>>>>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
>>>>>> ee 4c [ 2.952043]
>>>>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 2.952080] RAX:
>>>>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>>>>>> 0000000000000000
>>>>>> [ 2.952124] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>>>>>> dead000000000122
>>>>>> [ 2.952167] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>>>>>> ffffc008c0deb868
>>>>>> [ 2.952211] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>>>>>> dead000000000122
>>>>>> [ 2.952256] R13: 0000000000000001 R14: 0000000000000000 R15:
>>>>>> 0000000000000000
>>>>>> [ 2.952299] FS: 00007f7fa5b5b880(0000)
>>>>>> GS:ffffa0a81f840000(0000)
>>>>>> knlGS:0000000000000000
>>>>>> [ 2.952369] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>>>> 2.952407] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>>>>>> 0000000000770ee0
>>>>>> [ 2.952451] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>>>> 0000000000000000
>>>>>> [ 2.952492] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>>>> 0000000000000400
>>>>>> [ 2.952533] PKRU: 55555554
>>>>>> [ 2.952561] Call Trace:
>>>>>> [ 2.952579] <TASK>
>>>>>> [ 2.952598] spi_set_cs+0x257/0x4a0 [ 2.952630]
>>>>>> spi_setup+0x1a2/0x500 [ 2.952667] __spi_add_device+0x88/0x160 [
>>>>>> 2.952710] spi_add_device+0x60/0x90 [ 2.952738]
>>>>>> smi_spi_probe+0x178/0x370 [serial_multi_instantiate] [ 2.952792]
>>>>>> smi_probe+0xcf/0x110 [serial_multi_instantiate] [ 2.952854]
>>>>>> platform_probe+0x42/0xb0 [ 2.952885] really_probe+0x1b2/0x420 [
>>>>>> 2.952914] __driver_probe_device+0x7e/0x180 [ 2.952947]
>>>>>> driver_probe_device+0x23/0xa0 [ 2.952993]
>>>>>> __driver_attach+0xe4/0x1e0 [ 2.953021] ?
>>>>>> __pfx___driver_attach+0x10/0x10
>>>>>> [ 2.953061] bus_for_each_dev+0x7a/0xd0 [ 2.953088]
>>>>>> driver_attach+0x1e/0x30 [ 2.953123] bus_add_driver+0x11c/0x220
>>>>>> [ 2.953150] driver_register+0x64/0x130 [ 2.953174] ?
>>>>>> __pfx_init_module+0x10/0x10 [serial_multi_instantiate] [
>>>>>> 2.953221]
>>>>>> __platform_driver_register+0x1e/0x30
>>>>>> [ 2.953251] smi_driver_init+0x1c/0xff0
>>>>>> [serial_multi_instantiate] [ 2.953310] do_one_initcall+0x46/0x220
>> [ 2.953339] ?
>>>>>> kmalloc_trace+0x2a/0xa0 [ 2.953375] do_init_module+0x52/0x220 [
>>>>>> 2.953411] load_module+0x223c/0x2460 [ 2.953450]
>>>>>> __do_sys_finit_module+0xc8/0x140 [ 2.953479] ?
>>>>>> __do_sys_finit_module+0xc8/0x140
>>>>>> [ 2.953510] __x64_sys_finit_module+0x18/0x20 [ 2.953538]
>>>>>> do_syscall_64+0x38/0x90 [ 2.953574]
>>>>>> entry_SYSCALL_64_after_hwframe+0x72/0xdc
>>>>>> [ 2.953606] RIP: 0033:0x7f7fa5d7476d [ 2.953639] Code: 00 c3
>>>>>> 66 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
>>>>>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24
>>>>>> 08 0f
>>>>>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
>>>>>> 48 [ 2.953739] RSP: 002b:00007fff1f8dd3b8 EFLAGS: 00000246
>>>> ORIG_RAX:
>>>>>> 0000000000000139
>>>>>> [ 2.956833] RAX: ffffffffffffffda RBX: 000055d648654ab0 RCX:
>>>>>> 00007f7fa5d7476d
>>>>>> [ 2.959202] RDX: 0000000000000000 RSI: 00007f7fa5c54ded RDI:
>>>>>> 0000000000000006
>>>>>> [ 2.961542] RBP: 0000000000020000 R08: 0000000000000000 R09:
>>>>>> 0000000000000000
>>>>>> [ 2.964312] R10: 0000000000000006 R11: 0000000000000246 R12:
>>>>>> 00007f7fa5c54ded
>>>>>> [ 2.966694] R13: 0000000000000000 R14: 000055d6483f41a0 R15:
>>>>>> 000055d648654ab0
>>>>>> [ 2.967668] resource: resource sanity check: requesting [mem
>>>>>> 0x00000000fedc0000-0x00000000fedcffff], which spans more than pnp
>>>>>> 00:04 [mem 0xfedc0000-0xfedc7fff] [ 2.968998] </TASK> [
>>>>>> 2.971615] caller
>>>>>> igen6_probe+0x178/0x8e0 [igen6_edac] mapping multiple BARs [
>>>>>> 2.975014] Modules linked in: igen6_edac(+) fjes(-)
>>>>>> serial_multi_instantiate(+) int3403_thermal sch_fq_codel
>>>>>> int340x_thermal_zone int3400_thermal intel_hid acpi_thermal_rel
>>>>>> acpi_tad sparse_keymap acpi_pad mac_hid msr parport_pc ppdev lp
>>>>>> parport drm ramoops reed_solomon efi_pstore ip_tables x_tables
>>>>>> autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core nvme
>>>> intel_lpss_pci
>>>>>> intel_lpss crc32_pclmul thunderbolt i2c_i801 xhci_pci idma64
>>>>>> nvme_core i2c_smbus virt_dma xhci_pci_renesas video wmi
>>>>>> pinctrl_tigerlake [ 2.987901] ---[ end trace 0000000000000000
>>>>>> ]---
>>>> [ 3.157030] RIP:
>>>>>> 0010:gpiod_set_value_cansleep+0x21/0xa0
>>>>>> [ 3.159077] Code: 90 90 90 90 90 90 90 90 90 0f 1f 44 00 00 48
>>>>>> 85 ff
>>>>>> 74 3e 55 48 89 e5 41 55 41 89 f5 41 54 49 89 fc 48 81 ff 00 f0 ff
>>>>>> ff
>>>>>> 77 2c <48> 8b 3f 48 85 ff 74 53 48 83 bf 68 03 00 00 00 74 34 44 89
>>>>>> ee 4c [ 3.161461]
>>>>>> RSP: 0018:ffffc008c0deb928 EFLAGS: 00010287 [ 3.164005] RAX:
>>>>>> 0000000000000001 RBX: ffffa0a489534c00 RCX:
>>>>>> 0000000000000000
>>>>>> [ 3.166354] RDX: dead000000000122 RSI: 0000000000000001 RDI:
>>>>>> dead000000000122
>>>>>> [ 3.168499] RBP: ffffc008c0deb938 R08: 0000000000000000 R09:
>>>>>> ffffc008c0deb868
>>>>>> [ 3.170609] R10: ffffffffffffffff R11: 00000000000000b0 R12:
>>>>>> dead000000000122
>>>>>> [ 3.172893] R13: 0000000000000001 R14: 0000000000000000 R15:
>>>>>> 0000000000000000
>>>>>> [ 3.175335] FS: 00007f7fa5b5b880(0000)
>>>>>> GS:ffffa0a81f840000(0000)
>>>>>> knlGS:0000000000000000
>>>>>> [ 3.180434] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>>>> 3.183356] CR2: 000055d648427100 CR3: 000000010e960003 CR4:
>>>>>> 0000000000770ee0
>>>>>> [ 3.185107] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>>>> 0000000000000000
>>>>>> [ 3.186840] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>>>> 0000000000000400
>>>>>> [ 3.188647] PKRU: 55555554
>>>>> Thank you for sharing the logs.
>>>>> As per our analysis the spi->cs_gpiod[0] is getting messed up while
>>>>> setting it in __spi_add_device( ).
>>>>> Is it possible for you to do the following changes on top of this
>>>>> patch series & re-run your test.
>>>>>
>>>>> After applying this patch series, in drivers/spi/spi.c file replace
>>>>> the following code snippet in __spi_add_device( ) function defination.
>>>>>
>>>>> if (ctlr->cs_gpiods) {
>>>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>> spi_set_csgpiod(spi, idx,
>>>>> ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
>>>>>
>>>>> with the below code snippet
>>>>>
>>>>> if (ctlr->cs_gpiods) {
>>>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>> if (!(idx != 0 && !spi_get_chipselect(spi, idx)))
>>>>> spi_set_csgpiod(spi, idx, ctlr-
>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>>>> }
>>>>> }
>>>>>
>>>>> then re-run your test.
>>>>>
>>>>> Regards,
>>>>> Amit
>>>> I'm still seeing a crash on probe:
>>>>
>>>> [ 3.265683] BUG: unable to handle page fault for address:
>>>> 00000000fffedfdd
>>>> [ 3.265744] #PF: supervisor read access in kernel mode [ 3.265781] #PF:
>>>> error_code(0x0000) - not-present page [ 3.265817] PGD 0 P4D 0 [
>>>> 3.265840] Oops: 0000 [#1] PREEMPT SMP NOPTI [ 3.265865] CPU: 4 PID:
>>>> 385 Comm: systemd-udevd Tainted: G A 6.3.0-rc3+ #32 [
>>>> 3.265910] Hardware name: HP /896D, BIOS U70 Ver. 89.33.02 10/29/2021
>>>> [ 3.265956]
>>>> RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
>>>> [ 3.266007] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48
>>>> 2b
>>>> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48
>>>> 89
>>>> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d
>>>> 5d [ 3.266092] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [
>>>> 3.266121]
>>>> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
>>>> cccccccccccccccd
>>>> [ 3.266156] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
>>>> ffff9c8d4a5f6d40
>>>> [ 3.266192] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
>>>> 0000000000000000
>>>> [ 3.266228] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
>>>> 00000000fffedf7d
>>>> [ 3.266264] R13: 0000000000000000 R14: 0000000000000001 R15:
>>>> 0000000000000001
>>>> [ 3.266299] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
>>>> knlGS:0000000000000000
>>>> [ 3.266358] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>> 3.266388] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
>>>> 0000000000770ee0
>>>> [ 3.266422] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>> 0000000000000000
>>>> [ 3.266457] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>> 0000000000000400
>>>> [ 3.266490] PKRU: 55555554
>>>> [ 3.266513] Call Trace:
>>>> [ 3.266530] <TASK>
>>>> [ 3.266546] gpiod_set_value_nocheck+0x5b/0x70 [ 3.266583]
>>>> gpiod_set_value_cansleep+0x3e/0xa0
>>>> [ 3.266609] spi_set_cs+0x257/0x4a0 [ 3.266634]
>>>> spi_transfer_one_message+0x49/0x740
>>>> [ 3.266672] __spi_pump_transfer_message+0x29b/0x620
>>>> [ 3.266712] __spi_sync+0x26f/0x3b0 [ 3.266735]
>>>> spi_write_then_read+0x157/0x210 [ 3.266771] ?
>>>> psi_group_change+0x175/0x3b0
>> [ 3.266802] regmap_spi_read+0xe/0x20
>>>> [ 3.266826] _regmap_raw_read+0xe1/0x210 [ 3.266861]
>>>> _regmap_bus_read+0x3a/0x70 [ 3.266887] _regmap_read+0x66/0x140
>> [
>>>> 3.266918] regmap_read+0x3f/0x70 [ 3.266957]
>>>> cs35l41_hda_probe+0x553/0xc10 [snd_hda_scodec_cs35l41]
>> [ 3.267027]
>>>> cs35l41_hda_spi_probe+0x62/0x80 [snd_hda_scodec_cs35l41_spi] [
>>>> 3.267096] spi_probe+0x55/0x90 [ 3.267145]
>>>> really_probe+0x1b2/0x420 [ 3.267184]
>>>> __driver_probe_device+0x7e/0x180 [ 3.267227]
>>>> driver_probe_device+0x23/0xa0 [ 3.267287]
>>>> __driver_attach+0xe4/0x1e0 [ 3.267326] ?
>>>> __pfx___driver_attach+0x10/0x10
>>>> [ 3.267381] bus_for_each_dev+0x7a/0xd0 [ 3.267406]
>>>> driver_attach+0x1e/0x30 [ 3.267437] bus_add_driver+0x11c/0x220 [
>>>> 3.267461] driver_register+0x64/0x130 [ 3.267483] ?
>>>> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi] [
>>>> 3.267525] __spi_register_driver+0xa1/0xd0 [ 3.270712] ?
>>>> __pfx_init_module+0x10/0x10 [snd_hda_scodec_cs35l41_spi] [
>>>> 3.273446] cs35l41_spi_driver_init+0x1c/0xff0
>>>> [snd_hda_scodec_cs35l41_spi]
>>>> [ 3.275119] do_one_initcall+0x46/0x220 [ 3.276828] ?
>>>> kmalloc_trace+0x2a/0xa0 [ 3.279290] do_init_module+0x52/0x220 [
>>>> 3.283593] load_module+0x223c/0x2460 [ 3.283602]
>>>> __do_sys_finit_module+0xc8/0x140 [ 3.287883] ?
>>>> __do_sys_finit_module+0xc8/0x140
>>>> [ 3.287907] __x64_sys_finit_module+0x18/0x20 [ 3.293156]
>>>> do_syscall_64+0x38/0x90 [ 3.298937]
>>>> entry_SYSCALL_64_after_hwframe+0x72/0xdc
>>>> [ 3.298945] RIP: 0033:0x7f98d06f776d [ 3.319574] Code: 00 c3 66
>>>> 2e 0f 1f 84 00 00 00 00 00 90 f3 0f 1e fa
>>>> 48 89 f8 48 89 f7 48 89 d6 48 89 ca 4d 89 c2 4d 89 c8 4c 8b 4c 24 08
>>>> 0f
>>>> 05 <48> 3d 01 f0 ff ff 73 01 c3 48 8b 0d f3 36 0d 00 f7 d8 64 89 01
>>>> 48 [ 3.319579] RSP: 002b:00007ffd988f7a08 EFLAGS: 00000246
>> ORIG_RAX:
>>>> 0000000000000139
>>>> [ 3.319585] RAX: ffffffffffffffda RBX: 000055af06a7d030 RCX:
>>>> 00007f98d06f776d
>>>> [ 3.319589] RDX: 0000000000000000 RSI: 00007f98d05d7ded RDI:
>>>> 0000000000000013
>>>> [ 3.329520] RBP: 0000000000020000 R08: 0000000000000000 R09:
>>>> 0000000000000000
>>>> [ 3.329523] R10: 0000000000000013 R11: 0000000000000246 R12:
>>>> 00007f98d05d7ded
>>>> [ 3.329525] R13: 0000000000000000 R14: 000055af06cdd040 R15:
>>>> 000055af06a7d030
>>>> [ 3.329531] </TASK>
>>>> [ 3.329533] Modules linked in: snd_hda_intel(+) ttm
>>>> snd_intel_dspcfg btusb rapl snd_seq_midi snd_intel_sdw_acpi libarc4
>>>> intel_cstate binfmt_misc
>>>> uvcvideo(+) snd_seq_midi_event btrtl
>>>> snd_hda_scodec_cs35l41_spi(+) snd_hda_codec drm_display_helper
>>>> cdc_ncm(+) videobuf2_vmalloc snd_rawmidi btbcm uvc cdc_ether cec
>>>> btintel videobuf2_memops snd_hda_scodec_cs35l41_i2c snd_hda_core
>>>> videobuf2_v4l2 uas usbnet rc_core snd_hwdep btmtk
>>>> snd_hda_scodec_cs35l41 input_leds mii wmi_bmof videodev snd_seq
>>>> processor_thermal_device_pci bluetooth iwlwifi drm_kms_helper
>> snd_pcm
>>>> snd_hda_cs_dsp_ctls processor_thermal_device mei_me
>> videobuf2_common
>>>> snd_seq_device i2c_algo_bit cs_dsp processor_thermal_rfim
>>>> ecdh_generic usb_storage serio_raw mc syscopyarea ecc
>>>> processor_thermal_mbox ucsi_acpi snd_soc_cs35l41_lib 8250_dw mei
>>>> snd_timer cfg80211 sysfillrect typec_ucsi processor_thermal_rapl
>>>> igen6_edac sysimgblt intel_rapl_common typec snd soundcore
>>>> int3403_thermal int340x_thermal_zone serial_multi_instantiate
>>>> int3400_thermal intel_hid acpi_thermal_rel [ 3.338475]
>>>> sparse_keymap acpi_tad acpi_pad mac_hid sch_fq_codel msr parport_pc
>>>> ppdev lp parport drm ramoops reed_solomon efi_pstore ip_tables
>>>> x_tables autofs4 spi_pxa2xx_platform dw_dmac dw_dmac_core
>>>> intel_lpss_pci nvme intel_lpss i2c_i801 idma64 crc32_pclmul
>>>> thunderbolt i2c_smbus nvme_core xhci_pci virt_dma xhci_pci_renesas
>>>> video wmi pinctrl_tigerlake [ 3.338514]
>>>> CR2: 00000000fffedfdd [ 3.338517] ---[ end trace 0000000000000000
>>>> ]--- [ 3.504965] RIP: 0010:gpiod_set_raw_value_commit+0x3d/0xf0
>>>> [ 3.504973] Code: 48 89 e5 41 55 44 0f b6 ee 41 54 53 48 8b 17 48
>>>> 2b
>>>> 82 70 03 00 00 4c 8b a2 68 03 00 00 48 c1 f8 03 48 0f af c1 66 90 48
>>>> 89
>>>> c6 <49> 8b 44 24 60 44 89 ea 4c 89 e7 ff d0 0f 1f 00 5b 41 5c 41 5d
>>>> 5d [ 3.504975] RSP: 0018:ffffaad780f6f620 EFLAGS: 00010a03 [
>>>> 3.504978]
>>>> RAX: 333330b6bdbad102 RBX: ffff9c8d4a5f6800 RCX:
>>>> cccccccccccccccd
>>>> [ 3.504979] RDX: ffff9c8d4a5f6d40 RSI: 333330b6bdbad102 RDI:
>>>> ffff9c8d4a5f6d40
>>>> [ 3.504980] RBP: ffffaad780f6f638 R08: 00000001018c3789 R09:
>>>> 0000000000000000
>>>> [ 3.504982] R10: ffff9c8c4009ee40 R11: 0000000000000000 R12:
>>>> 00000000fffedf7d
>>>> [ 3.504983] R13: 0000000000000000 R14: 0000000000000001 R15:
>>>> 0000000000000001
>>>> [ 3.504984] FS: 00007f98d04de880(0000) GS:ffff9c90df700000(0000)
>>>> knlGS:0000000000000000
>>>> [ 3.504986] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [
>>>> 3.504988] CR2: 00000000fffedfdd CR3: 000000010b680003 CR4:
>>>> 0000000000770ee0
>>>> [ 3.504989] DR0: 0000000000000000 DR1: 0000000000000000 DR2:
>>>> 0000000000000000
>>>> [ 3.504990] DR3: 0000000000000000 DR6: 00000000ffff07f0 DR7:
>>>> 0000000000000400
>>>> [ 3.504992] PKRU: 55555554
>>>>
>>>> Thanks,
>>>> Stefan
>>> Thanks for the logs.
>>>
>>> Could you please confirm that your test case was passing with
>>>
>> https://github.com/torvalds/linux/commit/303feb3cc06ac0665d0ee9c14149
>> 4
>>> 1200e60e8a3 patch but it is failing with the current patch series ?
>> I retested with the latest master kernel
>> https://github.com/torvalds/linux/commit/33afd4b76393627477e878b3b195
>> d606e585d816
>> and I could see it worked fine. I attached a dmesg log of this.
>>
>> That particular commit id you posted does not work, due to a different issue
>> which was fixed in a later commit.
> Thank you for the confirmation.
>>> Regarding the failure
>>> The logs suggest that we are trying to access an invalid pointer while
>>> calling the gpiod_set_value_cansleep( ) API.
>>> This could be possible if the cs_num is corrupted and we are trying to
>>> access an invalid spi->cs_gpiod[ ].
>>> To confirm the same could you please do the following changes in the
>>> code and re-test.
>>>
>>> After applying this patch series, in drivers/spi/spi.c file replace
>>> the following code snippet in __spi_add_device( ) function definition.
>>> if (ctlr->cs_gpiods) {
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>> spi_set_csgpiod(spi, idx,
>>> ctlr->cs_gpiods[spi_get_chipselect(spi, idx)]); }
>>>
>>> with the below code snippet
>>>
>>> if (ctlr->cs_gpiods) {
>>> for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>> if (!(idx != 0 && !spi_get_chipselect(spi, idx))) {
>>> printk("%s( ) [%d] cs[%d] = [%d]\n", __func__, __LINE__, idx,
>> spi_get_chipselect(spi, idx));
>>> spi_set_csgpiod(spi, idx, ctlr-
>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>> }
>>> }
>>> }
>>>
>>> And at the start of spi_set_cs( ) function in drivers/spi/spi.c file
>>> add the following print statements.
>>>
>>> printk("%s( ) [%d] spi->cs_index_mask == [%d]\n", __func__, __LINE__,
>>> spi->cs_index_mask); printk("%s( ) [%d] cs_num == [%d]\n", __func__,
>>> __LINE__, cs_num);
>> I've attached dmesg log of this. It no longer crashes when using the prints (I
>> am unsure why), but it still does not work.
>> For sanity, I retested these changes with the print lines commented out, and
>> the crash returned.
> Thanks a lot for the dmesg log.
> Here the __ffs() is creating the issue. __ffs() behavior is undefined if
> no set bits exist in spi->cs_index_mask , as a result random value
> (i.e, 64) is assigned to cs_num.
> I think this could be fixed by replacing __ffs() with ffs() calls.
> To confirm the same could you please apply the attached patch on top of
> this patch series and re-test. If it works fine, then for sanity kindly
> rerun by removing the printk lines.
I tested the patch (with and without the prints) on a number of systems
we have
which use multiple SPI Chip Select GPIOs, and it looks like with this
patch, they
are all working now.
Thanks,
Stefan
>
> Thanks,
> Amit
>
>>> Thanks,
>>> Amit
>>>>>> Thanks,
>>>>>>
>>>>>> Stefan
>>>>>>
>>>>>>>> Thanks,
>>>>>>>> Stefan Binding
>>>>>>>>
>>>>>>>>> Signed-off-by: Amit Kumar Mahapatra <amit.kumar-
>>>>>>>> [email protected]>
>>>>>>>>> ---
>>>>>>>>> drivers/spi/spi.c | 226
>>>>>>>> ++++++++++++++++++++++++++++------------
>>>>>>>>> include/linux/spi/spi.h | 32 ++++--
>>>>>>>>> 2 files changed, 183 insertions(+), 75 deletions(-)
>>>>>>>>>
>>>>>>>>> diff --git a/drivers/spi/spi.c b/drivers/spi/spi.c index
>>>>>>>>> 9036d7a50674..04d7322170c4 100644
>>>>>>>>> --- a/drivers/spi/spi.c
>>>>>>>>> +++ b/drivers/spi/spi.c
>>>>>>>>> @@ -612,10 +612,24 @@ static int spi_dev_check(struct device
>> *dev,
>>>>>>>>> void *data) {
>>>>>>>>> struct spi_device *spi = to_spi_device(dev);
>>>>>>>>> struct spi_device *new_spi = data;
>>>>>>>>> + int idx, nw_idx;
>>>>>>>>>
>>>>>>>>> - if (spi->controller == new_spi->controller &&
>>>>>>>>> - spi_get_chipselect(spi, 0) == spi_get_chipselect(new_spi,
>>>>>>>> 0))
>>>>>>>>> - return -EBUSY;
>>>>>>>>> + if (spi->controller == new_spi->controller) {
>>>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>>>> + for (nw_idx = 0; nw_idx < SPI_CS_CNT_MAX;
>>>>>>>>> nw_idx++) {
>>>>>>>>> + if ((idx != 0 &&
>>>>>>>> !spi_get_chipselect(spi,
>>>>>>>>> idx)) ||
>>>>>>>>> + (nw_idx != 0 &&
>>>>>>>>> !spi_get_chipselect(spi, nw_idx))) {
>>>>>>>>> + continue;
>>>>>>>>> + } else if (spi_get_chipselect(spi,
>>>>>>>> idx) ==
>>>>>>>>> + spi_get_chipselect(new_spi,
>>>>>>>> nw_idx))
>>>>>>>>> {
>>>>>>>>> + dev_err(dev,
>>>>>>>>> + "chipselect %d
>>>> already
>>>>>>>>> in use\n",
>>>>>>>>> +
>>>>>>>>> spi_get_chipselect(new_spi, nw_idx));
>>>>>>>>> + return -EBUSY;
>>>>>>>>> + }
>>>>>>>>> + }
>>>>>>>>> + }
>>>>>>>>> + }
>>>>>>>>> return 0;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> @@ -629,7 +643,7 @@ static int __spi_add_device(struct spi_device
>>>>>>>>> *spi)
>>>>>>>>> {
>>>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>>>> - int status;
>>>>>>>>> + int status, idx;
>>>>>>>>>
>>>>>>>>> /*
>>>>>>>>> * We need to make sure there's no other device with this
>>>> @@
>>>>>>>>> -638,8
>>>>>>>>> +652,6 @@ static int __spi_add_device(struct spi_device
>>>>>>>>> *spi)
>>>>>>>>> */
>>>>>>>>> status = bus_for_each_dev(&spi_bus_type, NULL, spi,
>>>>>>>> spi_dev_check);
>>>>>>>>> if (status) {
>>>>>>>>> - dev_err(dev, "chipselect %d already in use\n",
>>>>>>>>> - spi_get_chipselect(spi, 0));
>>>>>>>>> return status;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> @@ -649,8 +661,10 @@ static int __spi_add_device(struct
>> spi_device
>>>>>>>>> *spi)
>>>>>>>>> return -ENODEV;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> - if (ctlr->cs_gpiods)
>>>>>>>>> - spi_set_csgpiod(spi, 0, ctlr-
>>>>>>>>>> cs_gpiods[spi_get_chipselect(spi, 0)]);
>>>>>>>>> + if (ctlr->cs_gpiods) {
>>>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++)
>>>>>>>>> + spi_set_csgpiod(spi, idx, ctlr-
>>>>>>>>>> cs_gpiods[spi_get_chipselect(spi, idx)]);
>>>>>>>>> + }
>>>>>>>>>
>>>>>>>>> /*
>>>>>>>>> * Drivers may modify this initial i/o setup, but will @@
>>>>>>>>> -690,13
>>>>>>>>> +704,15 @@ int spi_add_device(struct spi_device *spi) {
>>>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>>>> - int status;
>>>>>>>>> + int status, idx;
>>>>>>>>>
>>>>>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>>>>>> spi_get_chipselect(spi, 0),
>>>>>>>>> - ctlr->num_chipselect);
>>>>>>>>> - return -EINVAL;
>>>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>>>>>> ctlr->num_chipselect) {
>>>>>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>>>>>> spi_get_chipselect(spi, idx),
>>>>>>>>> + ctlr->num_chipselect);
>>>>>>>>> + return -EINVAL;
>>>>>>>>> + }
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> /* Set the bus ID string */
>>>>>>>>> @@ -713,12 +729,15 @@ static int spi_add_device_locked(struct
>>>>>>>>> spi_device *spi) {
>>>>>>>>> struct spi_controller *ctlr = spi->controller;
>>>>>>>>> struct device *dev = ctlr->dev.parent;
>>>>>>>>> + int idx;
>>>>>>>>>
>>>>>>>>> - /* Chipselects are numbered 0..max; validate. */
>>>>>>>>> - if (spi_get_chipselect(spi, 0) >= ctlr->num_chipselect) {
>>>>>>>>> - dev_err(dev, "cs%d >= max %d\n",
>>>>>>>>> spi_get_chipselect(spi, 0),
>>>>>>>>> - ctlr->num_chipselect);
>>>>>>>>> - return -EINVAL;
>>>>>>>>> + for (idx = 0; idx < SPI_CS_CNT_MAX; idx++) {
>>>>>>>>> + /* Chipselects are numbered 0..max; validate. */
>>>>>>>>> + if (spi_get_chipselect(spi, idx) >=
>>>>>>>> ctlr->num_chipselect) {
>>>>>>>>> + dev_err(dev, "cs%d >= max %d\n",
>>>>>>>>> spi_get_chipselect(spi, idx),
>>>>>>>>> + ctlr->num_chipselect);
>>>>>>>>> + return -EINVAL;
>>>>>>>>> + }
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> /* Set the bus ID string */
>>>>>>>>> @@ -966,58 +985,118 @@ static void spi_res_release(struct
>>>>>>>>> spi_controller *ctlr, struct spi_message *mes static void
>>>>>>>>> spi_set_cs(struct spi_device *spi, bool enable, bool
>>>>>>>> force)
>>>>>>>>> {
>>>>>>>>> bool activate = enable;
>>>>>>>>> + u32 cs_num = __ffs(spi->cs_index_mask);
>>>>>>>>> + int idx;
>>>>>>>>>
>>>>>>>>> /*
>>>>>>>>> - * Avoid calling into the driver (or doing delays) if the chip
>>>>>>>> select
>>>>>>>>> - * isn't actually changing from the last time this was called.
>>>>>>>>> + * In parallel mode all the chip selects are
>>>>>>>> asserted/de-asserted
>>>>>>>>> + * at once
>>>>>>>>> */
>>>>>>>>> - if (!force && ((enable && spi->controller->last_cs ==
>>>>>>>>> spi_get_chipselect(spi, 0)) ||
>>>>>>>>> - (!enable && spi->controller->last_cs !=
>>>>>>>>> spi_get_chipselect(spi, 0))) &&
>>>>>>>>> - (spi->controller->last_cs_mode_high == (spi->mode &
>>>>>>>>> SPI_CS_HIGH)))
>>>>>>>>> - return;
>>>>>>>>> -
>>>>>>>>> - trace_spi_set_cs(spi, activate);
>>>>>>>>> -
>>>>>>>>> - spi->controller->last_cs = enable ? spi_get_chipselect(spi, 0)
>>>>>>>> : -1;
>>>>>>>>> - spi->controller->last_cs_mode_high = spi->mode &
>>>>>>>>> SPI_CS_HIGH;
>>>>>>>>> -
>>>>>>>>> - if ((spi_get_csgpiod(spi, 0) ||
>>>>>>>> !spi->controller->set_cs_timing)
>>>>>>>>> && !activate)
>>>>>>>>> - spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>>>> -
>>>>>>>>> - if (spi->mode & SPI_CS_HIGH)
>>>>>>>>> - enable = !enable;
>>>>>>>>> + if ((spi->cs_index_mask & SPI_PARALLEL_CS_MASK) ==
>>>>>>>>> SPI_PARALLEL_CS_MASK) {
>>>>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>>>>>> SPI_CS_HIGH;
>>>>>>>>> +
>>>>>>>>> + if ((spi_get_csgpiod(spi, 0) || !spi->controller-
>>>>>>>>>> set_cs_timing) && !activate)
>>>>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>>>> +
>>>>>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>>>>>> + enable = !enable;
>>>>>>>>> +
>>>>>>>>> + if (spi_get_csgpiod(spi, 0) && spi_get_csgpiod(spi,
>>>>>>>> 1)) {
>>>>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>>>>>> + /*
>>>>>>>>> + * Historically ACPI has no means of
>>>>>>>> the
>>>>>>>>> GPIO polarity and
>>>>>>>>> + * thus the SPISerialBus() resource
>>>>>>>>> defines it on the per-chip
>>>>>>>>> + * basis. In order to avoid a chain of
>>>>>>>>> negations, the GPIO
>>>>>>>>> + * polarity is considered being Active
>>>>>>>>> High. Even for the cases
>>>>>>>>> + * when _DSD() is involved (in the
>>>>>>>>> updated versions of ACPI)
>>>>>>>>> + * the GPIO CS polarity must be
>>>>>>>> defined
>>>>>>>>> Active High to avoid
>>>>>>>>> + * ambiguity. That's why we use
>>>>>>>> enable,
>>>>>>>>> that takes SPI_CS_HIGH
>>>>>>>>> + * into account.
>>>>>>>>> + */
>>>>>>>>> + if (has_acpi_companion(&spi->dev)) {
>>>>>>>>> + for (idx = 0; idx <
>>>>>>>>> SPI_CS_CNT_MAX; idx++)
>>>>>>>>> +
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>>>> +
>>>>>>>>> !enable);
>>>>>>>>> + } else {
>>>>>>>>> + for (idx = 0; idx <
>>>>>>>>> SPI_CS_CNT_MAX; idx++)
>>>>>>>>> + /* Polarity handled by
>>>>>>>>> GPIO library */
>>>>>>>>> +
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, idx),
>>>>>>>>> +
>>>>>>>>> activate);
>>>>>>>>> + }
>>>>>>>>> + }
>>>>>>>>> + /* Some SPI masters need both GPIO CS &
>>>>>>>>> slave_select */
>>>>>>>>> + if ((spi->controller->flags &
>>>>>>>>> SPI_MASTER_GPIO_SS) &&
>>>>>>>>> + spi->controller->set_cs)
>>>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>>>> + } else if (spi->controller->set_cs) {
>>>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>>>> + }
>>>>>>>>>
>>>>>>>>> - if (spi_get_csgpiod(spi, 0)) {
>>>>>>>>> - if (!(spi->mode & SPI_NO_CS)) {
>>>>>>>>> - /*
>>>>>>>>> - * Historically ACPI has no means of the GPIO
>>>>>>>>> polarity and
>>>>>>>>> - * thus the SPISerialBus() resource defines it
>>>>>>>> on
>>>>>>>>> the per-chip
>>>>>>>>> - * basis. In order to avoid a chain of
>>>>>>>> negations,
>>>>>>>>> the GPIO
>>>>>>>>> - * polarity is considered being Active High.
>>>>>>>> Even
>>>>>>>>> for the cases
>>>>>>>>> - * when _DSD() is involved (in the updated
>>>>>>>>> versions of ACPI)
>>>>>>>>> - * the GPIO CS polarity must be defined
>> Active
>>>>>>>>> High to avoid
>>>>>>>>> - * ambiguity. That's why we use enable, that
>>>>>>>>> takes SPI_CS_HIGH
>>>>>>>>> - * into account.
>>>>>>>>> - */
>>>>>>>>> - if (has_acpi_companion(&spi->dev))
>>>>>>>>> -
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), !enable);
>>>>>>>>> + if (spi_get_csgpiod(spi, 0) || spi_get_csgpiod(spi, 1)
>>>>>>>> ||
>>>>>>>>> + !spi->controller->set_cs_timing) {
>>>>>>>>> + if (activate)
>>>>>>>>> + spi_delay_exec(&spi->cs_setup,
>>>> NULL);
>>>>>>>>> else
>>>>>>>>> - /* Polarity handled by GPIO library */
>>>>>>>>> -
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, 0), activate);
>>>>>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>>>>>> NULL);
>>>>>>>>> }
>>>>>>>>> - /* Some SPI masters need both GPIO CS &
>> slave_select
>>>>>>>>> */
>>>>>>>>> - if ((spi->controller->flags & SPI_MASTER_GPIO_SS)
>> &&
>>>>>>>>> - spi->controller->set_cs)
>>>>>>>>> + } else {
>>>>>>>>> + /*
>>>>>>>>> + * Avoid calling into the driver (or doing delays) if
>>>>>>>> the
>>>>>>>>> chip select
>>>>>>>>> + * isn't actually changing from the last time this was
>>>>>>>>> called.
>>>>>>>>> + */
>>>>>>>>> + if (!force && ((enable && spi->controller->last_cs ==
>>>>>>>>> + spi_get_chipselect(spi, cs_num)) ||
>>>>>>>>> + (!enable && spi->controller->last_cs
>>>>>>>> !=
>>>>>>>>> + spi_get_chipselect(spi, cs_num))) &&
>>>>>>>>> + (spi->controller->last_cs_mode_high ==
>>>>>>>>> + (spi->mode & SPI_CS_HIGH)))
>>>>>>>>> + return;
>>>>>>>>> +
>>>>>>>>> + trace_spi_set_cs(spi, activate);
>>>>>>>>> +
>>>>>>>>> + spi->controller->last_cs = enable ?
>>>>>>>>> spi_get_chipselect(spi, cs_num) : -1;
>>>>>>>>> + spi->controller->last_cs_mode_high = spi->mode &
>>>>>>>>> SPI_CS_HIGH;
>>>>>>>>> +
>>>>>>>>> + if ((spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>>>>>> set_cs_timing) && !activate)
>>>>>>>>> + spi_delay_exec(&spi->cs_hold, NULL);
>>>>>>>>> +
>>>>>>>>> + if (spi->mode & SPI_CS_HIGH)
>>>>>>>>> + enable = !enable;
>>>>>>>>> +
>>>>>>>>> + if (spi_get_csgpiod(spi, cs_num)) {
>>>>>>>>> + if (!(spi->mode & SPI_NO_CS)) {
>>>>>>>>> + /*
>>>>>>>>> + * Historically ACPI has no means of
>>>>>>>> the
>>>>>>>>> GPIO polarity and
>>>>>>>>> + * thus the SPISerialBus() resource
>>>>>>>>> defines it on the per-chip
>>>>>>>>> + * basis. In order to avoid a chain of
>>>>>>>>> negations, the GPIO
>>>>>>>>> + * polarity is considered being Active
>>>>>>>>> High. Even for the cases
>>>>>>>>> + * when _DSD() is involved (in the
>>>>>>>>> updated versions of ACPI)
>>>>>>>>> + * the GPIO CS polarity must be
>>>>>>>> defined
>>>>>>>>> Active High to avoid
>>>>>>>>> + * ambiguity. That's why we use
>>>>>>>> enable,
>>>>>>>>> that takes SPI_CS_HIGH
>>>>>>>>> + * into account.
>>>>>>>>> + */
>>>>>>>>> + if (has_acpi_companion(&spi->dev))
>>>>>>>>> +
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>>>>>> +
>>>>>>>>> !enable);
>>>>>>>>> + else
>>>>>>>>> + /* Polarity handled by GPIO
>>>>>>>>> library */
>>>>>>>>> +
>>>>>>>>> gpiod_set_value_cansleep(spi_get_csgpiod(spi, cs_num),
>>>>>>>>> +
>>>>>>>>> activate);
>>>>>>>>> + }
>>>>>>>>> + /* Some SPI masters need both GPIO CS &
>>>>>>>>> slave_select */
>>>>>>>>> + if ((spi->controller->flags &
>>>>>>>>> SPI_MASTER_GPIO_SS) &&
>>>>>>>>> + spi->controller->set_cs)
>>>>>>>>> + spi->controller->set_cs(spi, !enable);
>>>>>>>>> + } else if (spi->controller->set_cs) {
>>>>>>>>> spi->controller->set_cs(spi, !enable);
>>>>>>>>> - } else if (spi->controller->set_cs) {
>>>>>>>>> - spi->controller->set_cs(spi, !enable);
>>>>>>>>> - }
>>>>>>>>> + }
>>>>>>>>>
>>>>>>>>> - if (spi_get_csgpiod(spi, 0) ||
>>>>>>>> !spi->controller->set_cs_timing) {
>>>>>>>>> - if (activate)
>>>>>>>>> - spi_delay_exec(&spi->cs_setup, NULL);
>>>>>>>>> - else
>>>>>>>>> - spi_delay_exec(&spi->cs_inactive, NULL);
>>>>>>>>> + if (spi_get_csgpiod(spi, cs_num) || !spi->controller-
>>>>>>>>>> set_cs_timing) {
>>>>>>>>> + if (activate)
>>>>>>>>> + spi_delay_exec(&spi->cs_setup,
>>>> NULL);
>>>>>>>>> + else
>>>>>>>>> + spi_delay_exec(&spi->cs_inactive,
>>>>>>>>> NULL);
>>>>>>>>> + }
>>>>>>>>> }
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> @@ -2246,8 +2325,8 @@ static void
>> of_spi_parse_dt_cs_delay(struct
>>>>>>>>> device_node *nc, static int of_spi_parse_dt(struct spi_controller
>>>>>>>>> *ctlr, struct
>>>>>>>> spi_device
>>>>>>>>> *spi,
>>>>>>>>> struct device_node *nc)
>>>>>>>>> {
>>>>>>>>> - u32 value;
>>>>>>>>> - int rc;
>>>>>>>>> + u32 value, cs[SPI_CS_CNT_MAX] = {0};
>>>>>>>>> + int rc, idx;
>>>>>>>>>
>>>>>>>>> /* Mode (clock phase/polarity/etc.) */
>>>>>>>>> if (of_property_read_bool(nc, "spi-cpha")) @@ -2320,13
>>>>>>>>> +2399,21
>>>>>>>> @@
>>>>>>>>> static int of_spi_parse_dt(struct spi_controller *ctlr, struct
>>>>>>>>> spi_device *spi,
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> /* Device address */
>>>>>>>>> - rc = of_property_read_u32(nc, "reg", &value);
>>>>>>>>> - if (rc) {
>>>>>>>>> + rc = of_property_read_variable_u32_array(nc, "reg", &cs[0],
>>>> 1,
>>>>>>>>> + SPI_CS_CNT_MAX);
>>>>>>>>> + if (rc < 0 || rc > ctlr->num_chipselect) {
>>>>>>>>> dev_err(&ctlr->dev, "%pOF has no valid 'reg' property
>>>>>>>> (%d)\n",
>>>>>>>>> nc, rc);
>>>>>>>>> return rc;
>>>>>>>>> + } else if ((of_property_read_bool(nc, "parallel-memories"))
>>>> &&
>>>>>>>>> + (!(ctlr->flags & SPI_CONTROLLER_MULTI_CS))) {
>>>>>>>>> + dev_err(&ctlr->dev, "SPI controller doesn't support
>>>>>>>> multi
>>>>>>>>> CS\n");
>>>>>>>>> + return -EINVAL;
>>>>>>>>> }
>>>>>>>>> - spi_set_chipselect(spi, 0, value);
>>>>>>>>> + for (idx = 0; idx < rc; idx++)
>>>>>>>>> + spi_set_chipselect(spi, idx, cs[idx]);
>>>>>>>>> + /* By default set the spi->cs_index_mask as 1 */
>>>>>>>>> + spi->cs_index_mask = 0x01;
>>>>>>>>>
>>>>>>>>> /* Device speed */
>>>>>>>>> if (!of_property_read_u32(nc, "spi-max-frequency", &value))
>>>> @@
>>>>>>>>> -3907,7 +3994,8 @@ static int __spi_validate(struct spi_device
>>>>>>>>> *spi, struct spi_message *message)
>>>>>>>>> * cs_change is set for each transfer.
>>>>>>>>> */
>>>>>>>>> if ((spi->mode & SPI_CS_WORD) && (!(ctlr->mode_bits &
>>>>>>>>> SPI_CS_WORD) ||
>>>>>>>>> - spi_get_csgpiod(spi, 0))) {
>>>>>>>>> + spi_get_csgpiod(spi, 0) ||
>>>>>>>>> + spi_get_csgpiod(spi, 1))) {
>>>>>>>>> size_t maxsize;
>>>>>>>>> int ret;
>>>>>>>>>
>>>>>>>>> diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
>>>>>>>>> index 873ced6ae4ca..6453b246e0af 100644
>>>>>>>>> --- a/include/linux/spi/spi.h
>>>>>>>>> +++ b/include/linux/spi/spi.h
>>>>>>>>> @@ -19,6 +19,11 @@
>>>>>>>>> #include <linux/acpi.h>
>>>>>>>>> #include <linux/u64_stats_sync.h>
>>>>>>>>>
>>>>>>>>> +/* Max no. of CS supported per spi device */ #define
>>>>>>>>> +SPI_CS_CNT_MAX
>>>>>>>>> +2
>>>>>>>>> +
>>>>>>>>> +/* chip select mask */
>>>>>>>>> +#define SPI_PARALLEL_CS_MASK (BIT(0) | BIT(1))
>>>>>>>>> struct dma_chan;
>>>>>>>>> struct software_node;
>>>>>>>>> struct ptp_system_timestamp;
>>>>>>>>> @@ -166,6 +171,7 @@ extern void
>>>>>>>>> spi_transfer_cs_change_delay_exec(struct spi_message *msg,
>>>>>>>>> * deasserted. If @cs_change_delay is used from
>>>> @spi_transfer,
>>>>>>>>> then the
>>>>>>>>> * two delays will be added up.
>>>>>>>>> * @pcpu_statistics: statistics for the spi_device
>>>>>>>>> + * @cs_index_mask: Bit mask of the active chipselect(s) in the
>>>>>>>>> chipselect array
>>>>>>>>> *
>>>>>>>>> * A @spi_device is used to interchange data between an SPI slave
>>>>>>>>> * (usually a discrete chip) and CPU memory.
>>>>>>>>> @@ -181,7 +187,7 @@ struct spi_device {
>>>>>>>>> struct spi_controller *controller;
>>>>>>>>> struct spi_controller *master; /* Compatibility layer
>>>>>>>> */
>>>>>>>>> u32 max_speed_hz;
>>>>>>>>> - u8 chip_select;
>>>>>>>>> + u8 chip_select[SPI_CS_CNT_MAX];
>>>>>>>>> u8 bits_per_word;
>>>>>>>>> bool rt;
>>>>>>>>> #define SPI_NO_TX BIT(31) /* No transmit wire */
>>>>>>>>> @@ -202,7 +208,7 @@ struct spi_device {
>>>>>>>>> void *controller_data;
>>>>>>>>> char modalias[SPI_NAME_SIZE];
>>>>>>>>> const char *driver_override;
>>>>>>>>> - struct gpio_desc *cs_gpiod; /* Chip select gpio
>>>>>>>> desc
>>>>>>>>> */
>>>>>>>>> + struct gpio_desc *cs_gpiod[SPI_CS_CNT_MAX]; /*
>>>>>>>> Chip
>>>>>>>>> select gpio desc */
>>>>>>>>> struct spi_delay word_delay; /* Inter-word delay */
>>>>>>>>> /* CS delays */
>>>>>>>>> struct spi_delay cs_setup;
>>>>>>>>> @@ -212,6 +218,13 @@ struct spi_device {
>>>>>>>>> /* The statistics */
>>>>>>>>> struct spi_statistics __percpu *pcpu_statistics;
>>>>>>>>>
>>>>>>>>> + /* Bit mask of the chipselect(s) that the driver need to use
>>>>>>>> from
>>>>>>>>> + * the chipselect array.When the controller is capable to
>>>>>>>> handle
>>>>>>>>> + * multiple chip selects & memories are connected in parallel
>>>>>>>>> + * then more than one bit need to be set in cs_index_mask.
>>>>>>>>> + */
>>>>>>>>> + u32 cs_index_mask : SPI_CS_CNT_MAX;
>>>>>>>>> +
>>>>>>>>> /*
>>>>>>>>> * likely need more hooks for more protocol options affecting
>>>> how
>>>>>>>>> * the controller talks to each chip, like:
>>>>>>>>> @@ -268,22 +281,22 @@ static inline void *spi_get_drvdata(const
>>>>>>>>> struct spi_device *spi)
>>>>>>>>>
>>>>>>>>> static inline u8 spi_get_chipselect(const struct spi_device
>>>>>>>>> *spi,
>>>>>>>> u8 idx)
>>>>>>>>> {
>>>>>>>>> - return spi->chip_select;
>>>>>>>>> + return spi->chip_select[idx];
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> static inline void spi_set_chipselect(struct spi_device *spi,
>>>>>>>>> u8
>>>>>>>> idx, u8
>>>>>>>>> chipselect)
>>>>>>>>> {
>>>>>>>>> - spi->chip_select = chipselect;
>>>>>>>>> + spi->chip_select[idx] = chipselect;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> static inline struct gpio_desc *spi_get_csgpiod(const struct
>>>>>>>> spi_device
>>>>>>>>> *spi, u8 idx)
>>>>>>>>> {
>>>>>>>>> - return spi->cs_gpiod;
>>>>>>>>> + return spi->cs_gpiod[idx];
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> static inline void spi_set_csgpiod(struct spi_device *spi, u8
>>>>>>>>> idx,
>>>>>>>> struct
>>>>>>>>> gpio_desc *csgpiod)
>>>>>>>>> {
>>>>>>>>> - spi->cs_gpiod = csgpiod;
>>>>>>>>> + spi->cs_gpiod[idx] = csgpiod;
>>>>>>>>> }
>>>>>>>>>
>>>>>>>>> /**
>>>>>>>>> @@ -388,6 +401,8 @@ extern struct spi_device
>>>>>>>>> *spi_new_ancillary_device(struct spi_device *spi, u8 ch
>>>>>>>>> * @bus_lock_spinlock: spinlock for SPI bus locking
>>>>>>>>> * @bus_lock_mutex: mutex for exclusion of multiple callers
>>>>>>>>> * @bus_lock_flag: indicates that the SPI bus is locked for
>>>>>>>> exclusive use
>>>>>>>>> + * @multi_cs_cap: indicates that the SPI Controller can
>>>>>>>> assert/de-assert
>>>>>>>>> + * more than one chip select at once.
>>>>>>>>> * @setup: updates the device mode and clocking records used by
>> a
>>>>>>>>> * device's SPI controller; protocol code may call this. This
>>>>>>>>> * must fail if an unrecognized or unsupported mode is
>>>> requested.
>>>>>>>>> @@ -554,6 +569,11 @@ struct spi_controller {
>>>>>>>>> #define SPI_CONTROLLER_MUST_TX BIT(4) /*
>> Requires tx
>>>>>>>>> */
>>>>>>>>>
>>>>>>>>> #define SPI_MASTER_GPIO_SS BIT(5) /* GPIO CS
>> must
>>>>>>>> select
>>>>>>>>> slave */
>>>>>>>>> + /*
>>>>>>>>> + * The spi-controller has multi chip select capability and can
>>>>>>>>> + * assert/de-assert more than one chip select at once.
>>>>>>>>> + */
>>>>>>>>> +#define SPI_CONTROLLER_MULTI_CS BIT(6)
>>>>>>>>>
>>>>>>>>> /* Flag indicating if the allocation of this struct is devres-
>>>>>>>>> managed */
>>>>>>>>> bool devm_allocated;
>>>>>>>>> --
>>>>>>>>> 2.17.1