Intel EHL consist of 3 identical MAC. 2 are located in the Intel(R)
Programmable Services Engine (Intel(R) PSE) and 1 is located in the
platform Controller Hub (PCH). Each MAC consist of 3 PCI IDs which are
differentiated by MII and speed.
Voon Weifeng (3):
net: stmmac: add EHL PSE0 & PSE1 1Gbps PCI info and PCI ID
net: stmmac: add EHL PSE0 & PSE1 2.5Gbps PCI info and PCI ID
net: stmmac: add EHL SGMII 2.5Gbps PCI info and PCI ID
.../net/ethernet/stmicro/stmmac/stmmac_pci.c | 92 +++++++++++++++++--
1 file changed, 86 insertions(+), 6 deletions(-)
--
2.17.1
Add EHL PSE0/1 RGMII & SGMII 1Gbps PCI info and PCI ID
Signed-off-by: Voon Weifeng <[email protected]>
Signed-off-by: Ong Boon Leong <[email protected]>
---
.../net/ethernet/stmicro/stmmac/stmmac_pci.c | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
index 7acbac73c29c..47f589968e66 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_pci.c
@@ -240,6 +240,66 @@ static struct stmmac_pci_info ehl_rgmii1g_pci_info = {
.setup = ehl_rgmii_data,
};
+static int ehl_pse0_common_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->bus_id = 2;
+ plat->phy_addr = 1;
+ return ehl_common_data(pdev, plat);
+}
+
+static int ehl_pse0_rgmii1g_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
+ return ehl_pse0_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_pse0_rgmii1g_pci_info = {
+ .setup = ehl_pse0_rgmii1g_data,
+};
+
+static int ehl_pse0_sgmii1g_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ return ehl_pse0_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_pse0_sgmii1g_pci_info = {
+ .setup = ehl_pse0_sgmii1g_data,
+};
+
+static int ehl_pse1_common_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->bus_id = 3;
+ plat->phy_addr = 1;
+ return ehl_common_data(pdev, plat);
+}
+
+static int ehl_pse1_rgmii1g_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID;
+ return ehl_pse1_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_pse1_rgmii1g_pci_info = {
+ .setup = ehl_pse1_rgmii1g_data,
+};
+
+static int ehl_pse1_sgmii1g_data(struct pci_dev *pdev,
+ struct plat_stmmacenet_data *plat)
+{
+ plat->phy_interface = PHY_INTERFACE_MODE_SGMII;
+ return ehl_pse1_common_data(pdev, plat);
+}
+
+static struct stmmac_pci_info ehl_pse1_sgmii1g_pci_info = {
+ .setup = ehl_pse1_sgmii1g_data,
+};
+
static int tgl_common_data(struct pci_dev *pdev,
struct plat_stmmacenet_data *plat)
{
@@ -585,6 +645,10 @@ static SIMPLE_DEV_PM_OPS(stmmac_pm_ops, stmmac_pci_suspend, stmmac_pci_resume);
#define PCI_DEVICE_ID_INTEL_QUARK_ID 0x0937
#define PCI_DEVICE_ID_INTEL_EHL_RGMII1G_ID 0x4b30
#define PCI_DEVICE_ID_INTEL_EHL_SGMII1G_ID 0x4b31
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_RGMII1G_ID 0x4ba0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE0_SGMII1G_ID 0x4ba1
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_RGMII1G_ID 0x4bb0
+#define PCI_DEVICE_ID_INTEL_EHL_PSE1_SGMII1G_ID 0x4bb1
#define PCI_DEVICE_ID_INTEL_TGL_SGMII1G_ID 0xa0ac
#define PCI_DEVICE_ID_SYNOPSYS_GMAC5_ID 0x7102
@@ -594,6 +658,14 @@ static const struct pci_device_id stmmac_id_table[] = {
{ PCI_DEVICE_DATA(INTEL, QUARK_ID, &quark_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_RGMII1G_ID, &ehl_rgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, EHL_SGMII1G_ID, &ehl_sgmii1g_pci_info) },
+ { PCI_DEVICE_DATA(INTEL, EHL_PSE0_RGMII1G_ID,
+ &ehl_pse0_rgmii1g_pci_info) },
+ { PCI_DEVICE_DATA(INTEL, EHL_PSE0_SGMII1G_ID,
+ &ehl_pse0_sgmii1g_pci_info) },
+ { PCI_DEVICE_DATA(INTEL, EHL_PSE1_RGMII1G_ID,
+ &ehl_pse1_rgmii1g_pci_info) },
+ { PCI_DEVICE_DATA(INTEL, EHL_PSE1_SGMII1G_ID,
+ &ehl_pse1_sgmii1g_pci_info) },
{ PCI_DEVICE_DATA(INTEL, TGL_SGMII1G_ID, &tgl_sgmii1g_pci_info) },
{ PCI_DEVICE_DATA(SYNOPSYS, GMAC5_ID, &snps_gmac5_pci_info) },
{}
--
2.17.1
From: Voon Weifeng <[email protected]>
Date: Mar/20/2020, 16:48:22 (UTC+00:00)
> Intel EHL consist of 3 identical MAC. 2 are located in the Intel(R)
> Programmable Services Engine (Intel(R) PSE) and 1 is located in the
> platform Controller Hub (PCH). Each MAC consist of 3 PCI IDs which are
> differentiated by MII and speed.
This stmmac_pci.c is getting bigger and bigger ... Can you consider adding
your own PCI driver (dwmac-intel.c) to stmmac tree ?
You could even submit a patch for MAINTAINERS for this particular driver
as it's already done for others.
---
Thanks,
Jose Miguel Abreu
> > Intel EHL consist of 3 identical MAC. 2 are located in the Intel(R)
> > Programmable Services Engine (Intel(R) PSE) and 1 is located in the
> > platform Controller Hub (PCH). Each MAC consist of 3 PCI IDs which are
> > differentiated by MII and speed.
>
> This stmmac_pci.c is getting bigger and bigger ... Can you consider
> adding your own PCI driver (dwmac-intel.c) to stmmac tree ?
Good idea. I will rework on this and submit as v2. Thanks.
>
> You could even submit a patch for MAINTAINERS for this particular driver
> as it's already done for others.
Do you mean becoming the maintainer for this particular file?
Regards,
Weifeng
>
> ---
> Thanks,
> Jose Miguel Abreu