2022-02-14 19:23:04

by Zhang, Tianfei

Subject: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

From: Matthew Gerlach <[email protected]>

Not all FPGA designs managed by the DFL driver have a port.
In these cases, don't write the Port Access Control register
when enabling SRIOV.

Signed-off-by: Matthew Gerlach <[email protected]>
Signed-off-by: Tianfei Zhang <[email protected]>
---
drivers/fpga/dfl.c | 2 ++
1 file changed, 2 insertions(+)

diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
index cfc539a656f0..a5263ac258c5 100644
--- a/drivers/fpga/dfl.c
+++ b/drivers/fpga/dfl.c
@@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
int ret = 0, port_count = 0;

mutex_lock(&cdev->lock);
+ if (list_empty(&cdev->port_dev_list))
+ goto done;

list_for_each_entry(pdata, &cdev->port_dev_list, node) {
if (pdata->dev)
--
2.17.1

2022-02-15 16:03:02

by Tom Rix

Subject: Re: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

On 2/14/22 3:26 AM, Tianfei zhang wrote:
> From: Matthew Gerlach <[email protected]>
>
> Not all FPGA designs managed by the DFL driver have a port.
> In these cases, don't write the Port Access Control register
> when enabling SRIOV.

Drop the 'drivers:' in the subject line.

This patch likely needs to moved to 4/7 since the last patch also
iterated over the list.

Tom

>
> Signed-off-by: Matthew Gerlach <[email protected]>
> Signed-off-by: Tianfei Zhang <[email protected]>
> ---
> drivers/fpga/dfl.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c
> index cfc539a656f0..a5263ac258c5 100644
> --- a/drivers/fpga/dfl.c
> +++ b/drivers/fpga/dfl.c
> @@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct dfl_fpga_cdev *cdev, int num_vfs)
> int ret = 0, port_count = 0;
>
> mutex_lock(&cdev->lock);
> + if (list_empty(&cdev->port_dev_list))
> + goto done;
>
> list_for_each_entry(pdata, &cdev->port_dev_list, node) {
> if (pdata->dev)

2022-02-18 08:36:53

by Zhang, Tianfei

Subject: RE: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list

> -----Original Message-----
> From: Tom Rix <[email protected]>
> Sent: Tuesday, February 15, 2022 11:56 PM
> To: Zhang, Tianfei <[email protected]>; Wu, Hao <[email protected]>;
> [email protected]; Xu, Yilun <[email protected]>; [email protected];
> [email protected]; [email protected]
> Cc: [email protected]; Matthew Gerlach <[email protected]>
> Subject: Re: [PATCH v1 5/7] drivers: fpga: dfl: handle empty port list
>
>
> On 2/14/22 3:26 AM, Tianfei zhang wrote:
> > From: Matthew Gerlach <[email protected]>
> >
> > Not all FPGA designs managed by the DFL driver have a port.
> > In these cases, don't write the Port Access Control register when
> > enabling SRIOV.
>
> Drop the 'drivers:' in the subject line.

Yes, I agree.

>
> This patch likely needs to moved to 4/7 since the last patch also iterated over
> the list.

Yes, I agree, I will move it on next version patch.

>
> Tom
>
> >
> > Signed-off-by: Matthew Gerlach <[email protected]>
> > Signed-off-by: Tianfei Zhang <[email protected]>
> > ---
> > drivers/fpga/dfl.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index
> > cfc539a656f0..a5263ac258c5 100644
> > --- a/drivers/fpga/dfl.c
> > +++ b/drivers/fpga/dfl.c
> > @@ -1708,6 +1708,8 @@ int dfl_fpga_cdev_config_ports_vf(struct
> dfl_fpga_cdev *cdev, int num_vfs)
> > int ret = 0, port_count = 0;
> >
> > mutex_lock(&cdev->lock);
> > + if (list_empty(&cdev->port_dev_list))
> > + goto done;
> >
> > list_for_each_entry(pdata, &cdev->port_dev_list, node) {
> > if (pdata->dev)