Base firmware node and clock child node binding are part of mainline kernel.
This patchset adds documentation to describe rest of the firmware child node bindings.
Complete firmware DT node example is shown below for ease of understanding:
firmware {
zynqmp_firmware: zynqmp-firmware {
compatible = "xlnx,zynqmp-firmware";
method = "smc";
#power-domain-cells = <1>;
#reset-cells = <1>;
zynqmp_clk: clock-controller {
#clock-cells = <1>;
compatible = "xlnx,zynqmp-clk";
clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <>_crx_ref_clk>;
clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
};
zynqmp_power: zynqmp-power {
compatible = "xlnx,zynqmp-power";
interrupts = <0 35 4>;
};
zynqmp_reset: reset-controller {
compatible = "xlnx,zynqmp-reset";
#reset-cells = <1>;
};
nvmem_firmware {
compatible = "xlnx,zynqmp-nvmem-fw";
#address-cells = <1>;
#size-cells = <1>;
/* Data cells */
soc_revision: soc_revision {
reg = <0x0 0x4>;
};
};
pinctrl0: pinctrl@ff180000 {
compatible = "xlnx,zynqmp-pinctrl";
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
};
};
};
};
};
Nava kishore Manne (3):
dt-bindings: reset: Add bindings for ZynqMP reset driver
dt-bindings: nvmem: Add bindings for ZynqMP nvmem driver
dt-bindings: fpga: Add bindings for ZynqMP fpga driver
Rajan Vaja (3):
dt-bindings: power: Add ZynqMP power domain bindings
dt-bindings: soc: Add ZynqMP PM bindings
dt-bindings: pinctrl: Add ZynqMP pin controller bindings
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++
.../bindings/pinctrl/xlnx,zynqmp-pinctrl.txt | 275 ++++++++++++++++++
.../power/reset/xlnx,zynqmp-power.txt | 25 ++
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 +++
.../bindings/reset/xlnx,zynqmp-reset.txt | 52 ++++
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++
.../dt-bindings/reset/xlnx-zynqmp-resets.h | 130 +++++++++
8 files changed, 615 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
create mode 100644 Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.txt
create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 Documentation/devicetree/bindings/reset/xlnx,zynqmp-reset.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
create mode 100644 include/dt-bindings/reset/xlnx-zynqmp-resets.h
--
2.18.0
Add documentation to describe Xilinx ZynqMP nvmem driver
bindings.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v3:
-Added nvmem node as child of FW. Since nvmem driver is a provider.
.../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
diff --git a/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
new file mode 100644
index 000000000000..2043c8284f8c
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
@@ -0,0 +1,47 @@
+--------------------------------------------------------------------------
+= Zynq UltraScale+ MPSoC nvmem firmware driver binding =
+--------------------------------------------------------------------------
+The nvmem_firmware node provides access to the hardware related data
+like soc revision, IDCODE... etc, By using the firmware interface.
+
+Required properties:
+- compatible: should be "xlnx,zynqmp-nvmem-fw"
+
+= Data cells =
+Are child nodes of silicon id, bindings of which as described in
+bindings/nvmem/nvmem.txt
+
+-------
+ Example
+-------
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ nvmem_firmware {
+ compatible = "xlnx,zynqmp-nvmem-fw";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ /* Data cells */
+ soc_revision: soc_revision {
+ reg = <0x0 0x4>;
+ };
+ };
+ };
+};
+
+= Data consumers =
+Are device nodes which consume nvmem data cells.
+
+For example:
+ pcap {
+ ...
+
+ nvmem-cells = <&soc_revision>;
+ nvmem-cell-names = "soc_revision";
+
+ ...
+ };
+
--
2.18.0
From: Rajan Vaja <[email protected]>
Add documentation to describe Xilinx ZynqMP power management
bindings.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes for v3:
-None.
.../power/reset/xlnx,zynqmp-power.txt | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
diff --git a/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
new file mode 100644
index 000000000000..d366f1eb623a
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.txt
@@ -0,0 +1,25 @@
+--------------------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC Power Management
+--------------------------------------------------------------------
+The zynqmp-power node describes the power management configurations.
+It will control remote suspend/shutdown interfaces.
+
+Required properties:
+ - compatible: Must contain: "xlnx,zynqmp-power"
+ - interrupts: Interrupt specifier
+
+-------
+Example
+-------
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ compatible = "xlnx,zynqmp-firmware";
+ method = "smc";
+
+ zynqmp_power: zynqmp-power {
+ compatible = "xlnx,zynqmp-power";
+ interrupts = <0 35 4>;
+ };
+ };
+};
--
2.18.0
Add documentation to describe Xilinx ZynqMP fpga driver
bindings.
Signed-off-by: Nava kishore Manne <[email protected]>
---
Changes for v3:
-Removed PCAP as a child node to the FW and Created
an independent node since PCAP driver is a consumer
not a provider.
.../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
1 file changed, 13 insertions(+)
create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
new file mode 100644
index 000000000000..1f6f58872311
--- /dev/null
+++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
@@ -0,0 +1,13 @@
+Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
+using ZynqMP SoC firmware interface
+For Bitstream configuration on ZynqMp Soc uses processor configuration
+port(PCAP) to configure the programmable logic(PL) through PS by using
+FW interface.
+
+Required properties:
+- compatible: should contain "xlnx,zynqmp-pcap-fpga"
+
+Example:
+ zynqmp_pcap: pcap {
+ compatible = "xlnx,zynqmp-pcap-fpga";
+ };
--
2.18.0
From: Rajan Vaja <[email protected]>
Add documentation to describe ZynqMP power domain bindings.
Signed-off-by: Rajan Vaja <[email protected]>
Signed-off-by: Jolly Shah <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Changes for v3:
-None.
.../bindings/power/xlnx,zynqmp-genpd.txt | 34 ++++++++++++++++
include/dt-bindings/power/xlnx-zynqmp-power.h | 39 +++++++++++++++++++
2 files changed, 73 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
create mode 100644 include/dt-bindings/power/xlnx-zynqmp-power.h
diff --git a/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
new file mode 100644
index 000000000000..3c7f2378e146
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/xlnx,zynqmp-genpd.txt
@@ -0,0 +1,34 @@
+-----------------------------------------------------------
+Device Tree Bindings for the Xilinx Zynq MPSoC PM domains
+-----------------------------------------------------------
+The binding for zynqmp-power-controller follow the common
+generic PM domain binding[1].
+
+[1] Documentation/devicetree/bindings/power/power_domain.txt
+
+== Zynq MPSoC Generic PM Domain Node ==
+
+Required property:
+ - Below property should be in zynqmp-firmware node.
+ - #power-domain-cells: Number of cells in a PM domain specifier. Must be 1.
+
+Power domain ID indexes are mentioned in
+include/dt-bindings/power/xlnx-zynqmp-power.h.
+
+-------
+Example
+-------
+
+firmware {
+ zynqmp_firmware: zynqmp-firmware {
+ ...
+ #power-domain-cells = <1>;
+ ...
+ };
+};
+
+sata {
+ ...
+ power-domains = <&zynqmp_firmware 2>;
+ ...
+};
diff --git a/include/dt-bindings/power/xlnx-zynqmp-power.h b/include/dt-bindings/power/xlnx-zynqmp-power.h
new file mode 100644
index 000000000000..1bc9636098ca
--- /dev/null
+++ b/include/dt-bindings/power/xlnx-zynqmp-power.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 Xilinx, Inc.
+ */
+
+#ifndef _DT_BINDINGS_ZYNQMP_POWER_H
+#define _DT_BINDINGS_ZYNQMP_POWER_H
+
+#define PD_USB_0 0
+#define PD_USB_1 1
+#define PD_SATA 2
+#define PD_SPI_0 3
+#define PD_SPI_1 4
+#define PD_UART_0 5
+#define PD_UART_1 6
+#define PD_ETH_0 7
+#define PD_ETH_1 8
+#define PD_ETH_2 9
+#define PD_ETH_3 10
+#define PD_I2C_0 11
+#define PD_I2C_1 12
+#define PD_DP 13
+#define PD_GDMA 14
+#define PD_ADMA 15
+#define PD_TTC_0 16
+#define PD_TTC_1 17
+#define PD_TTC_2 18
+#define PD_TTC_3 19
+#define PD_SD_0 20
+#define PD_SD_1 21
+#define PD_NAND 22
+#define PD_QSPI 23
+#define PD_GPIO 24
+#define PD_CAN_0 25
+#define PD_CAN_1 26
+#define PD_PCIE 27
+#define PD_GPU 28
+
+#endif
--
2.18.0
On Mon, 21 Jan 2019 23:08:34 +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP nvmem driver
> bindings.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> Changes for v3:
> -Added nvmem node as child of FW. Since nvmem driver is a provider.
>
> .../bindings/nvmem/xlnx,zynqmp-nvmem.txt | 47 +++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/xlnx,zynqmp-nvmem.txt
>
Reviewed-by: Rob Herring <[email protected]>
On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> Add documentation to describe Xilinx ZynqMP fpga driver
> bindings.
>
> Signed-off-by: Nava kishore Manne <[email protected]>
> ---
> Changes for v3:
> -Removed PCAP as a child node to the FW and Created
> an independent node since PCAP driver is a consumer
> not a provider.
>
> .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> diff --git a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> new file mode 100644
> index 000000000000..1f6f58872311
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> @@ -0,0 +1,13 @@
> +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC controlled
> +using ZynqMP SoC firmware interface
> +For Bitstream configuration on ZynqMp Soc uses processor configuration
> +port(PCAP) to configure the programmable logic(PL) through PS by using
> +FW interface.
> +
> +Required properties:
> +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> +
> +Example:
> + zynqmp_pcap: pcap {
> + compatible = "xlnx,zynqmp-pcap-fpga";
> + };
There's no need for a DT node. Just make the firware driver create a
platform device for pcap.
Rob
On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <[email protected]> wrote:
>
> Hi Rob,
>
>
>
> Thanks for providing the comments...
Please fix your mailer to send plain text emails to mail lists.
> > -----Original Message-----
>
> > From: Rob Herring [mailto:[email protected]]
>
> > Sent: Monday, January 21, 2019 9:19 PM
>
> > To: Nava kishore Manne <[email protected]>
>
> > Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
>
> > <[email protected]>; [email protected]; linux-
>
> > [email protected]; [email protected]; Jolly Shah
>
> > <[email protected]>; [email protected]
>
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
>
> > driver
>
> >
>
> > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
>
> > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
>
> > >
>
> > > Signed-off-by: Nava kishore Manne <[email protected]>
>
> > > ---
>
> > > Changes for v3:
>
> > > -Removed PCAP as a child node to the FW and Created
>
> > > an independent node since PCAP driver is a consumer
>
> > > not a provider.
>
> > >
>
> > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
>
> > > 1 file changed, 13 insertions(+)
>
> > > create mode 100644
>
> > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > >
>
> > > diff --git
>
> > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > new file mode 100644
>
> > > index 000000000000..1f6f58872311
>
> > > --- /dev/null
>
> > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
>
> > > @@ -0,0 +1,13 @@
>
> > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
>
> > > +controlled using ZynqMP SoC firmware interface For Bitstream
>
> > > +configuration on ZynqMp Soc uses processor configuration
>
> > > +port(PCAP) to configure the programmable logic(PL) through PS by
>
> > > +using FW interface.
>
> > > +
>
> > > +Required properties:
>
> > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
>
> > > +
>
> > > +Example:
>
> > > + zynqmp_pcap: pcap {
>
> > > + compatible = "xlnx,zynqmp-pcap-fpga";
>
> > > + };
>
> >
>
> > There's no need for a DT node. Just make the firware driver create a platform
>
> > device for pcap.
>
> >
>
>
>
> This driver being used by the FPGA manager framework(fpga-region) to apply overlay's so this node is needed AFAIK.
The binding says nothing about child nodes and what they are. Please
define that.
Rob
Hi Rob,
Thanks for providing the review comments..
Please find my response inline.
> -----Original Message-----
> From: Rob Herring [mailto:[email protected]]
> Sent: Saturday, February 23, 2019 2:01 AM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected]; linux-
> [email protected]; [email protected]; Jolly Shah
> <[email protected]>; [email protected]
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
>
> On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <[email protected]>
> wrote:
> >
> > Hi Rob,
> >
> >
> >
> > Thanks for providing the comments...
>
> Please fix your mailer to send plain text emails to mail lists.
>
Thanks for pointing it..
>
> > > -----Original Message-----
> >
> > > From: Rob Herring [mailto:[email protected]]
> >
> > > Sent: Monday, January 21, 2019 9:19 PM
> >
> > > To: Nava kishore Manne <[email protected]>
> >
> > > Cc: [email protected]; Michal Simek <[email protected]>; Rajan
> > > Vaja
> >
> > > <[email protected]>; [email protected]; linux-
> >
> > > [email protected]; [email protected]; Jolly Shah
> >
> > > <[email protected]>; [email protected]
> >
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga
> >
> > > driver
> >
> > >
> >
> > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> >
> > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> >
> > > >
> >
> > > > Signed-off-by: Nava kishore Manne <[email protected]>
> >
> > > > ---
> >
> > > > Changes for v3:
> >
> > > > -Removed PCAP as a child node to the FW
> > > > and Created
> >
> > > > an independent node since PCAP driver is a
> > > > consumer
> >
> > > > not a provider.
> >
> > > >
> >
> > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
> >
> > > > 1 file changed, 13 insertions(+)
> >
> > > > create mode 100644
> >
> > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > >
> >
> > > > diff --git
> >
> > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> >
> > > > new file mode 100644
> >
> > > > index 000000000000..1f6f58872311
> >
> > > > --- /dev/null
> >
> > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > +++ .txt
> >
> > > > @@ -0,0 +1,13 @@
> >
> > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> >
> > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> >
> > > > +configuration on ZynqMp Soc uses processor configuration
> >
> > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> >
> > > > +using FW interface.
> >
> > > > +
> >
> > > > +Required properties:
> >
> > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> >
> > > > +
> >
> > > > +Example:
> >
> > > > + zynqmp_pcap: pcap {
> >
> > > > + compatible = "xlnx,zynqmp-pcap-fpga";
> >
> > > > + };
> >
> > >
> >
> > > There's no need for a DT node. Just make the firware driver create a
> > > platform
> >
> > > device for pcap.
> >
> > >
> >
> >
> >
> > This driver being used by the FPGA manager framework(fpga-region) to apply
> overlay's so this node is needed AFAIK.
>
> The binding says nothing about child nodes and what they are. Please define
> that.
>
Do you mean I need to add the example usage of the pcap node like as below in the binding doc?
Device Tree Example for Full Reconfiguration
============================================
Live Device Tree contains:
zynqmp_pcap: pcap {
compatible = "xlnx,zynqmp-pcap-fpga";
};
fpga_region0: fpga-region0 {
compatible = "fpga-region";
fpga-mgr = <&zynqmp_pcap>;
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
};
DT Overlay contains:
/dts-v1/ /plugin/;
/ {
fragment@0 {
target = <&fpga_region0>;
#address-cells = <1>;
#size-cells = <1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <1>;
firmware-name = "zynqmp-gpio.bin";
gpio1: gpio@40000000 {
compatible = "xlnx,xps-gpio-1.00.a";
reg = <0x40000000 0x10000>;
gpio-controller;
#gpio-cells = <0x2>;
xlnx,gpio-width= <0x6>;
};
};
};
Please correct me if my understanding is wrong.
Regards,
Navakishore.
On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <[email protected]> wrote:
>
> Hi Rob,
>
> Thanks for providing the review comments..
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:[email protected]]
> > Sent: Saturday, February 23, 2019 2:01 AM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
> > <[email protected]>; [email protected]; linux-
> > [email protected]; [email protected]; Jolly Shah
> > <[email protected]>; [email protected]
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver
> >
> > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne <[email protected]>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > >
> > >
> > > Thanks for providing the comments...
> >
> > Please fix your mailer to send plain text emails to mail lists.
> >
> Thanks for pointing it..
>
> >
> > > > -----Original Message-----
> > >
> > > > From: Rob Herring [mailto:[email protected]]
> > >
> > > > Sent: Monday, January 21, 2019 9:19 PM
> > >
> > > > To: Nava kishore Manne <[email protected]>
> > >
> > > > Cc: [email protected]; Michal Simek <[email protected]>; Rajan
> > > > Vaja
> > >
> > > > <[email protected]>; [email protected]; linux-
> > >
> > > > [email protected]; [email protected]; Jolly Shah
> > >
> > > > <[email protected]>; [email protected]
> > >
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga
> > >
> > > > driver
> > >
> > > >
> > >
> > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > >
> > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > >
> > > > >
> > >
> > > > > Signed-off-by: Nava kishore Manne <[email protected]>
> > >
> > > > > ---
> > >
> > > > > Changes for v3:
> > >
> > > > > -Removed PCAP as a child node to the FW
> > > > > and Created
> > >
> > > > > an independent node since PCAP driver is a
> > > > > consumer
> > >
> > > > > not a provider.
> > >
> > > > >
> > >
> > > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
> > >
> > > > > 1 file changed, 13 insertions(+)
> > >
> > > > > create mode 100644
> > >
> > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > >
> > >
> > > > > diff --git
> > >
> > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.txt
> > >
> > > > > new file mode 100644
> > >
> > > > > index 000000000000..1f6f58872311
> > >
> > > > > --- /dev/null
> > >
> > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > +++ .txt
> > >
> > > > > @@ -0,0 +1,13 @@
> > >
> > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+ MPSoC
> > >
> > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > >
> > > > > +configuration on ZynqMp Soc uses processor configuration
> > >
> > > > > +port(PCAP) to configure the programmable logic(PL) through PS by
> > >
> > > > > +using FW interface.
> > >
> > > > > +
> > >
> > > > > +Required properties:
> > >
> > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > >
> > > > > +
> > >
> > > > > +Example:
> > >
> > > > > + zynqmp_pcap: pcap {
> > >
> > > > > + compatible = "xlnx,zynqmp-pcap-fpga";
> > >
> > > > > + };
> > >
> > > >
> > >
> > > > There's no need for a DT node. Just make the firware driver create a
> > > > platform
> > >
> > > > device for pcap.
> > >
> > > >
> > >
> > >
> > >
> > > This driver being used by the FPGA manager framework(fpga-region) to apply
> > overlay's so this node is needed AFAIK.
> >
> > The binding says nothing about child nodes and what they are. Please define
> > that.
> >
> Do you mean I need to add the example usage of the pcap node like as below in the binding doc?
You can have an example, but no, I meant you need say something like
"The pcap node may have 1 or more child nodes which have an
'fpga-region' compatible.
>
> Device Tree Example for Full Reconfiguration
> ============================================
>
> Live Device Tree contains:
>
> zynqmp_pcap: pcap {
> compatible = "xlnx,zynqmp-pcap-fpga";
> };
>
> fpga_region0: fpga-region0 {
This should be a child of pcap.
> compatible = "fpga-region";
> fpga-mgr = <&zynqmp_pcap>;
> #address-cells = <0x1>;
> #size-cells = <0x1>;
> ranges;
> };
>
> DT Overlay contains:
Don't show overlays in examples. Just show a final tree (i.e. base
with overlay applied).
> /dts-v1/ /plugin/;
> / {
> fragment@0 {
> target = <&fpga_region0>;
> #address-cells = <1>;
> #size-cells = <1>;
> __overlay__ {
> #address-cells = <1>;
> #size-cells = <1>;
>
> firmware-name = "zynqmp-gpio.bin";
>
> gpio1: gpio@40000000 {
> compatible = "xlnx,xps-gpio-1.00.a";
> reg = <0x40000000 0x10000>;
> gpio-controller;
> #gpio-cells = <0x2>;
> xlnx,gpio-width= <0x6>;
> };
> };
> };
>
> Please correct me if my understanding is wrong.
>
> Regards,
> Navakishore.
Hi Rob,
Thanks for the quick response.
Please find my response inline.
> -----Original Message-----
> From: Rob Herring [mailto:[email protected]]
> Sent: Monday, March 4, 2019 10:57 PM
> To: Nava kishore Manne <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected]; linux-
> [email protected]; [email protected]; Jolly Shah
> <[email protected]>; [email protected]
> Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
>
> On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <[email protected]>
> wrote:
> >
> > Hi Rob,
> >
> > Thanks for providing the review comments..
> > Please find my response inline.
> >
> > > -----Original Message-----
> > > From: Rob Herring [mailto:[email protected]]
> > > Sent: Saturday, February 23, 2019 2:01 AM
> > > To: Nava kishore Manne <[email protected]>
> > > Cc: [email protected]; Michal Simek <[email protected]>; Rajan
> > > Vaja <[email protected]>; [email protected];
> > > linux- [email protected]; [email protected]; Jolly
> > > Shah <[email protected]>; [email protected]
> > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > ZynqMP fpga driver
> > >
> > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > <[email protected]>
> > > wrote:
> > > >
> > > > Hi Rob,
> > > >
> > > >
> > > >
> > > > Thanks for providing the comments...
> > >
> > > Please fix your mailer to send plain text emails to mail lists.
> > >
> > Thanks for pointing it..
> >
> > >
> > > > > -----Original Message-----
> > > >
> > > > > From: Rob Herring [mailto:[email protected]]
> > > >
> > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > >
> > > > > To: Nava kishore Manne <[email protected]>
> > > >
> > > > > Cc: [email protected]; Michal Simek <[email protected]>;
> > > > > Rajan Vaja
> > > >
> > > > > <[email protected]>; [email protected];
> > > > > linux-
> > > >
> > > > > [email protected]; [email protected]; Jolly Shah
> > > >
> > > > > <[email protected]>; [email protected]
> > > >
> > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > > ZynqMP fpga
> > > >
> > > > > driver
> > > >
> > > > >
> > > >
> > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne wrote:
> > > >
> > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > >
> > > > > >
> > > >
> > > > > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > >
> > > > > > ---
> > > >
> > > > > > Changes for v3:
> > > >
> > > > > > -Removed PCAP as a child node to the
> > > > > > FW and Created
> > > >
> > > > > > an independent node since PCAP driver
> > > > > > is a consumer
> > > >
> > > > > > not a provider.
> > > >
> > > > > >
> > > >
> > > > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13 +++++++++++++
> > > >
> > > > > > 1 file changed, 13 insertions(+)
> > > >
> > > > > > create mode 100644
> > > >
> > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga.t
> > > > > > xt
> > > >
> > > > > >
> > > >
> > > > > > diff --git
> > > >
> > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > .txt
> > > >
> > > > > > new file mode 100644
> > > >
> > > > > > index 000000000000..1f6f58872311
> > > >
> > > > > > --- /dev/null
> > > >
> > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-
> > > > > > +++ fpga
> > > > > > +++ .txt
> > > >
> > > > > > @@ -0,0 +1,13 @@
> > > >
> > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > +MPSoC
> > > >
> > > > > > +controlled using ZynqMP SoC firmware interface For Bitstream
> > > >
> > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > >
> > > > > > +port(PCAP) to configure the programmable logic(PL) through PS
> > > > > > +by
> > > >
> > > > > > +using FW interface.
> > > >
> > > > > > +
> > > >
> > > > > > +Required properties:
> > > >
> > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > >
> > > > > > +
> > > >
> > > > > > +Example:
> > > >
> > > > > > + zynqmp_pcap: pcap {
> > > >
> > > > > > + compatible = "xlnx,zynqmp-pcap-fpga";
> > > >
> > > > > > + };
> > > >
> > > > >
> > > >
> > > > > There's no need for a DT node. Just make the firware driver
> > > > > create a platform
> > > >
> > > > > device for pcap.
> > > >
> > > > >
> > > >
> > > >
> > > >
> > > > This driver being used by the FPGA manager framework(fpga-region)
> > > > to apply
> > > overlay's so this node is needed AFAIK.
> > >
> > > The binding says nothing about child nodes and what they are. Please
> > > define that.
> > >
> > Do you mean I need to add the example usage of the pcap node like as below
> in the binding doc?
>
> You can have an example, but no, I meant you need say something like "The
> pcap node may have 1 or more child nodes which have an 'fpga-region'
> compatible.
> >
> > Device Tree Example for Full Reconfiguration
> > ============================================
> >
> > Live Device Tree contains:
> >
> > zynqmp_pcap: pcap {
> > compatible = "xlnx,zynqmp-pcap-fpga";
> > };
> >
> > fpga_region0: fpga-region0 {
>
> This should be a child of pcap.
>
AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
I have made this changes by looking into the below reference doc.
https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt
> > compatible = "fpga-region";
> > fpga-mgr = <&zynqmp_pcap>;
> > #address-cells = <0x1>;
> > #size-cells = <0x1>;
> > ranges;
> > };
> >
> > DT Overlay contains:
>
> Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> applied).
To get a better picture for the users i have added this example node with overlays
I feel it's good to have this info because it will not impact the functionality of PCAP node.
Please let me know if you still want me to make this example without overlay node.
Regards,
Navakishore.
Ping !!
> -----Original Message-----
> From: Nava kishore Manne
> Sent: Tuesday, March 5, 2019 3:12 PM
> To: 'Rob Herring' <[email protected]>
> Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
> <[email protected]>; [email protected]; linux-
> [email protected]; [email protected]; Jolly Shah
> <[email protected]>; [email protected]; 'Alan Tull'
> <[email protected]>; Moritz Fischer <[email protected]>
> Subject: RE: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> driver
>
> Hi Rob,
>
> Thanks for the quick response.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:[email protected]]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; Michal Simek <[email protected]>; Rajan
> > Vaja <[email protected]>; [email protected]; linux-
> > [email protected]; [email protected]; Jolly Shah
> > <[email protected]>; [email protected]
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP
> > fpga driver
> >
> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <[email protected]>
> > wrote:
> > >
> > > Hi Rob,
> > >
> > > Thanks for providing the review comments..
> > > Please find my response inline.
> > >
> > > > -----Original Message-----
> > > > From: Rob Herring [mailto:[email protected]]
> > > > Sent: Saturday, February 23, 2019 2:01 AM
> > > > To: Nava kishore Manne <[email protected]>
> > > > Cc: [email protected]; Michal Simek <[email protected]>; Rajan
> > > > Vaja <[email protected]>; [email protected];
> > > > linux- [email protected]; [email protected]; Jolly
> > > > Shah <[email protected]>; [email protected]
> > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for
> > > > ZynqMP fpga driver
> > > >
> > > > On Wed, Jan 23, 2019 at 2:46 PM Nava kishore Manne
> > > > <[email protected]>
> > > > wrote:
> > > > >
> > > > > Hi Rob,
> > > > >
> > > > >
> > > > >
> > > > > Thanks for providing the comments...
> > > >
> > > > Please fix your mailer to send plain text emails to mail lists.
> > > >
> > > Thanks for pointing it..
> > >
> > > >
> > > > > > -----Original Message-----
> > > > >
> > > > > > From: Rob Herring [mailto:[email protected]]
> > > > >
> > > > > > Sent: Monday, January 21, 2019 9:19 PM
> > > > >
> > > > > > To: Nava kishore Manne <[email protected]>
> > > > >
> > > > > > Cc: [email protected]; Michal Simek <[email protected]>;
> > > > > > Rajan Vaja
> > > > >
> > > > > > <[email protected]>; [email protected];
> > > > > > linux-
> > > > >
> > > > > > [email protected]; [email protected]; Jolly Shah
> > > > >
> > > > > > <[email protected]>; [email protected]
> > > > >
> > > > > > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings
> > > > > > for ZynqMP fpga
> > > > >
> > > > > > driver
> > > > >
> > > > > >
> > > > >
> > > > > > On Mon, Jan 21, 2019 at 11:08:35PM +0530, Nava kishore Manne
> wrote:
> > > > >
> > > > > > > Add documentation to describe Xilinx ZynqMP fpga driver bindings.
> > > > >
> > > > > > >
> > > > >
> > > > > > > Signed-off-by: Nava kishore Manne <[email protected]>
> > > > >
> > > > > > > ---
> > > > >
> > > > > > > Changes for v3:
> > > > >
> > > > > > > -Removed PCAP as a child node to the
> > > > > > > FW and Created
> > > > >
> > > > > > > an independent node since PCAP
> > > > > > > driver is a consumer
> > > > >
> > > > > > > not a provider.
> > > > >
> > > > > > >
> > > > >
> > > > > > > .../bindings/fpga/xlnx,zynqmp-pcap-fpga.txt | 13
> +++++++++++++
> > > > >
> > > > > > > 1 file changed, 13 insertions(+)
> > > > >
> > > > > > > create mode 100644
> > > > >
> > > > > > > Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fpga
> > > > > > > .t
> > > > > > > xt
> > > > >
> > > > > > >
> > > > >
> > > > > > > diff --git
> > > > >
> > > > > > > a/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pcap-fp
> > > > > > > ga
> > > > > > > .txt
> > > > >
> > > > > > > new file mode 100644
> > > > >
> > > > > > > index 000000000000..1f6f58872311
> > > > >
> > > > > > > --- /dev/null
> > > > >
> > > > > > > +++ b/Documentation/devicetree/bindings/fpga/xlnx,zynqmp-pca
> > > > > > > +++ p-
> > > > > > > +++ fpga
> > > > > > > +++ .txt
> > > > >
> > > > > > > @@ -0,0 +1,13 @@
> > > > >
> > > > > > > +Device Tree zynqmp-fpga bindings for the Zynq Ultrascale+
> > > > > > > +MPSoC
> > > > >
> > > > > > > +controlled using ZynqMP SoC firmware interface For
> > > > > > > +Bitstream
> > > > >
> > > > > > > +configuration on ZynqMp Soc uses processor configuration
> > > > >
> > > > > > > +port(PCAP) to configure the programmable logic(PL) through
> > > > > > > +PS by
> > > > >
> > > > > > > +using FW interface.
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Required properties:
> > > > >
> > > > > > > +- compatible: should contain "xlnx,zynqmp-pcap-fpga"
> > > > >
> > > > > > > +
> > > > >
> > > > > > > +Example:
> > > > >
> > > > > > > + zynqmp_pcap: pcap {
> > > > >
> > > > > > > + compatible = "xlnx,zynqmp-pcap-fpga";
> > > > >
> > > > > > > + };
> > > > >
> > > > > >
> > > > >
> > > > > > There's no need for a DT node. Just make the firware driver
> > > > > > create a platform
> > > > >
> > > > > > device for pcap.
> > > > >
> > > > > >
> > > > >
> > > > >
> > > > >
> > > > > This driver being used by the FPGA manager
> > > > > framework(fpga-region) to apply
> > > > overlay's so this node is needed AFAIK.
> > > >
> > > > The binding says nothing about child nodes and what they are.
> > > > Please define that.
> > > >
> > > Do you mean I need to add the example usage of the pcap node like as
> > > below
> > in the binding doc?
> >
> > You can have an example, but no, I meant you need say something like
> > "The pcap node may have 1 or more child nodes which have an 'fpga-region'
> > compatible.
> > >
> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > > zynqmp_pcap: pcap {
> > > compatible = "xlnx,zynqmp-pcap-fpga";
> > > };
> > >
> > > fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent
> and they refered to each other using phandlers I have made this changes by
> looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bind
> ings/fpga/fpga-region.txt
>
> > > compatible = "fpga-region";
> > > fpga-mgr = <&zynqmp_pcap>;
> > > #address-cells = <0x1>;
> > > #size-cells = <0x1>;
> > > ranges;
> > > };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base
> > with overlay applied).
>
> To get a better picture for the users i have added this example node with
> overlays I feel it's good to have this info because it will not impact the
> functionality of PCAP node.
> Please let me know if you still want me to make this example without overlay
> node.
>
> Regards,
> Navakishore.
On Tue, Mar 5, 2019 at 3:42 AM Nava kishore Manne <[email protected]> wrote:
>
> Hi Rob,
>
> Thanks for the quick response.
> Please find my response inline.
>
> > -----Original Message-----
> > From: Rob Herring [mailto:[email protected]]
> > Sent: Monday, March 4, 2019 10:57 PM
> > To: Nava kishore Manne <[email protected]>
> > Cc: [email protected]; Michal Simek <[email protected]>; Rajan Vaja
> > <[email protected]>; [email protected]; linux-
> > [email protected]; [email protected]; Jolly Shah
> > <[email protected]>; [email protected]
> > Subject: Re: [PATCH v3 6/6] dt-bindings: fpga: Add bindings for ZynqMP fpga
> > driver
Please fix your mail program to...
> > On Mon, Mar 4, 2019 at 5:35 AM Nava kishore Manne <[email protected]>
> > wrote:
...use this style reply header.
[...]
> > > Device Tree Example for Full Reconfiguration
> > > ============================================
> > >
> > > Live Device Tree contains:
> > >
> > > zynqmp_pcap: pcap {
> > > compatible = "xlnx,zynqmp-pcap-fpga";
> > > };
> > >
> > > fpga_region0: fpga-region0 {
> >
> > This should be a child of pcap.
> >
> AFAIK we can't put the fpga-region as a child of pcap as both are independent and they refered to each other using phandlers
> I have made this changes by looking into the below reference doc.
> https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/fpga/fpga-region.txt
Indeed. But having them a as child of the firmware node doesn't make
sense either. Putting them at the top level would make more sense. I
don't recall why we didn't make them a child. Maybe regions can span
multiple bridges in the case with bridges.
> > > compatible = "fpga-region";
> > > fpga-mgr = <&zynqmp_pcap>;
> > > #address-cells = <0x1>;
> > > #size-cells = <0x1>;
> > > ranges;
> > > };
> > >
> > > DT Overlay contains:
> >
> > Don't show overlays in examples. Just show a final tree (i.e. base with overlay
> > applied).
>
> To get a better picture for the users i have added this example node with overlays
> I feel it's good to have this info because it will not impact the functionality of PCAP node.
Then feel free to document this somewhere else. As we move to schema
documents, your examples will have to compile and validate against the
schema. I don't want to add applying overlays to the mix.
Rob