2015-12-07 11:22:00

by Alexey Brodkin

Subject: [PATCH] ARC: [axs10x] cap ethernet phy to 100 Mbit/sec

Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.

To make sure networking is stable on the board we're
limiting phy to 100 Mbit.

Signed-off-by: Alexey Brodkin <[email protected]>
Cc: Vineet Gupta <[email protected]>
---
arch/arc/boot/dts/axs10x_mb.dtsi | 1 +
1 file changed, 1 insertion(+)

diff --git a/arch/arc/boot/dts/axs10x_mb.dtsi b/arch/arc/boot/dts/axs10x_mb.dtsi
index f3db321..44a578c 100644
--- a/arch/arc/boot/dts/axs10x_mb.dtsi
+++ b/arch/arc/boot/dts/axs10x_mb.dtsi
@@ -46,6 +46,7 @@
snps,pbl = < 32 >;
clocks = <&apbclk>;
clock-names = "stmmaceth";
+ max-speed = <100>;
};

ehci@0x40000 {
--
2.5.0

2015-12-07 14:09:50

by Vineet Gupta

Subject: Re: [PATCH] ARC: [axs10x] cap ethernet phy to 100 Mbit/sec

On Monday 07 December 2015 04:52 PM, Alexey Brodkin wrote:

Current ARC SDP boards cannot reliably handle 1Gbit
Ethernet connections due to limitations in hardware.

To make sure networking is stable on the board we're
limiting phy to 100 Mbit.

Signed-off-by: Alexey Brodkin <[email protected]><mailto:[email protected]>
Cc: Vineet Gupta <[email protected]><mailto:[email protected]>

LGTM - added to for-curr for 4.4 !

Thx,
-Vineet