Implement ARM errata 814220 for Cortex A7.
This patch has been wroten by Jason Liu years ago but never send upstream.
I have tried to contact the author on multiple email addresses but I haven't
found any valid one...
I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
version 2:
- limite help lines to 80 columns.
- Add Arnd Bergmann acks.
Benjamin Gaignard (2):
ARM: errata 814220-B-Cache maintenance by set/way operations can
execute out of order.
ARM: stm32: select ARM errata 814220
arch/arm/Kconfig | 12 ++++++++++++
arch/arm/mach-stm32/Kconfig | 1 +
arch/arm/mm/cache-v7.S | 3 +++
3 files changed, 16 insertions(+)
--
2.15.0
Description:
The v7 ARM states that all cache and branch predictor maintenance operations
that do not specify an address execute, relative to each other, in program
order. However, because of this erratum, an L2 set/way cache maintenance
operation can overtake an L1 set/way cache maintenance operation, this would
cause the data corruption.
This ERRATA affected the Cortex-A7 and present in r0p2, r0p3, r0p4, r0p5.
This patch is the SW workaround by adding a DSB before changing cache levels as
the ARM ERRATA: ARM/MP: 814220 told in the ARM ERRATA documentation.
Signed-off-by: Jason Liu <[email protected]>
Signed-off-by: Benjamin Gaignard <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
---
version 2:
- limite help lines to 80 columns.
- Add Arnd Bergmann acks.
arch/arm/Kconfig | 12 ++++++++++++
arch/arm/mm/cache-v7.S | 3 +++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 664e918e2624..72b6ed478d1e 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1227,6 +1227,18 @@ config PCI_HOST_ITE8152
default y
select DMABOUNCE
+config ARM_ERRATA_814220
+ bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
+ depends on CPU_V7
+ help
+ The v7 ARM states that all cache and branch predictor maintenance
+ operations that do not specify an address execute, relative to
+ each other, in program order.
+ However, because of this erratum, an L2 set/way cache maintenance
+ operation can overtake an L1 set/way cache maintenance operation.
+ This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
+ r0p4, r0p5.
+
endmenu
menu "Kernel Features"
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 2149b47a0c5a..7ff7b4c197cc 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -163,6 +163,9 @@ loop2:
skip:
add r10, r10, #2 @ increment cache number
cmp r3, r10
+#ifdef CONFIG_ARM_ERRATA_814220
+ dsb
+#endif
bgt flush_levels
finished:
mov r10, #0 @ switch back to cache level 0
--
2.15.0
Make sure that ARM errata 814220 is selected by STM32MP157 SoC
Signed-off-by: Benjamin Gaignard <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
---
arch/arm/mach-stm32/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 713c068b953f..be2403fa3deb 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -46,6 +46,7 @@ if ARCH_MULTI_V7
config MACH_STM32MP157
bool "STMicroelectronics STM32MP157"
+ select ARM_ERRATA_814220
default y
endif # ARMv7-A
--
2.15.0
On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> Implement ARM errata 814220 for Cortex A7.
>
> This patch has been wroten by Jason Liu years ago but never send upstream.
> I have tried to contact the author on multiple email addresses but I haven't
> found any valid one...
> I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
>
> version 2:
> - limite help lines to 80 columns.
> - Add Arnd Bergmann acks.
>
> Benjamin Gaignard (2):
> ARM: errata 814220-B-Cache maintenance by set/way operations can
> execute out of order.
> ARM: stm32: select ARM errata 814220
>
> arch/arm/Kconfig | 12 ++++++++++++
> arch/arm/mach-stm32/Kconfig | 1 +
> arch/arm/mm/cache-v7.S | 3 +++
> 3 files changed, 16 insertions(+)
>
Russel,
If you agree, can I take this series in my STM32 soc tree ?
If yes it will be part of my PR for v5.2.
regards
Alex
On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue
<[email protected]> wrote:
>
>
> On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> > Implement ARM errata 814220 for Cortex A7.
> >
> > This patch has been wroten by Jason Liu years ago but never send upstream.
> > I have tried to contact the author on multiple email addresses but I haven't
> > found any valid one...
> > I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
Adding Jason's NXP e-mail address.
Thanks
Le mar. 23 avr. 2019 à 19:46, Fabio Estevam <[email protected]> a écrit :
>
> On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue
> <[email protected]> wrote:
> >
> >
> > On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> > > Implement ARM errata 814220 for Cortex A7.
> > >
> > > This patch has been wroten by Jason Liu years ago but never send upstream.
> > > I have tried to contact the author on multiple email addresses but I haven't
> > > found any valid one...
> > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
>
> Adding Jason's NXP e-mail address.
Thanks !
Russell, can Alexandre push this series in stm32 tree or you prefer to
merge it yourself ?
Regards,
Benjamin
>
> Thanks
Le mer. 24 avr. 2019 à 09:25, Benjamin Gaignard
<[email protected]> a écrit :
>
> Le mar. 23 avr. 2019 à 19:46, Fabio Estevam <[email protected]> a écrit :
> >
> > On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue
> > <[email protected]> wrote:
> > >
> > >
> > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> > > > Implement ARM errata 814220 for Cortex A7.
> > > >
> > > > This patch has been wroten by Jason Liu years ago but never send upstream.
> > > > I have tried to contact the author on multiple email addresses but I haven't
> > > > found any valid one...
> > > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
> >
> > Adding Jason's NXP e-mail address.
> Thanks !
>
> Russell, can Alexandre push this series in stm32 tree or you prefer to
> merge it yourself ?
>
Hello Russell,
I have push this series in your patch system weeks ago, but nothing happens.
Do I miss something in your process ?
Regards,
Benjamin
> Regards,
> Benjamin
> >
> > Thanks
On Tue, Jun 11, 2019 at 01:42:34PM +0200, Benjamin Gaignard wrote:
> Le mer. 24 avr. 2019 ? 09:25, Benjamin Gaignard
> <[email protected]> a ?crit :
> >
> > Le mar. 23 avr. 2019 ? 19:46, Fabio Estevam <[email protected]> a ?crit :
> > >
> > > On Wed, Feb 27, 2019 at 1:21 PM Alexandre Torgue
> > > <[email protected]> wrote:
> > > >
> > > >
> > > > On 2/14/19 9:31 AM, Benjamin Gaignard wrote:
> > > > > Implement ARM errata 814220 for Cortex A7.
> > > > >
> > > > > This patch has been wroten by Jason Liu years ago but never send upstream.
> > > > > I have tried to contact the author on multiple email addresses but I haven't
> > > > > found any valid one...
> > > > > I have keep Jason's sign-off and just rebase the patch on to v5-rc6.
> > >
> > > Adding Jason's NXP e-mail address.
> > Thanks !
> >
> > Russell, can Alexandre push this series in stm32 tree or you prefer to
> > merge it yourself ?
> >
>
> Hello Russell,
>
> I have push this series in your patch system weeks ago, but nothing happens.
> Do I miss something in your process ?
I'm now running stuff on a shoe-string here, so I only process patches
once or twice a release cycle. That's what happens when your funding
gets severely cut - we are now _really_ struggling as a business, and
so I don't see the current situation being able to be maintained much
further into the future (our income is no longer sufficient to sustain
us as a business.)
However, I'll get to it in the next couple of weeks.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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