v4 -> v5:
- Rebase on next-20230522 (drop regdma, drop external dependencies)
- Reuse sdm845_vbif
- Resize non-DSI INTFs to 0x280 (no TE block)
- Fix up 6375 mdss bindings example
- Rewrite reasoning of dropping the QoS LUT entry in
"drm/msm/dpu: Add SM6350 support"
- pick up tags
- add DSC blocks for both SoCs
No more dependency on INTFTE (merged)
v4: https://lore.kernel.org/r/[email protected]
v3 -> v4:
- Drop adding new QoS LUT entries
- Add safe_lut_tbl for both SoCs
Depends on:
- https://lore.kernel.org/linux-arm-msm/[email protected]/
v3: https://lore.kernel.org/r/[email protected]
v2 -> v3:
- Don't duplicate qcm2290_lm_sblk
- Use DEFAULT_DPU_LINE_WIDTH defines
- Fix up sspp clk assignments for sm6350
- Add 6350-6375-common QoS data straight to the common file
instead of moving it around after adding it
- Fix up iommu compatible order before adding new entries
- Reuse sm6350 msm_mdss_data for sm6375
- INTF_SC7180_MASK -> INTF_SC7280_MASK (enable HCTL) on 6375
- use double tabs in catalog headers
- remove one unused entry in 6350 dpu_qos_lut_entry
- add missing tear IRQs, drop INTF0 irq on 6375
- don't overduplicate DPU bindings, reuse 7180
- Pick up tags
- Rebase on INTF_TE v4 and next-20230504
Depends on:
- https://lore.kernel.org/linux-arm-msm/[email protected]/
v2: https://lore.kernel.org/r/[email protected]
v1 -> v2:
- Rebase on the DPU catalog rework and INTF_TE
- Fix QSEED(3L/4) discrepancies
- Fixed DMA/cursor discrepancies for 6350
- No deduplication, that's gonna be handled in catalogrework 2:
"the return of the catalogrework"
- Split MDSS & DPU binding additions
- Drop "Allow variable SSPP/INTF_BLK size", that got in w/ the rework
- Split MDSS and DPU additions
- Pick up Rob's acks
Depends on (and based on): https://lore.kernel.org/linux-arm-msm/[email protected]/T/#t
v1: https://lore.kernel.org/linux-arm-msm/[email protected]/
Signed-off-by: Konrad Dybcio <[email protected]>
---
Konrad Dybcio (12):
dt-bindings: display/msm: dsi-controller-main: Add SM6350
dt-bindings: display/msm: dsi-controller-main: Add SM6375
dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
dt-bindings: display/msm: Add SM6350 MDSS
dt-bindings: display/msm: Add SM6375 MDSS
drm/msm/dpu: Add SM6350 support
drm/msm: mdss: Add SM6350 support
drm/msm/dpu: Add SM6375 support
drm/msm: mdss: Add SM6375 support
iommu/arm-smmu-qcom: Sort the compatible list alphabetically
iommu/arm-smmu-qcom: Add SM6375 DPU compatible
iommu/arm-smmu-qcom: Add SM6350 DPU compatible
.../bindings/display/msm/dsi-controller-main.yaml | 4 +
.../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++-
.../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 ++++++++++++++++++++
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/msm_mdss.c | 10 +
drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
11 files changed, 792 insertions(+), 3 deletions(-)
---
base-commit: 9f925874281f7e8855855d6210d6e29d844e4307
change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
Best regards,
--
Konrad Dybcio <[email protected]>
Document the SM6375 MDSS.
Signed-off-by: Konrad Dybcio <[email protected]>
---
.../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
1 file changed, 216 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
new file mode 100644
index 000000000000..3aa4f0470c95
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
@@ -0,0 +1,216 @@
+# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm SM6375 Display MDSS
+
+maintainers:
+ - Konrad Dybcio <[email protected]>
+
+description:
+ SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
+ like DPU display controller, DSI and DP interfaces etc.
+
+$ref: /schemas/display/msm/mdss-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-mdss
+
+ clocks:
+ items:
+ - description: Display AHB clock from gcc
+ - description: Display AHB clock
+ - description: Display core clock
+
+ clock-names:
+ items:
+ - const: iface
+ - const: ahb
+ - const: core
+
+ iommus:
+ maxItems: 1
+
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ maxItems: 2
+
+patternProperties:
+ "^display-controller@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dpu
+
+ "^dsi@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ items:
+ - const: qcom,sm6375-dsi-ctrl
+ - const: qcom,mdss-dsi-ctrl
+
+ "^phy@[0-9a-f]+$":
+ type: object
+ properties:
+ compatible:
+ const: qcom,sm6375-dsi-phy-7nm
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,sm6375-dispcc.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ display-subsystem@5e00000 {
+ compatible = "qcom,sm6375-mdss";
+ reg = <0x05e00000 0x1000>;
+ reg-names = "mdss";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ clocks = <&gcc GCC_DISP_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+ clock-names = "iface", "ahb", "core";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ iommus = <&apps_smmu 0x820 0x2>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ display-controller@5e01000 {
+ compatible = "qcom,sm6375-dpu";
+ reg = <0x05e01000 0x8e030>,
+ <0x05eb0000 0x2008>;
+ reg-names = "mdp", "vbif";
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_ROT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
+ <&gcc GCC_DISP_THROTTLE_CORE_CLK>;
+ clock-names = "bus",
+ "iface",
+ "rot",
+ "lut",
+ "core",
+ "vsync",
+ "throttle";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ operating-points-v2 = <&mdp_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDCX>;
+
+ interrupt-parent = <&mdss>;
+ interrupts = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dpu_intf1_out: endpoint {
+ remote-endpoint = <&dsi0_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dpu_intf2_out: endpoint {
+ remote-endpoint = <&dsi1_in>;
+ };
+ };
+ };
+ };
+
+ dsi@5e94000 {
+ compatible = "qcom,sm6375-dsi-ctrl", "qcom,mdss-dsi-ctrl";
+ reg = <0x05e94000 0x400>;
+ reg-names = "dsi_ctrl";
+
+ interrupt-parent = <&mdss>;
+ interrupts = <4>;
+
+ clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+ <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+ <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>;
+ clock-names = "byte",
+ "byte_intf",
+ "pixel",
+ "core",
+ "iface",
+ "bus";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
+
+ operating-points-v2 = <&dsi_opp_table>;
+ power-domains = <&rpmpd SM6375_VDDMX>;
+
+ phys = <&mdss_dsi0_phy>;
+ phy-names = "dsi";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dsi0_in: endpoint {
+ remote-endpoint = <&dpu_intf1_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ dsi0_out: endpoint {
+ };
+ };
+ };
+ };
+
+ mdss_dsi0_phy: phy@5e94400 {
+ compatible = "qcom,sm6375-dsi-phy-7nm";
+ reg = <0x05e94400 0x200>,
+ <0x05e94600 0x280>,
+ <0x05e94900 0x264>;
+ reg-names = "dsi_phy",
+ "dsi_phy_lane",
+ "dsi_pll";
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "iface", "ref";
+ };
+ };
+...
--
2.40.1
Add SM6350 support to the DPU1 driver to enable display output.
It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
{.fl = 0, .lut = 0x0011223344556677 },
due to the lack of support for selecting between portrait and landscape
LUT settings (for danger and safe LUTs) and no full support for
qseed/non-qseed usescases (for QoS LUT).
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Marijn Suijten <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
---
.../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
4 files changed, 180 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
new file mode 100644
index 000000000000..06eba23b0236
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -0,0 +1,173 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef _DPU_6_4_SM6350_H
+#define _DPU_6_4_SM6350_H
+
+static const struct dpu_caps sm6350_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 0x7,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_ubwc_cfg sm6350_ubwc_cfg = {
+ .ubwc_version = DPU_HW_UBWC_VER_20,
+ .ubwc_swizzle = 6,
+ .highest_bank_bit = 1,
+};
+
+static const struct dpu_mdp_cfg sm6350_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = 0,
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+static const struct dpu_ctl_cfg sm6350_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x1000, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x1200, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x1400, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x1600, .len = 0x1dc,
+ .features = BIT(DPU_CTL_ACTIVE_CFG),
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+};
+
+static const struct dpu_sspp_cfg sm6350_sspp[] = {
+ SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x1f8, VIG_SC7180_MASK,
+ sc7180_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
+ SSPP_BLK("sspp_8", SSPP_DMA0, 0x24000, 0x1f8, DMA_SDM845_MASK,
+ sdm845_dma_sblk_0, 1, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA0),
+ SSPP_BLK("sspp_9", SSPP_DMA1, 0x26000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_1, 5, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA1),
+ SSPP_BLK("sspp_10", SSPP_DMA2, 0x28000, 0x1f8, DMA_CURSOR_SDM845_MASK,
+ sdm845_dma_sblk_2, 9, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA2),
+};
+
+static const struct dpu_lm_cfg sm6350_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
+ &sc7180_lm_sblk, PINGPONG_1, LM_0, 0),
+};
+
+static const struct dpu_dspp_cfg sm6350_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+static struct dpu_pingpong_cfg sm6350_pp[] = {
+ PP_BLK("pingpong_0", PINGPONG_0, 0x70000, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
+ -1),
+ PP_BLK("pingpong_1", PINGPONG_1, 0x70800, PINGPONG_SM8150_MASK, 0, sdm845_pp_sblk,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
+ -1),
+};
+
+static const struct dpu_dsc_cfg sm6350_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000, BIT(DPU_DSC_OUTPUT_CTRL)),
+};
+
+static const struct dpu_intf_cfg sm6350_intf[] = {
+ INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
+ INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
+ DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
+ DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
+};
+
+static const struct dpu_perf_cfg sm6350_perf_data = {
+ .max_bw_low = 4200000,
+ .max_bw_high = 5100000,
+ .min_core_ib = 2500000,
+ .min_llcc_ib = 0,
+ .min_dram_ib = 1600000,
+ .min_prefill_lines = 35,
+ /* TODO: confirm danger_lut_tbl */
+ .danger_lut_tbl = {0xffff, 0xffff, 0x0},
+ .safe_lut_tbl = {0xff00, 0xff00, 0xffff},
+ .qos_lut_tbl = {
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile),
+ .entries = sm6350_qos_linear_macrotile
+ },
+ {.nentry = ARRAY_SIZE(sc7180_qos_nrt),
+ .entries = sc7180_qos_nrt
+ },
+ },
+ .cdp_cfg = {
+ {.rd_enable = 1, .wr_enable = 1},
+ {.rd_enable = 1, .wr_enable = 0}
+ },
+ .clk_inefficiency_factor = 105,
+ .bw_inefficiency_factor = 120,
+};
+
+const struct dpu_mdss_cfg dpu_sm6350_cfg = {
+ .caps = &sm6350_dpu_caps,
+ .ubwc = &sm6350_ubwc_cfg,
+ .mdp_count = ARRAY_SIZE(sm6350_mdp),
+ .mdp = sm6350_mdp,
+ .ctl_count = ARRAY_SIZE(sm6350_ctl),
+ .ctl = sm6350_ctl,
+ .sspp_count = ARRAY_SIZE(sm6350_sspp),
+ .sspp = sm6350_sspp,
+ .mixer_count = ARRAY_SIZE(sm6350_lm),
+ .mixer = sm6350_lm,
+ .dspp_count = ARRAY_SIZE(sm6350_dspp),
+ .dspp = sm6350_dspp,
+ .dsc_count = ARRAY_SIZE(sm6350_dsc),
+ .dsc = sm6350_dsc,
+ .pingpong_count = ARRAY_SIZE(sm6350_pp),
+ .pingpong = sm6350_pp,
+ .intf_count = ARRAY_SIZE(sm6350_intf),
+ .intf = sm6350_intf,
+ .vbif_count = ARRAY_SIZE(sdm845_vbif),
+ .vbif = sdm845_vbif,
+ .perf = &sm6350_perf_data,
+ .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
+ BIT(MDP_SSPP_TOP0_INTR2) | \
+ BIT(MDP_SSPP_TOP0_HIST_INTR) | \
+ BIT(MDP_INTF0_INTR) | \
+ BIT(MDP_INTF1_INTR) | \
+ BIT(MDP_INTF1_TEAR_INTR),
+};
+
+#endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1dee5ba2b312..6e338d569632 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -689,6 +689,10 @@ static const struct dpu_qos_lut_entry sc7180_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222335777},
};
+static const struct dpu_qos_lut_entry sm6350_qos_linear_macrotile[] = {
+ {.fl = 0, .lut = 0x0011223445566777 },
+};
+
static const struct dpu_qos_lut_entry sm8150_qos_linear[] = {
{.fl = 0, .lut = 0x0011222222223357 },
};
@@ -744,6 +748,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
#include "catalog/dpu_6_0_sm8250.h"
#include "catalog/dpu_6_2_sc7180.h"
#include "catalog/dpu_6_3_sm6115.h"
+#include "catalog/dpu_6_4_sm6350.h"
#include "catalog/dpu_6_5_qcm2290.h"
#include "catalog/dpu_7_0_sm8350.h"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..ed4311f6aaf0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -834,6 +834,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
+extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
extern const struct dpu_mdss_cfg dpu_sm8350_cfg;
extern const struct dpu_mdss_cfg dpu_sc7280_cfg;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 8ce057cc9374..d9925097626c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1328,6 +1328,7 @@ static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
+ { .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
{ .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
{ .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
--
2.40.1
On 23/05/2023 10:46, Konrad Dybcio wrote:
> Add SM6350 support to the DPU1 driver to enable display output.
>
> It's worth noting that one entry dpu_qos_lut_entry was trimmed off:
>
> {.fl = 0, .lut = 0x0011223344556677 },
>
> due to the lack of support for selecting between portrait and landscape
> LUT settings (for danger and safe LUTs) and no full support for
> qseed/non-qseed usescases (for QoS LUT).
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> Reviewed-by: Marijn Suijten <[email protected]>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 5 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 +
> 4 files changed, 180 insertions(+)
Reviewed-by: Dmitry Baryshkov <[email protected]>
--
With best wishes
Dmitry
On 23/05/2023 10:46, Konrad Dybcio wrote:
[skipped the changelog]
> ---
> Konrad Dybcio (12):
> dt-bindings: display/msm: dsi-controller-main: Add SM6350
> dt-bindings: display/msm: dsi-controller-main: Add SM6375
> dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
> dt-bindings: display/msm: Add SM6350 MDSS
> dt-bindings: display/msm: Add SM6375 MDSS
> drm/msm/dpu: Add SM6350 support
> drm/msm: mdss: Add SM6350 support
> drm/msm/dpu: Add SM6375 support
> drm/msm: mdss: Add SM6375 support
> iommu/arm-smmu-qcom: Sort the compatible list alphabetically
> iommu/arm-smmu-qcom: Add SM6375 DPU compatible
> iommu/arm-smmu-qcom: Add SM6350 DPU compatible
As we are now nearly ready to merge this series, Will, Robin, what
should be the merge strategy for these three patches? Would you take
them through the arm-smmu/iommu tree?
>
> .../bindings/display/msm/dsi-controller-main.yaml | 4 +
> .../bindings/display/msm/qcom,sc7180-dpu.yaml | 23 ++-
> .../bindings/display/msm/qcom,sm6350-mdss.yaml | 214 ++++++++++++++++++++
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h | 173 +++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h | 139 +++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 6 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
> drivers/gpu/drm/msm/msm_mdss.c | 10 +
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 6 +-
> 11 files changed, 792 insertions(+), 3 deletions(-)
> ---
> base-commit: 9f925874281f7e8855855d6210d6e29d844e4307
> change-id: 20230411-topic-straitlagoon_mdss-8f34cacd5e26
>
> Best regards,
--
With best wishes
Dmitry
On 23/05/2023 09:46, Konrad Dybcio wrote:
> Document the SM6375 MDSS.
>
> Signed-off-by: Konrad Dybcio <[email protected]>
> ---
> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> 1 file changed, 216 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
> new file mode 100644
> index 000000000000..3aa4f0470c95
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
> @@ -0,0 +1,216 @@
> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm SM6375 Display MDSS
> +
> +maintainers:
> + - Konrad Dybcio <[email protected]>
> +
> +description:
> + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
> + like DPU display controller, DSI and DP interfaces etc.
> +
> +$ref: /schemas/display/msm/mdss-common.yaml#
> +
> +properties:
> + compatible:
> + items:
> + - const: qcom,sm6375-mdss
> +
Same as 6350 - drop items.
Similar concern about interconnects, although we don't have header file
for them, so I assume we will fill it up later.
Best regards,
Krzysztof
On Mon, 5 Jun 2023 at 18:43, Will Deacon <[email protected]> wrote:
>
> On Thu, Jun 01, 2023 at 03:16:52AM +0300, Dmitry Baryshkov wrote:
> > On 23/05/2023 10:46, Konrad Dybcio wrote:
> >
> > [skipped the changelog]
> >
> > > ---
> > > Konrad Dybcio (12):
> > > dt-bindings: display/msm: dsi-controller-main: Add SM6350
> > > dt-bindings: display/msm: dsi-controller-main: Add SM6375
> > > dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
> > > dt-bindings: display/msm: Add SM6350 MDSS
> > > dt-bindings: display/msm: Add SM6375 MDSS
> > > drm/msm/dpu: Add SM6350 support
> > > drm/msm: mdss: Add SM6350 support
> > > drm/msm/dpu: Add SM6375 support
> > > drm/msm: mdss: Add SM6375 support
> > > iommu/arm-smmu-qcom: Sort the compatible list alphabetically
> > > iommu/arm-smmu-qcom: Add SM6375 DPU compatible
> > > iommu/arm-smmu-qcom: Add SM6350 DPU compatible
> >
> > As we are now nearly ready to merge this series, Will, Robin, what should be
> > the merge strategy for these three patches? Would you take them through the
> > arm-smmu/iommu tree?
>
> I'm happy to take the three IOMMU changes, but the bulk of this series is
> replated to display and GPU so I don't think it makes sense for me to take
> those.
Could you please then ack merging them through the msm-next?
--
With best wishes
Dmitry
On Thu, Jun 01, 2023 at 03:16:52AM +0300, Dmitry Baryshkov wrote:
> On 23/05/2023 10:46, Konrad Dybcio wrote:
>
> [skipped the changelog]
>
> > ---
> > Konrad Dybcio (12):
> > dt-bindings: display/msm: dsi-controller-main: Add SM6350
> > dt-bindings: display/msm: dsi-controller-main: Add SM6375
> > dt-bindings: display/msm: sc7180-dpu: Describe SM6350 and SM6375
> > dt-bindings: display/msm: Add SM6350 MDSS
> > dt-bindings: display/msm: Add SM6375 MDSS
> > drm/msm/dpu: Add SM6350 support
> > drm/msm: mdss: Add SM6350 support
> > drm/msm/dpu: Add SM6375 support
> > drm/msm: mdss: Add SM6375 support
> > iommu/arm-smmu-qcom: Sort the compatible list alphabetically
> > iommu/arm-smmu-qcom: Add SM6375 DPU compatible
> > iommu/arm-smmu-qcom: Add SM6350 DPU compatible
>
> As we are now nearly ready to merge this series, Will, Robin, what should be
> the merge strategy for these three patches? Would you take them through the
> arm-smmu/iommu tree?
I'm happy to take the three IOMMU changes, but the bulk of this series is
replated to display and GPU so I don't think it makes sense for me to take
those.
Will
On 4.06.2023 20:04, Krzysztof Kozlowski wrote:
> On 23/05/2023 09:46, Konrad Dybcio wrote:
>> Document the SM6375 MDSS.
>>
>> Signed-off-by: Konrad Dybcio <[email protected]>
>> ---
>> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
>> 1 file changed, 216 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
>> new file mode 100644
>> index 000000000000..3aa4f0470c95
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
>> @@ -0,0 +1,216 @@
>> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Qualcomm SM6375 Display MDSS
>> +
>> +maintainers:
>> + - Konrad Dybcio <[email protected]>
>> +
>> +description:
>> + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
>> + like DPU display controller, DSI and DP interfaces etc.
>> +
>> +$ref: /schemas/display/msm/mdss-common.yaml#
>> +
>> +properties:
>> + compatible:
>> + items:
>> + - const: qcom,sm6375-mdss
>> +
>
> Same as 6350 - drop items.
Ack
>
> Similar concern about interconnects, although we don't have header file
> for them, so I assume we will fill it up later.
Yep, they'll come later and other SoCs may need a bump up for a third icc
path soon..
Konrad
>
> Best regards,
> Krzysztof
>
On Mon, 5 Jun 2023 at 20:01, Konrad Dybcio <[email protected]> wrote:
>
>
>
> On 4.06.2023 20:04, Krzysztof Kozlowski wrote:
> > On 23/05/2023 09:46, Konrad Dybcio wrote:
> >> Document the SM6375 MDSS.
> >>
> >> Signed-off-by: Konrad Dybcio <[email protected]>
> >> ---
> >> .../bindings/display/msm/qcom,sm6375-mdss.yaml | 216 +++++++++++++++++++++
> >> 1 file changed, 216 insertions(+)
> >>
> >> diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
> >> new file mode 100644
> >> index 000000000000..3aa4f0470c95
> >> --- /dev/null
> >> +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6375-mdss.yaml
> >> @@ -0,0 +1,216 @@
> >> +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
> >> +%YAML 1.2
> >> +---
> >> +$id: http://devicetree.org/schemas/display/msm/qcom,sm6375-mdss.yaml#
> >> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> >> +
> >> +title: Qualcomm SM6375 Display MDSS
> >> +
> >> +maintainers:
> >> + - Konrad Dybcio <[email protected]>
> >> +
> >> +description:
> >> + SM6375 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
> >> + like DPU display controller, DSI and DP interfaces etc.
> >> +
> >> +$ref: /schemas/display/msm/mdss-common.yaml#
> >> +
> >> +properties:
> >> + compatible:
> >> + items:
> >> + - const: qcom,sm6375-mdss
> >> +
> >
> > Same as 6350 - drop items.
> Ack
>
> >
> > Similar concern about interconnects, although we don't have header file
> > for them, so I assume we will fill it up later.
> Yep, they'll come later and other SoCs may need a bump up for a third icc
> path soon..
4th ;-)
>
> Konrad
> >
> > Best regards,
> > Krzysztof
> >
--
With best wishes
Dmitry