2023-01-12 13:24:59

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 00/12] RkVDEC HEVC driver

Implement the HEVC codec variation for the RkVDEC driver. Currently only
the RK3399 is supported, but it is possible to enable the RK3288 as it
also supports this codec.

Changelog:

Changes since V1:
- Adjust NV15 documentation according to review requests by Laurent
- Add a new callback to check whether the supplied SPS (H264/HEVC) is
compatible with the provided pixel format on the OUTPUT queue. This is used
to ensure that streaming is only started with a compatible SPS and to unset
the SPS in case a new OUTPUT queue pixel format is set which is not
compatible with the latest SPS.
- Add a new callback to return a structure filled with major SPS attributes
shared by HEVC/H264 in a human readable format.
(e.g. subsampling=420 instead of chroma_format_idc=1, resolution in pixels
and bitdepth + 8)
The idea is to reduce code duplication when fetching those values and calculating
the actual width & height and to make the code more readable and self-documenting.
- Rework the SPS validation function from H264 to act as the SPS validation
callback, add helpful error messages to the checks
- Rework the way the SPS is stored in the driver and how the valid format is
determined. The general workflow is:
* Set the output format
* Try & Set the SPS control
* Driver figures out a matching CAPTURE queue format for the provided SPS and
stores the SPS in the internal context
* start streaming & prepare buffers & device_run ...
User-space is also allowed to change the SPS control at anytime, but it is
only accepted when no buffers are queued on the CAPTURE queue. Whenever the
driver needs to know the currently valid CAPTURE queue format, then it will
utilize the SPS in the context.
- Remove the new bit writer, as this tool should rather be implemented in a
general manner in a separate patch instead of as a part of this series.
- Ensure that streaming is only started once both queues are running
- Update copyright dates for my changes

The HEVC codec has been tested with the GStreamer V4L2 HEVC plugin.

As general changes were made to the RkVDEC driver I have tested all 3 supported
codecs with GStreamer.

Current Fluster score:
HEVC:
`Ran 134/147 tests successfully in 282.692 secs`
with
`python3 fluster.py run -d GStreamer-H.265-V4L2SL-Gst1.0 -ts JCT-VC-HEVC_V1 -j1`

H264:
`Ran 129/135 tests successfully in 78.950 secs`
with
`python3 fluster.py run -d GStreamer-H.264-V4L2SL-Gst1.0 -ts JVT-AVC_V1 -j1`

VP9:
`Ran 228/303 tests successfully in 327.417 secs`
with
`python3 fluster.py run -d GStreamer-VP9-V4L2SL-Gst1.0 -ts VP9-TEST-VECTORS -j1`

No regressions detected.

failed conformance tests:
- DBLK_D_VIXS_2 (Success on Hantro G2)
- DSLICE_A_HHI_5 (Success on Hantro G2)
- EXT_A_ericsson_4 (Success on Hantro G2)
- PICSIZE_A_Bossen_1 (Hardware limitation)
- PICSIZE_B_Bossen_1 (Hardware limitation)
- PICSIZE_C_Bossen_1 (Hardware limitation)
- PICSIZE_D_Bossen_1 (Hardware limitation)
- PPS_A_qualcomm_7 (Success on Hantro G2)
- SAODBLK_A_MainConcept_4 (Success on Hantro G2)
- SAODBLK_B_MainConcept_4 (Success on Hantro G2)
- TSUNEQBD_A_MAIN10_Technicolor_2 (Success on Hantro G2)
- VPSSPSPPS_A_MainConcept_1 (Success on Hantro G2)
- WPP_D_ericsson_MAIN10_2 (Fail on Hantro G2)
- WPP_D_ericsson_MAIN_2 (Fail on Hantro G2)

Not tested with FFMpeg so far.

Known issues:
- Unable to reliably decode multiple videos concurrently
- The SAODBLK_* tests timeout if the timeout time in fluster is lower than 120
- Currently the uv_virstride is calculated in a manner that is hardcoded
for the two available formats NV12 and NV15. (@config_registers)

Notable design decisions:
- The giant static array of cabac values is moved to a separate c file,
I did so because a separate .h file would be incorrect as it doesn't
expose anything of any value for any other file than the rkvdec-hevc.c
file. Other options were:
- Calculating the values instead of storing the results (No clear pattern
found for the calculation using the static array and the formulas from the
specification)
- Supply them via firmware (Adding firmware makes the whole software
way more complicated and the usage of the driver less obvious)

Ignored Checkpatch warnings:
```
WARNING: line length of 162 exceeds 100 columns

+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2,

ERROR: trailing statements should be on next line

+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/CbCr 4:2:0 (Packed)"; break;
```

v4l2-compliance test:
```
v4l2-compliance 1.23.0-4989, 64 bits, 64-bit time_t
v4l2-compliance SHA: b3527e08fbbc 2023-01-10 11:22:13

Total for rkvdec device /dev/video1: 46, Succeeded: 46, Failed: 0, Warnings: 0
```

To: Mauro Carvalho Chehab <[email protected]>
To: Ezequiel Garcia <[email protected]>
To: Greg Kroah-Hartman <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Jonas Karlman <[email protected]>
Cc: Alex Bee <[email protected]>
Cc: Nicolas Dufresne <[email protected]>
Cc: Collabora Kernel-domain <[email protected]>
Cc: Robert Beckett <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: Andrzej Pietrasiewicz <[email protected]>
Cc: Benjamin Gaignard <[email protected]>

---
Jonas Karlman (2):
media: v4l2: Add NV15 pixel format
media: v4l2-common: Add helpers to calculate bytesperline and sizeimage

Sebastian Fricke (10):
staging: media: rkvdec: Helper for buffer queue busy check
staging: media: rkvdec: Block start streaming until both queues run
staging: media: rkvdec: Add SPS structure to internal context
staging: media: rkvdec: Add a valid pixel format check as callback
staging: media: rkvdec: Add a routine to fetch SPS attributes as a callback
staging: media: rkvdec: Add a valid SPS check as a callback
staging: media: rkvdec: h264: Add callbacks for h264
staging: media: rkvdec: Wrapper for pixel format preparation
staging: media: rkvdec: Enable S_CTRL IOCTL
staging: media: rkvdec: Add HEVC backend

.../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 +
drivers/media/v4l2-core/v4l2-common.c | 79 +-
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/TODO | 11 +-
drivers/staging/media/rkvdec/rkvdec-h264.c | 105 +-
drivers/staging/media/rkvdec/rkvdec-hevc-data.c | 1845 ++++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 910 ++++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 300 +++-
drivers/staging/media/rkvdec/rkvdec.h | 14 +
include/uapi/linux/videodev2.h | 1 +
12 files changed, 3244 insertions(+), 100 deletions(-)
---
base-commit: 6599e683db1bf22fee74302c47e31b9a42a1c3d2
change-id: 20230101-patch-series-v2-6-2-rc1-be130fda994d

Best regards,
--
Sebastian Fricke <[email protected]>


2023-01-12 13:27:47

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format

From: Jonas Karlman <[email protected]>

Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers.

NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no
padding between components. Instead, luminance and chrominance samples are grouped
into 4s so that each group is packed into an integer number of bytes:

YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes

The '15' suffix refers to the optimum effective bits per pixel
which is achieved when the total number of luminance samples is a multiple
of 8 for NV15.

Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Sebastian Fricke <[email protected]>
---
.../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 ++++++++++++++++++++++
drivers/media/v4l2-core/v4l2-common.c | 2 +
drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
include/uapi/linux/videodev2.h | 1 +
4 files changed, 79 insertions(+)

diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
index f1d5bb7b806d..7d8d228f8063 100644
--- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
+++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
@@ -79,6 +79,13 @@ All components are stored with the same number of bits per component.
- Cr, Cb
- Yes
- Linear
+ * - V4L2_PIX_FMT_NV15
+ - 'NV15'
+ - 15
+ - 4:2:0
+ - Cb, Cr
+ - Yes
+ - Linear
* - V4L2_PIX_FMT_NV12M
- 'NM12'
- 8
@@ -183,6 +190,7 @@ horizontally.

.. _V4L2-PIX-FMT-NV12:
.. _V4L2-PIX-FMT-NV21:
+.. _V4L2-PIX-FMT-NV15:
.. _V4L2-PIX-FMT-NV12M:
.. _V4L2-PIX-FMT-NV21M:
.. _V4L2-PIX-FMT-P010:
@@ -586,6 +594,73 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord
- Cb\ :sub:`11`
- Cr\ :sub:`11`

+.. _V4L2_PIX_FMT_NV15:
+
+NV15
+----
+
+Similar to P010, a semi-planar 10-bit Y/CbCr format, but all components are
+packed without any padding between each other. As a side-effect, each group of
+4 components are stored over 5 bytes (YYYY or UVUV = 4 * 10 bits = 40 bits = 5
+bytes).
+
+.. flat-table:: Sample 4x4 NV15 Image
+ :header-rows: 0
+ :stub-columns: 0
+
+ * - start + 0:
+ - Y'\ :sub:`00`
+ - Y'\ :sub:`01`
+ - Y'\ :sub:`02`
+ - Y'\ :sub:`03`
+ * - start + 8:
+ - Y'\ :sub:`04`
+ - Y'\ :sub:`10`
+ - Y'\ :sub:`11`
+ - Y'\ :sub:`12`
+ * - start + 16:
+ - Y'\ :sub:`13`
+ - Y'\ :sub:`14`
+ - Y'\ :sub:`20`
+ - Y'\ :sub:`21`
+ * - start + 24:
+ - Y'\ :sub:`22`
+ - Y'\ :sub:`23`
+ - Y'\ :sub:`24`
+ - Y'\ :sub:`30`
+ * - start + 32:
+ - Y'\ :sub:`31`
+ - Y'\ :sub:`32`
+ - Y'\ :sub:`33`
+ - Y'\ :sub:`34`
+
+ * - start + 0:
+ - Cb\ :sub:`00`
+ - Cr\ :sub:`00`
+ - Cb\ :sub:`01`
+ - Cr\ :sub:`01`
+ * - start + 8:
+ - Cb\ :sub:`02`
+ - Cr\ :sub:`02`
+ - Cb\ :sub:`03`
+ - Cr\ :sub:`03`
+ * - start + 16:
+ - Cb\ :sub:`04`
+ - Cr\ :sub:`04`
+ - Cb\ :sub:`10`
+ - Cr\ :sub:`10`
+ * - start + 24:
+ - Cb\ :sub:`11`
+ - Cr\ :sub:`11`
+ - Cb\ :sub:`12`
+ - Cr\ :sub:`12`
+ * - start + 32:
+ - Cb\ :sub:`13`
+ - Cr\ :sub:`13`
+ - Cb\ :sub:`14`
+ - Cr\ :sub:`14`
+
+.. raw:: latex

Fully Planar YUV Formats
========================
diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
index 40f56e044640..be23e319fb3a 100644
--- a/drivers/media/v4l2-core/v4l2-common.c
+++ b/drivers/media/v4l2-core/v4l2-common.c
@@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
/* YUV planar formats */
{ .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
{ .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
+ { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2,
+ .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
{ .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
{ .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
index 8e0a0ff62a70..1c80ad78ef00 100644
--- a/drivers/media/v4l2-core/v4l2-ioctl.c
+++ b/drivers/media/v4l2-core/v4l2-ioctl.c
@@ -1343,6 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
+ case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
index 1befd181a4cc..e9731286dc77 100644
--- a/include/uapi/linux/videodev2.h
+++ b/include/uapi/linux/videodev2.h
@@ -621,6 +621,7 @@ struct v4l2_pix_format {
/* two planes -- one Y, one Cr + Cb interleaved */
#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
#define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
+#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
#define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
#define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
#define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */

--
2.25.1

2023-01-12 13:27:51

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 12/12] staging: media: rkvdec: Add HEVC backend

The Rockchip VDEC supports the HEVC codec with the Main and Main10
Profile up to Level 5.1 High Tier: 4096x2304@60 fps.
Add the backend for that format to the decoder.

Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Alex Bee <[email protected]>
Signed-off-by: Nicolas Dufresne <[email protected]>
Signed-off-by: Sebastian Fricke <[email protected]>
---
drivers/staging/media/rkvdec/Makefile | 2 +-
drivers/staging/media/rkvdec/TODO | 11 +-
drivers/staging/media/rkvdec/rkvdec-hevc-data.c | 1845 +++++++++++++++++++++++
drivers/staging/media/rkvdec/rkvdec-hevc.c | 910 +++++++++++
drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
drivers/staging/media/rkvdec/rkvdec.c | 72 +
drivers/staging/media/rkvdec/rkvdec.h | 1 +
7 files changed, 2834 insertions(+), 8 deletions(-)

diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
index cb86b429cfaa..a77122641d14 100644
--- a/drivers/staging/media/rkvdec/Makefile
+++ b/drivers/staging/media/rkvdec/Makefile
@@ -1,3 +1,3 @@
obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o

-rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
+rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO
index 2c0779383276..58652251241b 100644
--- a/drivers/staging/media/rkvdec/TODO
+++ b/drivers/staging/media/rkvdec/TODO
@@ -1,11 +1,8 @@
-* Support for HEVC is planned for this driver.
-
- Given the V4L controls for that CODEC will be part of
- the uABI, it will be required to have the driver in staging.
-
- For this reason, we are keeping this driver in staging for now.
-
* Evaluate introducing a helper to consolidate duplicated
code in rkvdec_request_validate and cedrus_request_validate.
The helper needs to the driver private data associated with
the videobuf2 queue, from a media request.
+
+* Add support for other hardware revisions (like RK3288 etc.)
+
+* Fix concurrent decoding for the HEVC codec
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
new file mode 100644
index 000000000000..d3b7760063ef
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
@@ -0,0 +1,1845 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder driver
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <[email protected]>
+ */
+#include <linux/types.h>
+
+#define RKV_CABAC_TABLE_SIZE 27456
+
+static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
+ 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f,
+ 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40,
+ 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60,
+ 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50,
+ 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68,
+ 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60,
+ 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58,
+ 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07,
+ 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40,
+ 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37,
+ 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57,
+ 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40,
+ 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e,
+ 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f,
+ 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
+ 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47,
+ 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47,
+ 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37,
+ 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10,
+ 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27,
+ 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07,
+ 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
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+ 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00,
+ 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08,
+ 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40,
+ 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17,
+ 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f,
+ 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f,
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+ 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47,
+ 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07,
+ 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47,
+ 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f,
+ 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37,
+ 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
new file mode 100644
index 000000000000..d3802ba613ab
--- /dev/null
+++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
@@ -0,0 +1,910 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Rockchip Video Decoder HEVC backend
+ *
+ * Copyright (C) 2023 Collabora, Ltd.
+ * Sebastian Fricke <[email protected]>
+ *
+ * Copyright (C) 2019 Collabora, Ltd.
+ * Boris Brezillon <[email protected]>
+ *
+ * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
+ * Jeffy Chen <[email protected]>
+ */
+
+#include <media/v4l2-mem2mem.h>
+
+#include "rkvdec.h"
+#include "rkvdec-regs.h"
+#include "rkvdec-hevc-data.c"
+
+/* Size in u8/u32 units. */
+#define RKV_SCALING_LIST_SIZE 1360
+#define SCALING_LIST_SIZE_NUM 4
+#define RKV_PPS_SIZE (80 / 4)
+#define RKV_PPS_LEN 64
+#define RKV_RPS_SIZE (32 / 4)
+#define RKV_RPS_LEN 600
+#define RKV_PPS_MAX_COLUMNS 20
+#define RKV_PPS_MAX_ROWS 22
+#define RKV_RPS_MAX_REFERENCES 15
+#define RKV_MAX_DEPTH_IN_BYTES 2
+
+struct rkvdec_sps_pps_packet {
+ u32 info[RKV_PPS_SIZE];
+};
+
+struct rkvdec_rps_packet {
+ u32 info[RKV_RPS_SIZE];
+};
+
+struct rkvdec_ps_field {
+ u16 offset;
+ u8 len;
+};
+
+#define PS_FIELD(_offset, _len) \
+ ((struct rkvdec_ps_field){ _offset, _len })
+
+/* SPS */
+#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)
+#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
+#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
+#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
+#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
+#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
+#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
+#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
+#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
+#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
+#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
+#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
+#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
+#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
+#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
+#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
+#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
+#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
+#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
+#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
+#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
+#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
+#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
+#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
+#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
+#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
+#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
+#define PPS_MBZ_1 PS_FIELD(100, 7)
+#define PPS_MBO_1 PS_FIELD(107, 21)
+/* PPS */
+#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
+#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
+#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
+#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
+#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
+#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
+#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
+#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
+#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
+#define INIT_QP_MINUS26 PS_FIELD(163, 7)
+#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
+#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
+#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
+#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
+#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
+#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
+#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
+#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
+#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
+#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
+#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
+#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
+#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
+#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
+#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
+#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
+#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
+#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
+#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
+#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
+#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
+#define PPS_MBZ_2 PS_FIELD(209, 3)
+#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
+#define NUM_TILE_ROWS PS_FIELD(217, 5)
+#define PPS_M_MODE PS_FIELD(222, 2)
+#define PPS_MBO_2 PS_FIELD(224, 30)
+#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
+#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
+#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
+#define PPS_MBO_3 PS_FIELD(624, 16)
+
+/* Data structure describing auxiliary buffer format. */
+struct rkvdec_hevc_priv_tbl {
+ u8 cabac_table[RKV_CABAC_TABLE_SIZE];
+ u8 scaling_list[RKV_SCALING_LIST_SIZE];
+ struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
+ struct rkvdec_rps_packet rps[RKV_RPS_LEN];
+};
+
+struct rkvdec_hevc_run {
+ struct rkvdec_run base;
+ const struct v4l2_ctrl_hevc_slice_params *slices_params;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps;
+ const struct v4l2_ctrl_hevc_pps *pps;
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
+ int num_slices;
+};
+
+struct rkvdec_hevc_ctx {
+ struct rkvdec_aux_buf priv_tbl;
+ struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
+};
+
+struct scaling_factor {
+ u8 scalingfactor0[1248];
+ u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
+ u8 scalingdc[12]; /*N1005 Vienna Meeting*/
+ u8 reserved[4]; /*16Bytes align*/
+};
+
+static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
+{
+ u8 bit = field.offset % 32, word = field.offset / 32;
+ u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
+ u64 val = ((u64)value << bit) & mask;
+
+ buf[word] &= ~mask;
+ buf[word] |= val;
+ if (bit + field.len > 32) {
+ buf[word + 1] &= ~(mask >> 32);
+ buf[word + 1] |= val >> 32;
+ }
+}
+
+static void assemble_hw_pps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_pps *pps = run->pps;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_sps_pps_packet *hw_ps;
+ u8 pcm_enabled = 0;
+ u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
+ u32 width, height, max_min_cb_size, x, pic_in_cts_width, pic_in_cts_height;
+ u32 log2_min_cu_qp_delta_size, scaling_distance;
+ dma_addr_t scaling_list_address;
+ int i;
+ u32 tmp_w = 0;
+ u32 prev_w = 0;
+ u32 tmp_h = 0;
+ u32 prev_h = 0;
+ u16 column_width[RKV_PPS_MAX_COLUMNS] = {0};
+ u16 row_height[RKV_PPS_MAX_ROWS] = {0};
+
+ /*
+ * HW read the SPS/PPS information from PPS packet index by PPS id.
+ * offset from the base can be calculated by PPS_id * 80 (size per PPS
+ * packet unit). so the driver copy SPS/PPS information to the exact PPS
+ * packet unit for HW accessing.
+ */
+ hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
+ width = sps->pic_width_in_luma_samples;
+ height = sps->pic_height_in_luma_samples;
+ max_min_cb_size = sps->log2_diff_max_min_luma_coding_block_size;
+
+#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)
+ /* write sps */
+ WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
+ WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
+ WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
+ WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
+ WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
+ LOG2_MAX_PIC_ORDER_CNT_LSB);
+ WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
+ LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
+ LOG2_MIN_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
+ LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
+ WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
+ MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
+ SCALING_LIST_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
+ AMP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
+ SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
+ pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
+ WRITE_PPS(pcm_enabled, PCM_ENABLED_FLAG);
+ WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0,
+ PCM_SAMPLE_BIT_DEPTH_LUMA);
+ WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0,
+ PCM_SAMPLE_BIT_DEPTH_CHROMA);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
+ PCM_LOOP_FILTER_DISABLED_FLAG);
+ WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
+ LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0,
+ LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
+ WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
+ LONG_TERM_REF_PICS_PRESENT_FLAG);
+ WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
+ SPS_TEMPORAL_MVP_ENABLED_FLAG);
+ WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
+ STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
+ WRITE_PPS(0, PPS_MBZ_1);
+ WRITE_PPS(0x1fffff, PPS_MBO_1);
+
+ /* write pps */
+ WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
+ WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
+ DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
+ OUTPUT_FLAG_PRESENT_FLAG);
+ WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
+ SIGN_DATA_HIDING_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
+ CABAC_INIT_PRESENT_FLAG);
+ WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
+ NUM_REF_IDX_L0_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
+ NUM_REF_IDX_L1_DEFAULT_ACTIVE);
+ WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
+ CONSTRAINED_INTRA_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
+ TRANSFORM_SKIP_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
+ CU_QP_DELTA_ENABLED_FLAG);
+
+ ctb_log2_size_y = min_cb_log2_size_y +
+ sps->log2_diff_max_min_luma_coding_block_size;
+ ctb_size_y = 1 << ctb_log2_size_y;
+ log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
+ WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
+ WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
+ WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
+ PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
+ WEIGHTED_PRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
+ WEIGHTED_BIPRED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
+ TRANSQUANT_BYPASS_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
+ TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
+ ENTROPY_CODING_SYNC_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
+ PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
+ LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
+ DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
+ PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
+ WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
+ WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
+ LISTS_MODIFICATION_PRESENT_FLAG);
+ WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
+ WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
+ SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
+ WRITE_PPS(0, PPS_MBZ_2);
+ WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
+ WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
+ WRITE_PPS(3, PPS_M_MODE);
+ WRITE_PPS(0x3fffffff, PPS_MBO_2);
+
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
+ if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) {
+ x = 1 << (min_cb_log2_size_y + max_min_cb_size);
+ pic_in_cts_width = (width + x - 1) / (x);
+ pic_in_cts_height = (height + x - 1) / (x);
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++) {
+ tmp_w = ((i + 1) * pic_in_cts_width) /
+ (pps->num_tile_columns_minus1 + 1);
+ column_width[i] = tmp_w - prev_w - 1;
+ prev_w = tmp_w;
+ }
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++) {
+ tmp_h = ((i + 1) * pic_in_cts_height) /
+ (pps->num_tile_rows_minus1 + 1);
+ row_height[i] = tmp_h - prev_h - 1;
+ prev_h = tmp_h;
+ }
+ } else {
+ for (i = 0; i <= pps->num_tile_columns_minus1; i++)
+ column_width[i] = pps->column_width_minus1[i];
+ for (i = 0; i <= pps->num_tile_rows_minus1; i++)
+ row_height[i] = pps->row_height_minus1[i];
+ }
+ } else {
+ column_width[0] =
+ ((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1;
+ row_height[0] =
+ ((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1;
+ }
+
+ for (i = 0; i < RKV_PPS_MAX_COLUMNS; i++)
+ WRITE_PPS(column_width[i], COLUMN_WIDTH(i));
+ for (i = 0; i < RKV_PPS_MAX_ROWS; i++)
+ WRITE_PPS(row_height[i], ROW_HEIGHT(i));
+
+ scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
+ scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
+ WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
+ WRITE_PPS(0xffff, PPS_MBO_3);
+}
+
+/*
+ * Creation of the Reference Picture Set memory blob for the hardware.
+ * The layout looks like this:
+ * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
+ * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
+ * + 4 bits of the 13th reference)
+ * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
+ * 21 bits for L1 (4 references + first bit of 5)
+ * [3] 32 bits of padding with 0s
+ * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
+ * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
+ * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
+ * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
+ * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
+ * [7] 32 bits of padding with 0s
+ *
+ * Thus we have to set up padding in between reference 5 of the L1 list.
+ */
+static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_sps *sps = run->sps;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params;
+ const struct v4l2_hevc_dpb_entry *dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
+ struct rkvdec_rps_packet *hw_ps;
+ int i, j;
+ unsigned int lowdelay;
+
+#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)
+
+#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
+#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
+#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
+#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
+
+#define LOWDELAY PS_FIELD(182, 1)
+#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
+#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
+#define NUM_RPS_POC PS_FIELD(202, 4)
+
+ for (j = 0; j < run->num_slices; j++) {
+ uint st_bit_offset = 0;
+ uint num_l0_refs = 0;
+ uint num_l1_refs = 0;
+
+ sl_params = &run->slices_params[j];
+ dpb = decode_params->dpb;
+
+ if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
+ num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
+
+ if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
+ num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
+
+ lowdelay = 1;
+ } else {
+ lowdelay = 0;
+ }
+
+ hw_ps = &priv_tbl->rps[j];
+ memset(hw_ps, 0, sizeof(*hw_ps));
+
+ for (i = 0; i < num_l0_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
+
+ WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
+ REF_PIC_LONG_TERM_L0(i));
+ WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
+
+ if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ for (i = 0; i < num_l1_refs; i++) {
+ const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
+ int is_long_term =
+ !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
+
+ WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
+ WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
+
+ if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
+ lowdelay = 0;
+ }
+
+ WRITE_RPS(lowdelay, LOWDELAY);
+
+ if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
+ if (sl_params->short_term_ref_pic_set_size)
+ st_bit_offset = sl_params->short_term_ref_pic_set_size;
+ else if (sps->num_short_term_ref_pic_sets > 1)
+ st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
+ }
+
+ WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
+ LONG_TERM_RPS_BIT_OFFSET);
+ WRITE_RPS(sl_params->short_term_ref_pic_set_size,
+ SHORT_TERM_RPS_BIT_OFFSET);
+
+ WRITE_RPS(decode_params->num_poc_st_curr_before +
+ decode_params->num_poc_st_curr_after +
+ decode_params->num_poc_lt_curr,
+ NUM_RPS_POC);
+ }
+}
+
+/*
+ * Flip one or more matrices along their main diagonal and flatten them
+ * before writing it to the memory.
+ * Convert:
+ * ABCD AEIM
+ * EFGH => BFJN => AEIMBFJNCGKODHLP
+ * IJKL CGKO
+ * MNOP DHLP
+ */
+static void rotate_and_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length)
+{
+ int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
+
+ matrix_size = row_length * row_length;
+ for (i = 0; i < matrices; i++) {
+ row = 0;
+ x_offset = 0;
+ matrix_offset = i * matrix_size;
+ for (j = 0; j < matrix_size; j++) {
+ y_offset = j - (row * row_length);
+ rot_index = y_offset * row_length + x_offset;
+ new_value = *(input + i * matrix_size + j);
+ output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
+ if ((j + 1) % row_length == 0) {
+ row += 1;
+ x_offset += 1;
+ }
+ }
+ }
+}
+
+static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ int offset = 0;
+
+ rotate_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4);
+ offset = 6 * 16 * sizeof(u8);
+ rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8);
+ offset += 6 * 64 * sizeof(u8);
+ /* Add a 128 byte padding with 0s between the two 32x32 matrices */
+ rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+ offset += 128 * sizeof(u8);
+ rotate_and_flatten_matrices(output + offset,
+ (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)),
+ 1, 8);
+ offset += 64 * sizeof(u8);
+ memset(output + offset, 0, 128);
+}
+
+/*
+ * Required layout:
+ * A = scaling_list_dc_coef_16x16
+ * B = scaling_list_dc_coef_32x32
+ * 0 = Padding
+ *
+ * A, A, A, A, A, A, B, 0, 0, B, 0, 0
+ */
+static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ u8 list_32x32[6] = {0};
+
+ memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8));
+ list_32x32[0] = input->scaling_list_dc_coef_32x32[0];
+ list_32x32[3] = input->scaling_list_dc_coef_32x32[1];
+ memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8));
+}
+
+static void translate_scaling_list(struct scaling_factor *output,
+ const struct v4l2_ctrl_hevc_scaling_matrix *input)
+{
+ assemble_scalingfactor0(output->scalingfactor0, input);
+ memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96);
+ assemble_scalingdc(output->scalingdc, input);
+ memset(output->reserved, 0, 4 * sizeof(u8));
+}
+
+static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
+{
+ const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
+ u8 *dst;
+
+ if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
+ return;
+
+ dst = tbl->scaling_list;
+ translate_scaling_list((struct scaling_factor *)dst, scaling);
+
+ memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling,
+ sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
+}
+
+static struct vb2_buffer *
+get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, unsigned int dpb_idx)
+{
+ struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
+ struct vb2_buffer *buf = NULL;
+
+ if (dpb_idx < decode_params->num_active_dpb_entries)
+ buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
+
+ /*
+ * If a DPB entry is unused or invalid, the address of current destination
+ * buffer is returned.
+ */
+ if (!buf)
+ return &run->base.bufs.dst->vb2_buf;
+
+ return buf;
+}
+
+static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
+ const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
+ const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
+ const struct v4l2_pix_format_mplane *dst_fmt;
+ struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
+ struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
+ const struct v4l2_format *f;
+ dma_addr_t rlc_addr;
+ dma_addr_t refer_addr;
+ u32 rlc_len;
+ u32 hor_virstride;
+ u32 ver_virstride;
+ u32 y_virstride;
+ u32 uv_virstride;
+ u32 yuv_virstride;
+ u32 offset;
+ dma_addr_t dst_addr;
+ u32 reg, i;
+
+ reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
+
+ f = &ctx->decoded_fmt;
+ dst_fmt = &f->fmt.pix_mp;
+ hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
+ ver_virstride = dst_fmt->height;
+ y_virstride = hor_virstride * ver_virstride;
+ uv_virstride = y_virstride / 2;
+ yuv_virstride = y_virstride + uv_virstride;
+
+ reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
+ RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
+
+ /* config rlc base address */
+ rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
+ writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
+
+ rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
+ reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
+
+ /* config cabac table */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
+ writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
+
+ /* config output base address */
+ dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
+ writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
+
+ reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
+
+ reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
+
+ /* config ref pic address */
+ for (i = 0; i < 15; i++) {
+ struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
+
+ if (i < 4 && decode_params->num_active_dpb_entries) {
+ reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
+ reg = (reg >> (i * 4)) & 0xf;
+ } else {
+ reg = 0;
+ }
+
+ refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
+ writel_relaxed(refer_addr | reg, rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
+
+ reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
+ dpb[i].pic_order_cnt_val : 0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
+ }
+
+ reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
+
+ /* config hw pps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
+ writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_PPS_BASE);
+
+ /* config hw rps address */
+ offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
+ writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_RPS_BASE);
+
+ reg = RKVDEC_AXI_DDR_RDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
+
+ reg = RKVDEC_AXI_DDR_WDATA(0);
+ writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
+}
+
+static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f)
+{
+ struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
+
+ fmt->num_planes = 1;
+ if (!fmt->plane_fmt[0].sizeimage)
+ fmt->plane_fmt[0].sizeimage =
+ fmt->width * fmt->height * RKV_MAX_DEPTH_IN_BYTES;
+ return 0;
+}
+
+static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_priv_tbl *priv_tbl;
+ struct rkvdec_hevc_ctx *hevc_ctx;
+ int ret;
+
+ hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
+ if (!hevc_ctx)
+ return -ENOMEM;
+
+ priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
+ &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
+ if (!priv_tbl) {
+ ret = -ENOMEM;
+ goto err_free_ctx;
+ }
+
+ hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
+ hevc_ctx->priv_tbl.cpu = priv_tbl;
+ memset(priv_tbl, 0, sizeof(*priv_tbl));
+ memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, sizeof(rkvdec_hevc_cabac_table));
+
+ ctx->priv = hevc_ctx;
+ return 0;
+
+err_free_ctx:
+ kfree(hevc_ctx);
+ return ret;
+}
+
+static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
+ struct rkvdec_dev *rkvdec = ctx->dev;
+
+ dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
+ hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
+ kfree(hevc_ctx);
+}
+
+static int rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
+{
+ struct v4l2_ctrl *ctrl;
+
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
+ run->decode_params = ctrl ? ctrl->p_cur.p : NULL;
+ if (WARN_ON(!run->decode_params))
+ return -EINVAL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
+ run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
+ if (WARN_ON(!run->slices_params))
+ return -EINVAL;
+ run->num_slices = ctrl->new_elems;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SPS);
+ run->sps = ctrl ? ctrl->p_cur.p : NULL;
+ if (WARN_ON(!run->sps))
+ return -EINVAL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_PPS);
+ run->pps = ctrl ? ctrl->p_cur.p : NULL;
+ if (WARN_ON(!run->pps))
+ return -EINVAL;
+ ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
+ run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
+ if (WARN_ON(!run->scaling_matrix))
+ return -EINVAL;
+
+ rkvdec_run_preamble(ctx, &run->base);
+ return 0;
+}
+
+static void start_hardware(struct rkvdec_dev *rkvdec)
+{
+ void __iomem *register_base_addr = rkvdec->regs;
+ struct delayed_work *watchdog_worker = &rkvdec->watchdog_work;
+ /*
+ * RkVDEC error detection doesn't work really well and seems racy
+ * and unstable. Disable it.
+ */
+ writel_relaxed(0, register_base_addr + RKVDEC_REG_STRMD_ERR_EN);
+ writel_relaxed(0, register_base_addr + RKVDEC_REG_H264_ERR_E);
+
+ schedule_delayed_work(watchdog_worker, msecs_to_jiffies(2000));
+
+ writel(1, register_base_addr + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
+ writel(1, register_base_addr + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
+
+ /* Start decoding! */
+ writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
+ RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
+ register_base_addr + RKVDEC_REG_INTERRUPT);
+}
+
+static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx)
+{
+ const struct v4l2_ctrl_hevc_sps *sps = ctx->sps;
+
+ /*
+ * No need to check chroma_format_idc, currently only 4:2:0 formats
+ * supported.
+ */
+ if (sps && sps->bit_depth_luma_minus8 == 2)
+ return V4L2_PIX_FMT_NV15;
+ else
+ return V4L2_PIX_FMT_NV12;
+}
+
+/*
+ * Convert some fields from the SPS structure into human readable attributes.
+ */
+static int rkvdec_hevc_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
+ struct sps_attributes *attributes)
+{
+ struct v4l2_ctrl_hevc_sps *hevc_sps = sps;
+ unsigned int width = hevc_sps->pic_width_in_luma_samples;
+ unsigned int height = hevc_sps->pic_height_in_luma_samples;
+
+ if (!(width % 64 == 0))
+ width = ALIGN(width, 64);
+
+ if (!(height % 16 == 0))
+ height = ALIGN(height, 16);
+
+ attributes->width = width;
+ attributes->height = height;
+ attributes->luma_bitdepth = hevc_sps->bit_depth_luma_minus8 + 8;
+ attributes->chroma_bitdepth = hevc_sps->bit_depth_chroma_minus8 + 8;
+ switch (hevc_sps->chroma_format_idc) {
+ case 0:
+ attributes->subsampling = 400;
+ break;
+ case 1:
+ attributes->subsampling = 420;
+ break;
+ case 2:
+ attributes->subsampling = 422;
+ break;
+ case 3:
+ attributes->subsampling = 444;
+ break;
+ };
+
+ return 0;
+}
+
+static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, void *sps,
+ struct v4l2_pix_format_mplane *pix_mp)
+{
+ struct sps_attributes attributes = {0};
+
+ rkvdec_hevc_get_sps_attributes(ctx, sps, &attributes);
+
+ if ((attributes.width != pix_mp->width) || (attributes.height != pix_mp->height)) {
+ dev_err(ctx->dev->dev,
+ "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.",
+ attributes.width, attributes.height, pix_mp->width, pix_mp->height);
+ return -EINVAL;
+ }
+
+ if ((attributes.luma_bitdepth == 8 && pix_mp->pixelformat != V4L2_PIX_FMT_NV12) ||
+ (attributes.luma_bitdepth == 10 && pix_mp->pixelformat != V4L2_PIX_FMT_NV15)) {
+ dev_err(ctx->dev->dev,
+ "Incompatible SPS bit-depth, SPS %d, Pixel format %d.",
+ attributes.luma_bitdepth,
+ pix_mp->pixelformat == V4L2_PIX_FMT_NV12 ? 8 : 10);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ struct sps_attributes attributes = {0};
+
+ rkvdec_hevc_get_sps_attributes(ctx, ctrl->p_new.p_hevc_sps, &attributes);
+
+ if (attributes.subsampling > 420)
+ return -EINVAL;
+ if (attributes.luma_bitdepth != 8 && attributes.luma_bitdepth != 10)
+ return -EINVAL;
+ return 0;
+}
+
+static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
+{
+ struct rkvdec_dev *rkvdec = ctx->dev;
+ struct rkvdec_hevc_run run;
+ int ret;
+
+ ret = rkvdec_hevc_run_preamble(ctx, &run);
+ if (ret) {
+ dev_err(ctx->dev->dev, "Missing required controls for the RkVDEC HEVC decoder.");
+ return ret;
+ }
+
+ assemble_hw_scaling_list(ctx, &run);
+ assemble_hw_pps(ctx, &run);
+ assemble_hw_rps(ctx, &run);
+ config_registers(ctx, &run);
+ rkvdec_run_postamble(ctx, &run.base);
+ start_hardware(rkvdec);
+
+ return 0;
+}
+
+const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
+ .adjust_fmt = rkvdec_hevc_adjust_fmt,
+ .start = rkvdec_hevc_start,
+ .stop = rkvdec_hevc_stop,
+ .run = rkvdec_hevc_run,
+ .try_ctrl = rkvdec_hevc_try_ctrl,
+ .valid_fmt = rkvdec_hevc_valid_fmt,
+ .sps_check = rkvdec_hevc_validate_sps,
+ .get_sps_attributes = rkvdec_hevc_get_sps_attributes,
+};
diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
index 15b9bee92016..83bf790ed9b7 100644
--- a/drivers/staging/media/rkvdec/rkvdec-regs.h
+++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
@@ -43,6 +43,7 @@
#define RKVDEC_RLC_MODE BIT(11)
#define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
#define RKVDEC_MODE(x) (((x) & 0x03) << 20)
+#define RKVDEC_MODE_HEVC 0
#define RKVDEC_MODE_H264 1
#define RKVDEC_MODE_VP9 2
#define RKVDEC_RPS_MODE BIT(24)
diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index 3d413c5ad1d2..6462dd83ea6d 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -13,6 +13,7 @@
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
@@ -230,6 +231,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
},
};

+static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
+ .cfg.name = "Slice parameters",
+ .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
+ .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
+ .cfg.dims = { 600 },
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
+ .cfg.ops = &rkvdec_ctrl_ops,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
+ .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
+ },
+ {
+ .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
+ .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
+ .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
+ },
+ {
+ .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
+ .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
+ .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
+ },
+};
+
+static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
+ .ctrls = rkvdec_hevc_ctrl_descs,
+ .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
+};
+
+static const u32 rkvdec_hevc_decoded_fmts[] = {
+ V4L2_PIX_FMT_NV12,
+ V4L2_PIX_FMT_NV15,
+};
+
static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
.ctrls = rkvdec_h264_ctrl_descs,
.num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
@@ -260,6 +317,21 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
};

static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
+ {
+ .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
+ .frmsize = {
+ .min_width = 64,
+ .max_width = 4096,
+ .step_width = 64,
+ .min_height = 64,
+ .max_height = 2304,
+ .step_height = 16,
+ },
+ .ctrls = &rkvdec_hevc_ctrls,
+ .ops = &rkvdec_hevc_fmt_ops,
+ .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
+ .decoded_fmts = rkvdec_hevc_decoded_fmts,
+ },
{
.fourcc = V4L2_PIX_FMT_H264_SLICE,
.frmsize = {
diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index d74821f9fd0b..9cf354968d52 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -135,6 +135,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);

extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
+extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;

#endif /* RKVDEC_H_ */

--
2.25.1

2023-01-12 13:28:48

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 09/12] staging: media: rkvdec: h264: Add callbacks for h264

Implement the valid format and sps validation callbacks for H264.
H264 already has a SPS validation function, adjust it to fit the
function the declaration and add error messages.
Additionally, add a function to fetch attributes from the SPS in a human
readable format to make the code more self documenting.

Signed-off-by: Sebastian Fricke <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec-h264.c | 105 ++++++++++++++++++++++-------
1 file changed, 80 insertions(+), 25 deletions(-)

diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
index 4fc167b42cf0..17b215874ddd 100644
--- a/drivers/staging/media/rkvdec/rkvdec-h264.c
+++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
@@ -1026,40 +1026,80 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
return 0;
}

-static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
- const struct v4l2_ctrl_h264_sps *sps)
+/*
+ * Convert some fields from the SPS structure into human readable attributes.
+ */
+static int rkvdec_h264_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
+ struct sps_attributes *attributes)
+{
+ struct v4l2_ctrl_h264_sps *h264_sps = sps;
+ unsigned int width = (h264_sps->pic_width_in_mbs_minus1 + 1) * 16;
+ unsigned int height = (h264_sps->pic_height_in_map_units_minus1 + 1) * 16;
+ /*
+ * When frame_mbs_only_flag is not set, this is field height,
+ * which is half the final height (see (7-18) in the
+ * specification)
+ */
+ if (!(h264_sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
+ height *= 2;
+
+ attributes->width = width;
+ attributes->height = height;
+ attributes->luma_bitdepth = h264_sps->bit_depth_luma_minus8 + 8;
+ attributes->chroma_bitdepth = h264_sps->bit_depth_chroma_minus8 + 8;
+ switch (h264_sps->chroma_format_idc) {
+ case 0:
+ attributes->subsampling = 400;
+ break;
+ case 1:
+ attributes->subsampling = 420;
+ break;
+ case 2:
+ attributes->subsampling = 422;
+ break;
+ case 3:
+ attributes->subsampling = 444;
+ break;
+ };
+ return 0;
+}
+
+static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, void *sps,
+ struct v4l2_pix_format_mplane *pix_mp)
{
- unsigned int width, height;
+ struct sps_attributes attributes = {0};
+
+ rkvdec_h264_get_sps_attributes(ctx, sps, &attributes);

/*
* TODO: The hardware supports 10-bit and 4:2:2 profiles,
* but it's currently broken in the driver.
* Reject them for now, until it's fixed.
*/
- if (sps->chroma_format_idc > 1)
- /* Only 4:0:0 and 4:2:0 are supported */
+ if (attributes.subsampling > 420) {
+ dev_err(ctx->dev->dev,
+ "Only 4:0:0 and 4:2:0 subsampling schemes are supported, got: %d\n",
+ attributes.subsampling);
return -EINVAL;
- if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
- /* Luma and chroma bit depth mismatch */
+ }
+ if (attributes.luma_bitdepth != attributes.chroma_bitdepth) {
+ dev_err(ctx->dev->dev,
+ "Luma and chroma bit depth mismatch, luma %d, chroma %d\n",
+ attributes.luma_bitdepth, attributes.chroma_bitdepth);
return -EINVAL;
- if (sps->bit_depth_luma_minus8 != 0)
- /* Only 8-bit is supported */
+ }
+ if (attributes.luma_bitdepth != 8) {
+ dev_err(ctx->dev->dev, "Only 8-bit H264 formats supported, SPS %d\n",
+ attributes.luma_bitdepth);
return -EINVAL;
+ }

- width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
- height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
-
- /*
- * When frame_mbs_only_flag is not set, this is field height,
- * which is half the final height (see (7-18) in the
- * specification)
- */
- if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
- height *= 2;
-
- if (width > ctx->coded_fmt.fmt.pix_mp.width ||
- height > ctx->coded_fmt.fmt.pix_mp.height)
+ if (attributes.width > pix_mp->width || attributes.height > pix_mp->height) {
+ dev_err(ctx->dev->dev,
+ "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.",
+ attributes.width, attributes.height, pix_mp->width, pix_mp->height);
return -EINVAL;
+ }

return 0;
}
@@ -1077,8 +1117,9 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
if (!ctrl)
return -EINVAL;

- ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
- if (ret)
+ ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
+ &ctx->coded_fmt.fmt.pix_mp);
+ if (ret < 0)
return ret;

h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL);
@@ -1175,10 +1216,21 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
return 0;
}

+static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx)
+{
+ /*
+ * Only 8 bit 4:0:0 and 4:2:0 formats supported for now.
+ * The SPS is validated at a different function thus we can assume that
+ * it is correct.
+ */
+ return V4L2_PIX_FMT_NV12;
+}
+
static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
{
if (ctrl->id == V4L2_CID_STATELESS_H264_SPS)
- return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
+ return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
+ &ctx->coded_fmt.fmt.pix_mp);

return 0;
}
@@ -1189,4 +1241,7 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
.stop = rkvdec_h264_stop,
.run = rkvdec_h264_run,
.try_ctrl = rkvdec_h264_try_ctrl,
+ .valid_fmt = rkvdec_h264_valid_fmt,
+ .sps_check = rkvdec_h264_validate_sps,
+ .get_sps_attributes = rkvdec_h264_get_sps_attributes,
};

--
2.25.1

2023-01-12 14:03:31

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 11/12] staging: media: rkvdec: Enable S_CTRL IOCTL

Enable user-space to set the SPS of the current byte-stream on the
decoder. This action will enable the decoder to pick the optimal
pixel-format for the capture queue, whenever it is required.

Signed-off-by: Sebastian Fricke <[email protected]>
Signed-off-by: Jonas Karlman <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec.c | 81 +++++++++++++++++++++++++++++++++++
1 file changed, 81 insertions(+)

diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index b303c6e0286d..3d413c5ad1d2 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -93,6 +93,79 @@ static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
return 0;
}

+static int rkvdec_set_sps(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
+{
+ struct v4l2_pix_format_mplane *pix_mp;
+ struct sps_attributes attributes = {0};
+ void *new_sps = NULL;
+
+ /*
+ * SPS structures are not filled until the control handler is set up
+ */
+ if (!ctx->fh.ctrl_handler)
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_STATELESS_H264_SPS:
+ new_sps = (void *)ctrl->p_new.p_h264_sps;
+ break;
+ case V4L2_CID_STATELESS_HEVC_SPS:
+ new_sps = (void *)ctrl->p_new.p_hevc_sps;
+ break;
+ default:
+ dev_err(ctx->dev->dev, "Unsupported stateless control ID: %x\n", ctrl->id);
+ return -EINVAL;
+ };
+ rkvdec_get_sps_attributes(ctx, new_sps, &attributes);
+
+ /*
+ * Providing an empty SPS is valid but we do not store it.
+ */
+ if (attributes.width == 0 && attributes.height == 0)
+ return 0;
+
+ pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
+
+ /*
+ * SPS must match the provided format dimension, if it doesn't userspace has to
+ * first reset the output format
+ */
+ if ((attributes.width > pix_mp->width) || (attributes.height > pix_mp->height)) {
+ dev_err(ctx->dev->dev,
+ "Dimension mismatch. [%s SPS] W: %d, H: %d, [Format] W: %d, H: %d)\n",
+ ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ? "HEVC" : "H264",
+ attributes.width, attributes.height, pix_mp->width, pix_mp->height);
+ return -EINVAL;
+ }
+
+ if (ctx->sps && pix_mp->pixelformat == rkvdec_get_valid_fmt(ctx)) {
+ /*
+ * Userspace is allowed to change the SPS at any point, if the
+ * pixel format doesn't differ from the format in the context,
+ * just accept the change even if buffers are queued
+ */
+ ctx->sps = new_sps;
+ } else {
+ /*
+ * Do not accept changing the SPS, while buffers are queued,
+ * when the new SPS would cause switching the CAPTURE pixel format
+ */
+ if (pix_mp->pixelformat != rkvdec_get_valid_fmt(ctx)) {
+ if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
+ return -EBUSY;
+ }
+ ctx->sps = new_sps;
+ /*
+ * For the initial SPS setting and when the pixel format is
+ * changed adjust the pixel format stored in the context
+ */
+ pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx);
+ rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
+ }
+
+ return 0;
+}
+
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
@@ -104,8 +177,16 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
return 0;
}

+static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
+
+ return rkvdec_set_sps(ctx, ctrl);
+}
+
static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
.try_ctrl = rkvdec_try_ctrl,
+ .s_ctrl = rkvdec_s_ctrl,
};

static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {

--
2.25.1

2023-01-12 14:04:59

by Sebastian Fricke

[permalink] [raw]
Subject: [PATCH v2 06/12] staging: media: rkvdec: Add a valid pixel format check as callback

Provide a callback for codec variant drivers to indicate the correct
output pixel-format. It will either utilize the SPS structure stored via
the S_CTRL IOCTL or return the default pixel-format.

Signed-off-by: Jonas Karlman <[email protected]>
Signed-off-by: Sebastian Fricke <[email protected]>
---
drivers/staging/media/rkvdec/rkvdec.c | 45 +++++++++++++++++++++++++++++------
drivers/staging/media/rkvdec/rkvdec.h | 1 +
2 files changed, 39 insertions(+), 7 deletions(-)

diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
index e0e95d06e216..a46f918926a2 100644
--- a/drivers/staging/media/rkvdec/rkvdec.c
+++ b/drivers/staging/media/rkvdec/rkvdec.c
@@ -38,6 +38,20 @@ static int rkvdec_queue_busy(struct rkvdec_ctx *ctx, enum v4l2_buf_type buf_type
return 0;
}

+/*
+ * Use the current SPS, set by the user via the VIDIOC_S_CTRL IOCTL,
+ * to determine the optimal pixel-format. Each codec is responsible
+ * for choosing the appropriate pixel-format for a given parameter set.
+ */
+static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx)
+{
+ const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
+
+ if (coded_desc->ops->valid_fmt)
+ return coded_desc->ops->valid_fmt(ctx);
+ return ctx->coded_fmt_desc->decoded_fmts[0];
+}
+
static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
{
struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
@@ -200,8 +214,9 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
{
struct v4l2_format *f = &ctx->decoded_fmt;
+ u32 valid_fmt = rkvdec_get_valid_fmt(ctx);

- rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
+ rkvdec_reset_fmt(ctx, f, valid_fmt);
f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
ctx->coded_fmt_desc->decoded_fmts[0],
@@ -260,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
if (WARN_ON(!coded_desc))
return -EINVAL;

- for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
- if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
- break;
- }
+ if (ctx->sps) {
+ pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx);
+ } else {
+ for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
+ if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
+ break;
+ }

- if (i == coded_desc->num_decoded_fmts)
- pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+ if (i == coded_desc->num_decoded_fmts)
+ pix_mp->pixelformat = coded_desc->decoded_fmts[0];
+ }

/* Always apply the frmsize constraint of the coded end. */
pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
@@ -435,6 +454,18 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
if (WARN_ON(!ctx->coded_fmt_desc))
return -EINVAL;

+ /*
+ * According to the specification the driver can only return formats
+ * that are supported by both the current encoded format and the
+ * provided controls
+ */
+ if (ctx->sps) {
+ if (f->index)
+ return -EINVAL;
+ f->pixelformat = rkvdec_get_valid_fmt(ctx);
+ return 0;
+ }
+
if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
return -EINVAL;

diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
index 332126e7b812..e353a4403e5b 100644
--- a/drivers/staging/media/rkvdec/rkvdec.h
+++ b/drivers/staging/media/rkvdec/rkvdec.h
@@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
struct rkvdec_coded_fmt_ops {
int (*adjust_fmt)(struct rkvdec_ctx *ctx,
struct v4l2_format *f);
+ u32 (*valid_fmt)(struct rkvdec_ctx *ctx);
int (*start)(struct rkvdec_ctx *ctx);
void (*stop)(struct rkvdec_ctx *ctx);
int (*run)(struct rkvdec_ctx *ctx);

--
2.25.1

2023-01-12 15:43:26

by Ezequiel Garcia

[permalink] [raw]
Subject: Re: [PATCH v2 06/12] staging: media: rkvdec: Add a valid pixel format check as callback

Hi Sebastian,

On Thu, Jan 12, 2023 at 9:56 AM Sebastian Fricke
<[email protected]> wrote:
>
> Provide a callback for codec variant drivers to indicate the correct
> output pixel-format. It will either utilize the SPS structure stored via
> the S_CTRL IOCTL or return the default pixel-format.
>
> Signed-off-by: Jonas Karlman <[email protected]>
> Signed-off-by: Sebastian Fricke <[email protected]>
> ---
> drivers/staging/media/rkvdec/rkvdec.c | 45 +++++++++++++++++++++++++++++------
> drivers/staging/media/rkvdec/rkvdec.h | 1 +
> 2 files changed, 39 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
> index e0e95d06e216..a46f918926a2 100644
> --- a/drivers/staging/media/rkvdec/rkvdec.c
> +++ b/drivers/staging/media/rkvdec/rkvdec.c
> @@ -38,6 +38,20 @@ static int rkvdec_queue_busy(struct rkvdec_ctx *ctx, enum v4l2_buf_type buf_type
> return 0;
> }
>
> +/*
> + * Use the current SPS, set by the user via the VIDIOC_S_CTRL IOCTL,
> + * to determine the optimal pixel-format. Each codec is responsible
> + * for choosing the appropriate pixel-format for a given parameter set.
> + */

It seems this assumes there's always only one valid format.
Do you think that will hold true always for RKVDEC and for all codecs?

How about we approach this differently? Instead of having a callback
for codecs to implement, we just maintain a list of valid decoded formats
(in the context) and re-create the list when the SPS is changed (in the S_CTRL).

Possibly simpler and less invasive, not sure if there are any caveats.

Thanks,
Ezequiel

> +static int rkvdec_get_valid_fmt(struct rkvdec_ctx *ctx)
> +{
> + const struct rkvdec_coded_fmt_desc *coded_desc = ctx->coded_fmt_desc;
> +
> + if (coded_desc->ops->valid_fmt)
> + return coded_desc->ops->valid_fmt(ctx);
> + return ctx->coded_fmt_desc->decoded_fmts[0];
> +}
> +
> static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
> {
> struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
> @@ -200,8 +214,9 @@ static void rkvdec_reset_coded_fmt(struct rkvdec_ctx *ctx)
> static void rkvdec_reset_decoded_fmt(struct rkvdec_ctx *ctx)
> {
> struct v4l2_format *f = &ctx->decoded_fmt;
> + u32 valid_fmt = rkvdec_get_valid_fmt(ctx);
>
> - rkvdec_reset_fmt(ctx, f, ctx->coded_fmt_desc->decoded_fmts[0]);
> + rkvdec_reset_fmt(ctx, f, valid_fmt);
> f->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
> v4l2_fill_pixfmt_mp(&f->fmt.pix_mp,
> ctx->coded_fmt_desc->decoded_fmts[0],
> @@ -260,13 +275,17 @@ static int rkvdec_try_capture_fmt(struct file *file, void *priv,
> if (WARN_ON(!coded_desc))
> return -EINVAL;
>
> - for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
> - if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
> - break;
> - }
> + if (ctx->sps) {
> + pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx);
> + } else {
> + for (i = 0; i < coded_desc->num_decoded_fmts; i++) {
> + if (coded_desc->decoded_fmts[i] == pix_mp->pixelformat)
> + break;
> + }
>
> - if (i == coded_desc->num_decoded_fmts)
> - pix_mp->pixelformat = coded_desc->decoded_fmts[0];
> + if (i == coded_desc->num_decoded_fmts)
> + pix_mp->pixelformat = coded_desc->decoded_fmts[0];
> + }
>
> /* Always apply the frmsize constraint of the coded end. */
> pix_mp->width = max(pix_mp->width, ctx->coded_fmt.fmt.pix_mp.width);
> @@ -435,6 +454,18 @@ static int rkvdec_enum_capture_fmt(struct file *file, void *priv,
> if (WARN_ON(!ctx->coded_fmt_desc))
> return -EINVAL;
>
> + /*
> + * According to the specification the driver can only return formats
> + * that are supported by both the current encoded format and the
> + * provided controls
> + */
> + if (ctx->sps) {
> + if (f->index)
> + return -EINVAL;
> + f->pixelformat = rkvdec_get_valid_fmt(ctx);
> + return 0;
> + }
> +
> if (f->index >= ctx->coded_fmt_desc->num_decoded_fmts)
> return -EINVAL;
>
> diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
> index 332126e7b812..e353a4403e5b 100644
> --- a/drivers/staging/media/rkvdec/rkvdec.h
> +++ b/drivers/staging/media/rkvdec/rkvdec.h
> @@ -66,6 +66,7 @@ vb2_to_rkvdec_decoded_buf(struct vb2_buffer *buf)
> struct rkvdec_coded_fmt_ops {
> int (*adjust_fmt)(struct rkvdec_ctx *ctx,
> struct v4l2_format *f);
> + u32 (*valid_fmt)(struct rkvdec_ctx *ctx);
> int (*start)(struct rkvdec_ctx *ctx);
> void (*stop)(struct rkvdec_ctx *ctx);
> int (*run)(struct rkvdec_ctx *ctx);
>
> --
> 2.25.1

2023-01-12 16:14:34

by Ezequiel Garcia

[permalink] [raw]
Subject: Re: [PATCH v2 11/12] staging: media: rkvdec: Enable S_CTRL IOCTL

Hi Sebastian,

On Thu, Jan 12, 2023 at 9:57 AM Sebastian Fricke
<[email protected]> wrote:
>
> Enable user-space to set the SPS of the current byte-stream on the
> decoder. This action will enable the decoder to pick the optimal
> pixel-format for the capture queue, whenever it is required.
>
> Signed-off-by: Sebastian Fricke <[email protected]>
> Signed-off-by: Jonas Karlman <[email protected]>
> ---
> drivers/staging/media/rkvdec/rkvdec.c | 81 +++++++++++++++++++++++++++++++++++
> 1 file changed, 81 insertions(+)
>
> diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
> index b303c6e0286d..3d413c5ad1d2 100644
> --- a/drivers/staging/media/rkvdec/rkvdec.c
> +++ b/drivers/staging/media/rkvdec/rkvdec.c
> @@ -93,6 +93,79 @@ static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
> return 0;
> }
>
> +static int rkvdec_set_sps(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
> +{
> + struct v4l2_pix_format_mplane *pix_mp;
> + struct sps_attributes attributes = {0};
> + void *new_sps = NULL;
> +
> + /*
> + * SPS structures are not filled until the control handler is set up
> + */
> + if (!ctx->fh.ctrl_handler)
> + return 0;

The control handler is embedded in the context, and the fh.ctrl_handler
is initialized when the context is returned.

You cannot have a context without a control handler (see hantro_open).

> +
> + switch (ctrl->id) {
> + case V4L2_CID_STATELESS_H264_SPS:
> + new_sps = (void *)ctrl->p_new.p_h264_sps;
> + break;
> + case V4L2_CID_STATELESS_HEVC_SPS:
> + new_sps = (void *)ctrl->p_new.p_hevc_sps;
> + break;
> + default:
> + dev_err(ctx->dev->dev, "Unsupported stateless control ID: %x\n", ctrl->id);
> + return -EINVAL;
> + };
> + rkvdec_get_sps_attributes(ctx, new_sps, &attributes);
> +
> + /*
> + * Providing an empty SPS is valid but we do not store it.
> + */
> + if (attributes.width == 0 && attributes.height == 0)
> + return 0;
> +
> + pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
> +
> + /*
> + * SPS must match the provided format dimension, if it doesn't userspace has to
> + * first reset the output format

This comment says it's a mismatch check, but the check is checking for
"larger than".

Other than that, the general idea looks good, can you rework the series to avoid
the extra storage of the SPS control in the context?

Thanks,
Ezequiel

> + */
> + if ((attributes.width > pix_mp->width) || (attributes.height > pix_mp->height)) {
> + dev_err(ctx->dev->dev,
> + "Dimension mismatch. [%s SPS] W: %d, H: %d, [Format] W: %d, H: %d)\n",
> + ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ? "HEVC" : "H264",
> + attributes.width, attributes.height, pix_mp->width, pix_mp->height);
> + return -EINVAL;
> + }
> +
> + if (ctx->sps && pix_mp->pixelformat == rkvdec_get_valid_fmt(ctx)) {
> + /*
> + * Userspace is allowed to change the SPS at any point, if the
> + * pixel format doesn't differ from the format in the context,
> + * just accept the change even if buffers are queued
> + */
> + ctx->sps = new_sps;
> + } else {
> + /*
> + * Do not accept changing the SPS, while buffers are queued,
> + * when the new SPS would cause switching the CAPTURE pixel format
> + */
> + if (pix_mp->pixelformat != rkvdec_get_valid_fmt(ctx)) {
> + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
> + return -EBUSY;
> + }
> + ctx->sps = new_sps;
> + /*
> + * For the initial SPS setting and when the pixel format is
> + * changed adjust the pixel format stored in the context
> + */
> + pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx);
> + rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
> + }
> +
> + return 0;
> +}
> +
> static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
> {
> struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
> @@ -104,8 +177,16 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
> return 0;
> }
>
> +static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
> +{
> + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
> +
> + return rkvdec_set_sps(ctx, ctrl);
> +}
> +
> static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
> .try_ctrl = rkvdec_try_ctrl,
> + .s_ctrl = rkvdec_s_ctrl,
> };
>
> static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
>
> --
> 2.25.1

2023-01-12 16:29:51

by Ezequiel Garcia

[permalink] [raw]
Subject: Re: [PATCH v2 09/12] staging: media: rkvdec: h264: Add callbacks for h264

On Thu, Jan 12, 2023 at 9:56 AM Sebastian Fricke
<[email protected]> wrote:
>
> Implement the valid format and sps validation callbacks for H264.
> H264 already has a SPS validation function, adjust it to fit the
> function the declaration and add error messages.
> Additionally, add a function to fetch attributes from the SPS in a human
> readable format to make the code more self documenting.
>
> Signed-off-by: Sebastian Fricke <[email protected]>
> ---
> drivers/staging/media/rkvdec/rkvdec-h264.c | 105 ++++++++++++++++++++++-------
> 1 file changed, 80 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
> index 4fc167b42cf0..17b215874ddd 100644
> --- a/drivers/staging/media/rkvdec/rkvdec-h264.c
> +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
> @@ -1026,40 +1026,80 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
> return 0;
> }
>
> -static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
> - const struct v4l2_ctrl_h264_sps *sps)
> +/*
> + * Convert some fields from the SPS structure into human readable attributes.
> + */
> +static int rkvdec_h264_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
> + struct sps_attributes *attributes)
> +{
> + struct v4l2_ctrl_h264_sps *h264_sps = sps;
> + unsigned int width = (h264_sps->pic_width_in_mbs_minus1 + 1) * 16;
> + unsigned int height = (h264_sps->pic_height_in_map_units_minus1 + 1) * 16;
> + /*
> + * When frame_mbs_only_flag is not set, this is field height,
> + * which is half the final height (see (7-18) in the
> + * specification)
> + */
> + if (!(h264_sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
> + height *= 2;
> +
> + attributes->width = width;
> + attributes->height = height;
> + attributes->luma_bitdepth = h264_sps->bit_depth_luma_minus8 + 8;
> + attributes->chroma_bitdepth = h264_sps->bit_depth_chroma_minus8 + 8;
> + switch (h264_sps->chroma_format_idc) {
> + case 0:
> + attributes->subsampling = 400;
> + break;
> + case 1:
> + attributes->subsampling = 420;
> + break;
> + case 2:
> + attributes->subsampling = 422;
> + break;
> + case 3:
> + attributes->subsampling = 444;
> + break;
> + };
> + return 0;
> +}
> +
> +static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, void *sps,
> + struct v4l2_pix_format_mplane *pix_mp)
> {
> - unsigned int width, height;
> + struct sps_attributes attributes = {0};
> +
> + rkvdec_h264_get_sps_attributes(ctx, sps, &attributes);
>
> /*
> * TODO: The hardware supports 10-bit and 4:2:2 profiles,
> * but it's currently broken in the driver.
> * Reject them for now, until it's fixed.
> */
> - if (sps->chroma_format_idc > 1)
> - /* Only 4:0:0 and 4:2:0 are supported */
> + if (attributes.subsampling > 420) {
> + dev_err(ctx->dev->dev,
> + "Only 4:0:0 and 4:2:0 subsampling schemes are supported, got: %d\n",
> + attributes.subsampling);
> return -EINVAL;
> - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
> - /* Luma and chroma bit depth mismatch */
> + }
> + if (attributes.luma_bitdepth != attributes.chroma_bitdepth) {
> + dev_err(ctx->dev->dev,
> + "Luma and chroma bit depth mismatch, luma %d, chroma %d\n",
> + attributes.luma_bitdepth, attributes.chroma_bitdepth);
> return -EINVAL;
> - if (sps->bit_depth_luma_minus8 != 0)
> - /* Only 8-bit is supported */
> + }
> + if (attributes.luma_bitdepth != 8) {
> + dev_err(ctx->dev->dev, "Only 8-bit H264 formats supported, SPS %d\n",
> + attributes.luma_bitdepth);
> return -EINVAL;
> + }
>
> - width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
> - height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
> -
> - /*
> - * When frame_mbs_only_flag is not set, this is field height,
> - * which is half the final height (see (7-18) in the
> - * specification)
> - */
> - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
> - height *= 2;
> -
> - if (width > ctx->coded_fmt.fmt.pix_mp.width ||
> - height > ctx->coded_fmt.fmt.pix_mp.height)
> + if (attributes.width > pix_mp->width || attributes.height > pix_mp->height) {
> + dev_err(ctx->dev->dev,
> + "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.",
> + attributes.width, attributes.height, pix_mp->width, pix_mp->height);
> return -EINVAL;
> + }
>
> return 0;
> }
> @@ -1077,8 +1117,9 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
> if (!ctrl)
> return -EINVAL;
>
> - ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
> - if (ret)
> + ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
> + &ctx->coded_fmt.fmt.pix_mp);

Not a problem with this patch, but I wonder why we accepted a validation
in the start_streaming step.

At this point, the driver accepted all the format negotiations in try_fmt.
It's difficult for applications to recover from this, as there would
be no way to tell what failed,
we would be returning EINVAL, which as per the spec is "buffer type is
not supported,
or no buffers have been allocated (memory mapping) or enqueued (output) yet.".

I think it would really make a lot of sense to fix this now, instead of continue
abusing it. And also, I'd like to prevent a possible anti-pattern from
spreading.

Thanks!
Ezequiel

> + if (ret < 0)
> return ret;
>
> h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL);
> @@ -1175,10 +1216,21 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
> return 0;
> }
>
> +static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx)
> +{
> + /*
> + * Only 8 bit 4:0:0 and 4:2:0 formats supported for now.
> + * The SPS is validated at a different function thus we can assume that
> + * it is correct.
> + */
> + return V4L2_PIX_FMT_NV12;
> +}
> +
> static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
> {
> if (ctrl->id == V4L2_CID_STATELESS_H264_SPS)
> - return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
> + return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
> + &ctx->coded_fmt.fmt.pix_mp);
>
> return 0;
> }
> @@ -1189,4 +1241,7 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
> .stop = rkvdec_h264_stop,
> .run = rkvdec_h264_run,
> .try_ctrl = rkvdec_h264_try_ctrl,
> + .valid_fmt = rkvdec_h264_valid_fmt,
> + .sps_check = rkvdec_h264_validate_sps,
> + .get_sps_attributes = rkvdec_h264_get_sps_attributes,
> };
>
> --
> 2.25.1

2023-01-12 19:26:37

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH v2 12/12] staging: media: rkvdec: Add HEVC backend

Hi Sebastian,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on 6599e683db1bf22fee74302c47e31b9a42a1c3d2]

url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Fricke/media-v4l2-Add-NV15-pixel-format/20230112-205935
base: 6599e683db1bf22fee74302c47e31b9a42a1c3d2
patch link: https://lore.kernel.org/r/20230101-patch-series-v2-6-2-rc1-v2-12-fa1897efac14%40collabora.com
patch subject: [PATCH v2 12/12] staging: media: rkvdec: Add HEVC backend
config: m68k-allmodconfig
compiler: m68k-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/b09b88f41bd2c6bf802598f997e4fc2d5048456a
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sebastian-Fricke/media-v4l2-Add-NV15-pixel-format/20230112-205935
git checkout b09b88f41bd2c6bf802598f997e4fc2d5048456a
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=m68k SHELL=/bin/bash drivers/staging/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>

All warnings (new ones prefixed by >>):

drivers/staging/media/rkvdec/rkvdec-hevc.c: In function 'rotate_and_flatten_matrices':
>> drivers/staging/media/rkvdec/rkvdec-hevc.c:476:83: warning: variable 'new_value' set but not used [-Wunused-but-set-variable]
476 | int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
| ^~~~~~~~~


vim +/new_value +476 drivers/staging/media/rkvdec/rkvdec-hevc.c

464
465 /*
466 * Flip one or more matrices along their main diagonal and flatten them
467 * before writing it to the memory.
468 * Convert:
469 * ABCD AEIM
470 * EFGH => BFJN => AEIMBFJNCGKODHLP
471 * IJKL CGKO
472 * MNOP DHLP
473 */
474 static void rotate_and_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length)
475 {
> 476 int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
477
478 matrix_size = row_length * row_length;
479 for (i = 0; i < matrices; i++) {
480 row = 0;
481 x_offset = 0;
482 matrix_offset = i * matrix_size;
483 for (j = 0; j < matrix_size; j++) {
484 y_offset = j - (row * row_length);
485 rot_index = y_offset * row_length + x_offset;
486 new_value = *(input + i * matrix_size + j);
487 output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
488 if ((j + 1) % row_length == 0) {
489 row += 1;
490 x_offset += 1;
491 }
492 }
493 }
494 }
495

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests


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2023-01-12 22:25:05

by Nicolas Dufresne

[permalink] [raw]
Subject: Re: [PATCH v2 11/12] staging: media: rkvdec: Enable S_CTRL IOCTL

Le jeudi 12 janvier 2023 à 12:09 -0300, Ezequiel Garcia a écrit :
> Hi Sebastian,
>
> On Thu, Jan 12, 2023 at 9:57 AM Sebastian Fricke
> <[email protected]> wrote:
> >
> > Enable user-space to set the SPS of the current byte-stream on the
> > decoder. This action will enable the decoder to pick the optimal
> > pixel-format for the capture queue, whenever it is required.
> >
> > Signed-off-by: Sebastian Fricke <[email protected]>
> > Signed-off-by: Jonas Karlman <[email protected]>
> > ---
> > drivers/staging/media/rkvdec/rkvdec.c | 81 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 81 insertions(+)
> >
> > diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
> > index b303c6e0286d..3d413c5ad1d2 100644
> > --- a/drivers/staging/media/rkvdec/rkvdec.c
> > +++ b/drivers/staging/media/rkvdec/rkvdec.c
> > @@ -93,6 +93,79 @@ static int rkvdec_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
> > return 0;
> > }
> >
> > +static int rkvdec_set_sps(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
> > +{
> > + struct v4l2_pix_format_mplane *pix_mp;
> > + struct sps_attributes attributes = {0};
> > + void *new_sps = NULL;
> > +
> > + /*
> > + * SPS structures are not filled until the control handler is set up
> > + */
> > + if (!ctx->fh.ctrl_handler)
> > + return 0;
>
> The control handler is embedded in the context, and the fh.ctrl_handler
> is initialized when the context is returned.
>
> You cannot have a context without a control handler (see hantro_open).
>
> > +
> > + switch (ctrl->id) {
> > + case V4L2_CID_STATELESS_H264_SPS:
> > + new_sps = (void *)ctrl->p_new.p_h264_sps;
> > + break;
> > + case V4L2_CID_STATELESS_HEVC_SPS:
> > + new_sps = (void *)ctrl->p_new.p_hevc_sps;
> > + break;
> > + default:
> > + dev_err(ctx->dev->dev, "Unsupported stateless control ID: %x\n", ctrl->id);
> > + return -EINVAL;
> > + };
> > + rkvdec_get_sps_attributes(ctx, new_sps, &attributes);
> > +
> > + /*
> > + * Providing an empty SPS is valid but we do not store it.
> > + */
> > + if (attributes.width == 0 && attributes.height == 0)
> > + return 0;
> > +
> > + pix_mp = &ctx->decoded_fmt.fmt.pix_mp;
> > +
> > + /*
> > + * SPS must match the provided format dimension, if it doesn't userspace has to
> > + * first reset the output format
>
> This comment says it's a mismatch check, but the check is checking for
> "larger than".
>
> Other than that, the general idea looks good, can you rework the series to avoid
> the extra storage of the SPS control in the context?

I'm not fan, but the careless alignment code states that the coded size cannot
be lower then 64x64, but while running the conformance, there is bunch of files
that have coded dimensions lower. And here's the reason why its not ==. I don't
really like this, but confusing allocation padding and coded size capability
seems to be deep down into rkvdec driver design.

If I only look at the FMT(OUTPUT) behaviour, anything < 64x64 is strictly not
supported by the driver, this the interpretation ffmpeg request code have, and
they are actually right. GStreamer simply does not check anything, and try
(there is not validation code there yet, and I don't want to add any until we
figure-out a solution).

>
> Thanks,
> Ezequiel
>
> > + */
> > + if ((attributes.width > pix_mp->width) || (attributes.height > pix_mp->height)) {
> > + dev_err(ctx->dev->dev,
> > + "Dimension mismatch. [%s SPS] W: %d, H: %d, [Format] W: %d, H: %d)\n",
> > + ctrl->id == V4L2_CID_STATELESS_HEVC_SPS ? "HEVC" : "H264",
> > + attributes.width, attributes.height, pix_mp->width, pix_mp->height);
> > + return -EINVAL;
> > + }
> > +
> > + if (ctx->sps && pix_mp->pixelformat == rkvdec_get_valid_fmt(ctx)) {
> > + /*
> > + * Userspace is allowed to change the SPS at any point, if the
> > + * pixel format doesn't differ from the format in the context,
> > + * just accept the change even if buffers are queued
> > + */
> > + ctx->sps = new_sps;
> > + } else {
> > + /*
> > + * Do not accept changing the SPS, while buffers are queued,
> > + * when the new SPS would cause switching the CAPTURE pixel format
> > + */
> > + if (pix_mp->pixelformat != rkvdec_get_valid_fmt(ctx)) {
> > + if (rkvdec_queue_busy(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE))
> > + return -EBUSY;
> > + }
> > + ctx->sps = new_sps;
> > + /*
> > + * For the initial SPS setting and when the pixel format is
> > + * changed adjust the pixel format stored in the context
> > + */
> > + pix_mp->pixelformat = rkvdec_get_valid_fmt(ctx);
> > + rkvdec_fill_decoded_pixfmt(ctx, pix_mp);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
> > {
> > struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
> > @@ -104,8 +177,16 @@ static int rkvdec_try_ctrl(struct v4l2_ctrl *ctrl)
> > return 0;
> > }
> >
> > +static int rkvdec_s_ctrl(struct v4l2_ctrl *ctrl)
> > +{
> > + struct rkvdec_ctx *ctx = container_of(ctrl->handler, struct rkvdec_ctx, ctrl_hdl);
> > +
> > + return rkvdec_set_sps(ctx, ctrl);
> > +}
> > +
> > static const struct v4l2_ctrl_ops rkvdec_ctrl_ops = {
> > .try_ctrl = rkvdec_try_ctrl,
> > + .s_ctrl = rkvdec_s_ctrl,
> > };
> >
> > static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
> >
> > --
> > 2.25.1

2023-01-12 22:47:49

by Nicolas Dufresne

[permalink] [raw]
Subject: Re: [PATCH v2 09/12] staging: media: rkvdec: h264: Add callbacks for h264

Le jeudi 12 janvier 2023 à 12:21 -0300, Ezequiel Garcia a écrit :
> On Thu, Jan 12, 2023 at 9:56 AM Sebastian Fricke
> <[email protected]> wrote:
> >
> > Implement the valid format and sps validation callbacks for H264.
> > H264 already has a SPS validation function, adjust it to fit the
> > function the declaration and add error messages.
> > Additionally, add a function to fetch attributes from the SPS in a human
> > readable format to make the code more self documenting.
> >
> > Signed-off-by: Sebastian Fricke <[email protected]>
> > ---
> > drivers/staging/media/rkvdec/rkvdec-h264.c | 105 ++++++++++++++++++++++-------
> > 1 file changed, 80 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/staging/media/rkvdec/rkvdec-h264.c b/drivers/staging/media/rkvdec/rkvdec-h264.c
> > index 4fc167b42cf0..17b215874ddd 100644
> > --- a/drivers/staging/media/rkvdec/rkvdec-h264.c
> > +++ b/drivers/staging/media/rkvdec/rkvdec-h264.c
> > @@ -1026,40 +1026,80 @@ static int rkvdec_h264_adjust_fmt(struct rkvdec_ctx *ctx,
> > return 0;
> > }
> >
> > -static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx,
> > - const struct v4l2_ctrl_h264_sps *sps)
> > +/*
> > + * Convert some fields from the SPS structure into human readable attributes.
> > + */
> > +static int rkvdec_h264_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
> > + struct sps_attributes *attributes)
> > +{
> > + struct v4l2_ctrl_h264_sps *h264_sps = sps;
> > + unsigned int width = (h264_sps->pic_width_in_mbs_minus1 + 1) * 16;
> > + unsigned int height = (h264_sps->pic_height_in_map_units_minus1 + 1) * 16;
> > + /*
> > + * When frame_mbs_only_flag is not set, this is field height,
> > + * which is half the final height (see (7-18) in the
> > + * specification)
> > + */
> > + if (!(h264_sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
> > + height *= 2;
> > +
> > + attributes->width = width;
> > + attributes->height = height;
> > + attributes->luma_bitdepth = h264_sps->bit_depth_luma_minus8 + 8;
> > + attributes->chroma_bitdepth = h264_sps->bit_depth_chroma_minus8 + 8;
> > + switch (h264_sps->chroma_format_idc) {
> > + case 0:
> > + attributes->subsampling = 400;
> > + break;
> > + case 1:
> > + attributes->subsampling = 420;
> > + break;
> > + case 2:
> > + attributes->subsampling = 422;
> > + break;
> > + case 3:
> > + attributes->subsampling = 444;
> > + break;
> > + };
> > + return 0;
> > +}
> > +
> > +static int rkvdec_h264_validate_sps(struct rkvdec_ctx *ctx, void *sps,
> > + struct v4l2_pix_format_mplane *pix_mp)
> > {
> > - unsigned int width, height;
> > + struct sps_attributes attributes = {0};
> > +
> > + rkvdec_h264_get_sps_attributes(ctx, sps, &attributes);
> >
> > /*
> > * TODO: The hardware supports 10-bit and 4:2:2 profiles,
> > * but it's currently broken in the driver.
> > * Reject them for now, until it's fixed.
> > */
> > - if (sps->chroma_format_idc > 1)
> > - /* Only 4:0:0 and 4:2:0 are supported */
> > + if (attributes.subsampling > 420) {
> > + dev_err(ctx->dev->dev,
> > + "Only 4:0:0 and 4:2:0 subsampling schemes are supported, got: %d\n",
> > + attributes.subsampling);
> > return -EINVAL;
> > - if (sps->bit_depth_luma_minus8 != sps->bit_depth_chroma_minus8)
> > - /* Luma and chroma bit depth mismatch */
> > + }
> > + if (attributes.luma_bitdepth != attributes.chroma_bitdepth) {
> > + dev_err(ctx->dev->dev,
> > + "Luma and chroma bit depth mismatch, luma %d, chroma %d\n",
> > + attributes.luma_bitdepth, attributes.chroma_bitdepth);
> > return -EINVAL;
> > - if (sps->bit_depth_luma_minus8 != 0)
> > - /* Only 8-bit is supported */
> > + }
> > + if (attributes.luma_bitdepth != 8) {
> > + dev_err(ctx->dev->dev, "Only 8-bit H264 formats supported, SPS %d\n",
> > + attributes.luma_bitdepth);
> > return -EINVAL;
> > + }
> >
> > - width = (sps->pic_width_in_mbs_minus1 + 1) * 16;
> > - height = (sps->pic_height_in_map_units_minus1 + 1) * 16;
> > -
> > - /*
> > - * When frame_mbs_only_flag is not set, this is field height,
> > - * which is half the final height (see (7-18) in the
> > - * specification)
> > - */
> > - if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY))
> > - height *= 2;
> > -
> > - if (width > ctx->coded_fmt.fmt.pix_mp.width ||
> > - height > ctx->coded_fmt.fmt.pix_mp.height)
> > + if (attributes.width > pix_mp->width || attributes.height > pix_mp->height) {
> > + dev_err(ctx->dev->dev,
> > + "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.",
> > + attributes.width, attributes.height, pix_mp->width, pix_mp->height);
> > return -EINVAL;
> > + }
> >
> > return 0;
> > }
> > @@ -1077,8 +1117,9 @@ static int rkvdec_h264_start(struct rkvdec_ctx *ctx)
> > if (!ctrl)
> > return -EINVAL;
> >
> > - ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
> > - if (ret)
> > + ret = rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
> > + &ctx->coded_fmt.fmt.pix_mp);
>
> Not a problem with this patch, but I wonder why we accepted a validation
> in the start_streaming step.

Its something we've been discussing a lot lately Benjamin / Sebastian an I (in
person, sorry for that, but sometimes we work better off chats). This is
something none of the reviewers/authors seems to have actually cared about so
far. In stateless decoders we have FMT(OUTPUT) that contains the coded size,
S_CTRL(SOME_HEADERS) which is restricted by the size in FMT(OUTPUT)
(restrictions depends on the codec, could be ==, or smaller) but also used to
create and limit what FMT(CAPTURE) can be.

One thing that raised, is that the width/height alignment has been carelessly
applied to OUTPUT and CAPTURE, saved by the fact the real value is in SPS, but
possibly leading to strange bugs. Notably we notice that some coded sizes
rejected by S_FMT(OUTOUT) still lead to working streamon and decode :-S.

The other aspect is validation. The initial thinking was that we can validate
the SPS (SOME_HEADERS) directly when the control is set. But we found a gap,
userspace could come back and change the coded size in FMT(OUTPUT) to miss-match
the header. We can't reject that, since FMT(OUTPUT) should just always works,
its the first step according to the doc. The doc does not impose closing the
device and restarting from scratch (even though this is what our userspace
currently though). So in short, if the SPS coded size no longer match the OUTPUT
reported coded size, we needed to reject streamon, hence the validation there.
Of course, there was some more mistakes done, like trying to validate when
executing a job, but I think all of these got caught at review.

On of the reflection we have, is that to be more "semantically" aligned with
V4L2 control framework, we should instead of this ensure the the SPS is always
valid. But this is a bit of work for a usecase that no one needs. In short,
S_FMT(OUTPUT) would always reset the SPS by creating one that is valid and
maches the coded size (when the bitstream header have that, the reason its
duplicated is that we wanted to support light coding format which does not carry
that information in the bitstream). The FMT(CAPTURE) would also be reset to
something valid according to both.

Then we'd validate the SPS control against the FMT(OUTPUT) when set, and always
reset the FMT(CAPTURE) accordingly. This way, no more validation would be
required at streamon, since we ensure everything stay valid by discarding past
settings. Such a method needs careful thought, and remember a bit of work, but
it would help prevent further broken logic, for those who haven't noticed,
Hantro G2 HEVC decoder will pick NV12_4L4 by default when you pass a 10bit SPS,
cause no one noticed until today ... But that's not what the spec is expecting,
as its not a "native" format for the bitstream. What I like about this proposal
is that it would remove any remaining possible side effect from a previous
session, trully allowing for reuse of codec instance, but again, this is
theoritical, as long as you can't crash the driver (which the current validation
is about), its not a real bug, most userspace will just set everything all the
time with these CODEC.

Ok, this is getting long, but I just want to keep in mind this is multiple years
of accumulated mistakes (or just delaying known limitation in driver designs),
we should probably not block features completely over getting this right
immediately, as all it does it makes the actual suffer longer. Though, we should
encourage cross-driver fixes whenever something is improved in one driver.

>
> At this point, the driver accepted all the format negotiations in try_fmt.
> It's difficult for applications to recover from this, as there would
> be no way to tell what failed,
> we would be returning EINVAL, which as per the spec is "buffer type is
> not supported,
> or no buffers have been allocated (memory mapping) or enqueued (output) yet.".
>
> I think it would really make a lot of sense to fix this now, instead of continue
> abusing it. And also, I'd like to prevent a possible anti-pattern from
> spreading.
>
> Thanks!
> Ezequiel
>
> > + if (ret < 0)
> > return ret;
> >
> > h264_ctx = kzalloc(sizeof(*h264_ctx), GFP_KERNEL);
> > @@ -1175,10 +1216,21 @@ static int rkvdec_h264_run(struct rkvdec_ctx *ctx)
> > return 0;
> > }
> >
> > +static u32 rkvdec_h264_valid_fmt(struct rkvdec_ctx *ctx)
> > +{
> > + /*
> > + * Only 8 bit 4:0:0 and 4:2:0 formats supported for now.
> > + * The SPS is validated at a different function thus we can assume that
> > + * it is correct.
> > + */
> > + return V4L2_PIX_FMT_NV12;
> > +}
> > +
> > static int rkvdec_h264_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
> > {
> > if (ctrl->id == V4L2_CID_STATELESS_H264_SPS)
> > - return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps);
> > + return rkvdec_h264_validate_sps(ctx, ctrl->p_new.p_h264_sps,
> > + &ctx->coded_fmt.fmt.pix_mp);
> >
> > return 0;
> > }
> > @@ -1189,4 +1241,7 @@ const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops = {
> > .stop = rkvdec_h264_stop,
> > .run = rkvdec_h264_run,
> > .try_ctrl = rkvdec_h264_try_ctrl,
> > + .valid_fmt = rkvdec_h264_valid_fmt,
> > + .sps_check = rkvdec_h264_validate_sps,
> > + .get_sps_attributes = rkvdec_h264_get_sps_attributes,
> > };
> >
> > --
> > 2.25.1

2023-01-13 12:55:53

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format

Hi Sebastian,

I love your patch! Perhaps something to improve:

[auto build test WARNING on 6599e683db1bf22fee74302c47e31b9a42a1c3d2]

url: https://github.com/intel-lab-lkp/linux/commits/Sebastian-Fricke/media-v4l2-Add-NV15-pixel-format/20230112-205935
base: 6599e683db1bf22fee74302c47e31b9a42a1c3d2
patch link: https://lore.kernel.org/r/20230101-patch-series-v2-6-2-rc1-v2-1-fa1897efac14%40collabora.com
patch subject: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format
reproduce:
# https://github.com/intel-lab-lkp/linux/commit/7439d8036125f983bcb57a5e2617ad4f5e2cc88f
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Sebastian-Fricke/media-v4l2-Add-NV15-pixel-format/20230112-205935
git checkout 7439d8036125f983bcb57a5e2617ad4f5e2cc88f
make menuconfig
# enable CONFIG_COMPILE_TEST, CONFIG_WARN_MISSING_DOCUMENTS, CONFIG_WARN_ABI_ERRORS
make htmldocs

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>

All warnings (new ones prefixed by >>):

>> Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst:663: WARNING: Content block expected for the "raw" directive; none found.

vim +/raw +663 Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst

606
607 .. flat-table:: Sample 4x4 NV15 Image
608 :header-rows: 0
609 :stub-columns: 0
610
611 * - start + 0:
612 - Y'\ :sub:`00`
613 - Y'\ :sub:`01`
614 - Y'\ :sub:`02`
615 - Y'\ :sub:`03`
616 * - start + 8:
617 - Y'\ :sub:`04`
618 - Y'\ :sub:`10`
619 - Y'\ :sub:`11`
620 - Y'\ :sub:`12`
621 * - start + 16:
622 - Y'\ :sub:`13`
623 - Y'\ :sub:`14`
624 - Y'\ :sub:`20`
625 - Y'\ :sub:`21`
626 * - start + 24:
627 - Y'\ :sub:`22`
628 - Y'\ :sub:`23`
629 - Y'\ :sub:`24`
630 - Y'\ :sub:`30`
631 * - start + 32:
632 - Y'\ :sub:`31`
633 - Y'\ :sub:`32`
634 - Y'\ :sub:`33`
635 - Y'\ :sub:`34`
636
637 * - start + 0:
638 - Cb\ :sub:`00`
639 - Cr\ :sub:`00`
640 - Cb\ :sub:`01`
641 - Cr\ :sub:`01`
642 * - start + 8:
643 - Cb\ :sub:`02`
644 - Cr\ :sub:`02`
645 - Cb\ :sub:`03`
646 - Cr\ :sub:`03`
647 * - start + 16:
648 - Cb\ :sub:`04`
649 - Cr\ :sub:`04`
650 - Cb\ :sub:`10`
651 - Cr\ :sub:`10`
652 * - start + 24:
653 - Cb\ :sub:`11`
654 - Cr\ :sub:`11`
655 - Cb\ :sub:`12`
656 - Cr\ :sub:`12`
657 * - start + 32:
658 - Cb\ :sub:`13`
659 - Cr\ :sub:`13`
660 - Cb\ :sub:`14`
661 - Cr\ :sub:`14`
662
> 663 .. raw:: latex
664

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests


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2023-01-16 13:05:09

by Andrzej Pietrasiewicz

[permalink] [raw]
Subject: Re: [PATCH v2 12/12] staging: media: rkvdec: Add HEVC backend

Hi Sebastian,

W dniu 12.01.2023 o 13:56, Sebastian Fricke pisze:
> The Rockchip VDEC supports the HEVC codec with the Main and Main10
> Profile up to Level 5.1 High Tier: 4096x2304@60 fps.
> Add the backend for that format to the decoder.
>
> Signed-off-by: Jonas Karlman <[email protected]>
> Signed-off-by: Alex Bee <[email protected]>
> Signed-off-by: Nicolas Dufresne <[email protected]>
> Signed-off-by: Sebastian Fricke <[email protected]>
> ---
> drivers/staging/media/rkvdec/Makefile | 2 +-
> drivers/staging/media/rkvdec/TODO | 11 +-
> drivers/staging/media/rkvdec/rkvdec-hevc-data.c | 1845 +++++++++++++++++++++++
> drivers/staging/media/rkvdec/rkvdec-hevc.c | 910 +++++++++++
> drivers/staging/media/rkvdec/rkvdec-regs.h | 1 +
> drivers/staging/media/rkvdec/rkvdec.c | 72 +
> drivers/staging/media/rkvdec/rkvdec.h | 1 +
> 7 files changed, 2834 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/staging/media/rkvdec/Makefile b/drivers/staging/media/rkvdec/Makefile
> index cb86b429cfaa..a77122641d14 100644
> --- a/drivers/staging/media/rkvdec/Makefile
> +++ b/drivers/staging/media/rkvdec/Makefile
> @@ -1,3 +1,3 @@
> obj-$(CONFIG_VIDEO_ROCKCHIP_VDEC) += rockchip-vdec.o
>
> -rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-vp9.o
> +rockchip-vdec-y += rkvdec.o rkvdec-h264.o rkvdec-hevc.o rkvdec-vp9.o
> diff --git a/drivers/staging/media/rkvdec/TODO b/drivers/staging/media/rkvdec/TODO
> index 2c0779383276..58652251241b 100644
> --- a/drivers/staging/media/rkvdec/TODO
> +++ b/drivers/staging/media/rkvdec/TODO
> @@ -1,11 +1,8 @@
> -* Support for HEVC is planned for this driver.
> -
> - Given the V4L controls for that CODEC will be part of
> - the uABI, it will be required to have the driver in staging.
> -
> - For this reason, we are keeping this driver in staging for now.
> -
> * Evaluate introducing a helper to consolidate duplicated
> code in rkvdec_request_validate and cedrus_request_validate.
> The helper needs to the driver private data associated with
> the videobuf2 queue, from a media request.
> +
> +* Add support for other hardware revisions (like RK3288 etc.)
> +
> +* Fix concurrent decoding for the HEVC codec
> diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc-data.c b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> new file mode 100644
> index 000000000000..d3b7760063ef
> --- /dev/null
> +++ b/drivers/staging/media/rkvdec/rkvdec-hevc-data.c
> @@ -0,0 +1,1845 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip Video Decoder driver
> + *
> + * Copyright (C) 2023 Collabora, Ltd.
> + * Sebastian Fricke <[email protected]>
> + */
> +#include <linux/types.h>
> +
> +#define RKV_CABAC_TABLE_SIZE 27456
> +
> +static const u8 rkvdec_hevc_cabac_table[RKV_CABAC_TABLE_SIZE] = {
> + 0x07, 0x0f, 0x48, 0x58, 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f,
> + 0x68, 0x48, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x40,
> + 0x40, 0x68, 0x58, 0x60, 0x40, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x48, 0x48, 0x60,
> + 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68, 0x68, 0x68, 0x50,
> + 0x48, 0x68, 0x60, 0x60, 0x50, 0x58, 0x50, 0x07, 0x58, 0x68, 0x50, 0x58, 0x68, 0x68, 0x68,
> + 0x68, 0x68, 0x50, 0x48, 0x68, 0x48, 0x48, 0x1f, 0x58, 0x68, 0x68, 0x58, 0x60, 0x60, 0x60,
> + 0x50, 0x50, 0x50, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x48, 0x58, 0x58, 0x37, 0x07, 0x58,
> + 0x48, 0x58, 0x58, 0x37, 0x07, 0x58, 0x50, 0x48, 0x1f, 0x1f, 0x0f, 0x0f, 0x0f, 0x0f, 0x07,
> + 0x0f, 0x48, 0x68, 0x0f, 0x48, 0x68, 0x40, 0x40, 0x50, 0x50, 0x07, 0x40, 0x50, 0x0f, 0x40,
> + 0x48, 0x07, 0x40, 0x27, 0x50, 0x48, 0x48, 0x40, 0x0f, 0x50, 0x37, 0x1f, 0x1f, 0x50, 0x37,
> + 0x40, 0x27, 0x40, 0x07, 0x0f, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0f, 0x47, 0x57,
> + 0x58, 0x40, 0x40, 0x40, 0x40, 0x40, 0x0f, 0x40, 0x40, 0x40, 0x0f, 0x66, 0x47, 0x40, 0x40,
> + 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x07, 0x00, 0x00, 0x67, 0x57, 0x5e,
> + 0x00, 0x1f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x47, 0x47, 0x5f, 0x5f, 0x4f, 0x57, 0x4f,
> + 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47, 0x66, 0x5f, 0x5f,
> + 0x4f, 0x57, 0x4f, 0x07, 0x57, 0x67, 0x4f, 0x57, 0x67, 0x67, 0x67, 0x67, 0x66, 0x4f, 0x47,
> + 0x66, 0x46, 0x48, 0x20, 0x57, 0x67, 0x67, 0x57, 0x5f, 0x5f, 0x5e, 0x4f, 0x4f, 0x4f, 0x47,
> + 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37, 0x07, 0x57, 0x47, 0x57, 0x57, 0x37,
> + 0x07, 0x57, 0x4f, 0x47, 0x1f, 0x1f, 0x0f, 0x10, 0x0f, 0x10, 0x07, 0x10, 0x47, 0x67, 0x10,
> + 0x47, 0x67, 0x40, 0x40, 0x4f, 0x4e, 0x08, 0x00, 0x4f, 0x0f, 0x00, 0x47, 0x07, 0x01, 0x27,
> + 0x4e, 0x47, 0x47, 0x00, 0x0f, 0x4f, 0x37, 0x1f, 0x1f, 0x4f, 0x36, 0x00, 0x27, 0x00, 0x07,
> + 0x10, 0x17, 0x0f, 0x0f, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x0e, 0x47, 0x57, 0x58, 0x40, 0x40, 0x40,
> + 0x40, 0x40, 0x0e, 0x40, 0x40, 0x40, 0x0e, 0x64, 0x47, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40,
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> + 0x47, 0x40, 0x1f, 0x07, 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17,
> + 0x47, 0x40, 0x17, 0x47, 0x40, 0x40, 0x40, 0x40, 0x01, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00,
> + 0x00, 0x2f, 0x27, 0x1f, 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x11, 0x10, 0x08, 0x40, 0x0f, 0x08,
> + 0x00, 0x26, 0x08, 0x36, 0x26, 0x26, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3e, 0x27, 0x07, 0x40,
> + 0x40, 0x47, 0x57, 0x67, 0x2f, 0x40, 0x07, 0x40, 0x40, 0x47, 0x0f, 0x07, 0x27, 0x40, 0x17,
> + 0x17, 0x27, 0x37, 0x3e, 0x3e, 0x07, 0x07, 0x00, 0x00, 0x08, 0x1f, 0x07, 0x07, 0x27, 0x2f,
> + 0x08, 0x40, 0x47, 0x4f, 0x40, 0x40, 0x40, 0x07, 0x07, 0x07, 0x0f, 0x0f, 0x0f, 0x17, 0x1f,
> + 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27, 0x07, 0x0f, 0x0f,
> + 0x0f, 0x17, 0x1f, 0x07, 0x07, 0x07, 0x27, 0x07, 0x40, 0x07, 0x07, 0x27, 0x1f, 0x17, 0x27,
> + 0x27, 0x40, 0x3e, 0x40, 0x4f, 0x40, 0x07, 0x07, 0x07, 0x17, 0x17, 0x37, 0x0f, 0x10, 0x47,
> + 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07, 0x40, 0x10, 0x47, 0x40, 0x1f, 0x07,
> + 0x40, 0x4f, 0x07, 0x0f, 0x0f, 0x1f, 0x27, 0x1f, 0x27, 0x08, 0x17, 0x47, 0x40, 0x17, 0x47,
> + 0x40, 0x40, 0x40, 0x40, 0x00, 0x08, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x00, 0x2f, 0x27, 0x1f,
> + 0x07, 0x27, 0x1f, 0x1f, 0x47, 0x10, 0x10, 0x08, 0x40, 0x0f, 0x08, 0x00, 0x27, 0x08, 0x37,
> + 0x27, 0x27, 0x08, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00,
> + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +};
> +
> diff --git a/drivers/staging/media/rkvdec/rkvdec-hevc.c b/drivers/staging/media/rkvdec/rkvdec-hevc.c
> new file mode 100644
> index 000000000000..d3802ba613ab
> --- /dev/null
> +++ b/drivers/staging/media/rkvdec/rkvdec-hevc.c
> @@ -0,0 +1,910 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Rockchip Video Decoder HEVC backend
> + *
> + * Copyright (C) 2023 Collabora, Ltd.
> + * Sebastian Fricke <[email protected]>
> + *
> + * Copyright (C) 2019 Collabora, Ltd.
> + * Boris Brezillon <[email protected]>
> + *
> + * Copyright (C) 2016 Rockchip Electronics Co., Ltd.
> + * Jeffy Chen <[email protected]>
> + */
> +
> +#include <media/v4l2-mem2mem.h>
> +
> +#include "rkvdec.h"
> +#include "rkvdec-regs.h"
> +#include "rkvdec-hevc-data.c"

I've been looking at the code for a long time and wasn't able to figure out
why file-private rkvdec_hevc_cabac_table from another file is accessible in this
file. This #include explains it. Maybe a comment would be in order to explain
why a .c file is included (I can tell why by the seer size of the cabac table,
but maybe it wouldn't hurt telling it here explicitly).

> +
> +/* Size in u8/u32 units. */
> +#define RKV_SCALING_LIST_SIZE 1360
> +#define SCALING_LIST_SIZE_NUM 4
> +#define RKV_PPS_SIZE (80 / 4)
> +#define RKV_PPS_LEN 64
> +#define RKV_RPS_SIZE (32 / 4)
> +#define RKV_RPS_LEN 600
> +#define RKV_PPS_MAX_COLUMNS 20
> +#define RKV_PPS_MAX_ROWS 22
> +#define RKV_RPS_MAX_REFERENCES 15
> +#define RKV_MAX_DEPTH_IN_BYTES 2
> +
> +struct rkvdec_sps_pps_packet {
> + u32 info[RKV_PPS_SIZE];
> +};
> +
> +struct rkvdec_rps_packet {
> + u32 info[RKV_RPS_SIZE];
> +};
> +
> +struct rkvdec_ps_field {
> + u16 offset;
> + u8 len;
> +};
> +
> +#define PS_FIELD(_offset, _len) \
> + ((struct rkvdec_ps_field){ _offset, _len })
> +
> +/* SPS */
> +#define VIDEO_PARAMETER_SET_ID PS_FIELD(0, 4)

I have a feeling it is a bit over-engineered. It is just that, though,
_a feeling_. And here we discuss technical stuff rather than feelings.
But... The reason of this and the below #defines to me is to name a
pair of numbers at the expense of creating "in-place" structs, which
then need to be copied one-by-one to set_ps_field(). I'm not sure how
clever the compiler can get in this special case, though. Maybe it is
clever enough to eliminate the copies altogether.

But later, when the #defines are used, they tend to be used like this:

WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);

I'm not sure if it is any clearer than

WRITE_PPS(sps->video_parameter_set_id, 4, 4);

The name of the first argument to WRITE_PPS() is informative enough,
what kind of new information do we get if the second parameter basically
repeats the same name in different capitalization style?

IMO there's no added information. Instead, we get rid of "magic numbers", which
are generally frowned upon (by myself, too). But in this special case of filling
in a large number of bitfields I'm not sure if

WRITE_PPS(sps->video_parameter_set_id, 4, 4);

is really worse than

WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);

On the other hand, by dropping the #defines you eliminate a good screenful of
lines of code, a struct definition, the PS_FIELD() macro definition and the
lines where you actually use these #defined numbers become (much) shorter.


> +#define SEQ_PARAMETER_SET_ID PS_FIELD(4, 4)
> +#define CHROMA_FORMAT_IDC PS_FIELD(8, 2)
> +#define PIC_WIDTH_IN_LUMA_SAMPLES PS_FIELD(10, 13)
> +#define PIC_HEIGHT_IN_LUMA_SAMPLES PS_FIELD(23, 13)
> +#define BIT_DEPTH_LUMA PS_FIELD(36, 4)
> +#define BIT_DEPTH_CHROMA PS_FIELD(40, 4)
> +#define LOG2_MAX_PIC_ORDER_CNT_LSB PS_FIELD(44, 5)
> +#define LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(49, 2)
> +#define LOG2_MIN_LUMA_CODING_BLOCK_SIZE PS_FIELD(51, 3)
> +#define LOG2_MIN_TRANSFORM_BLOCK_SIZE PS_FIELD(54, 3)
> +#define LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE PS_FIELD(57, 2)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTER PS_FIELD(59, 3)
> +#define MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA PS_FIELD(62, 3)
> +#define SCALING_LIST_ENABLED_FLAG PS_FIELD(65, 1)
> +#define AMP_ENABLED_FLAG PS_FIELD(66, 1)
> +#define SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG PS_FIELD(67, 1)
> +#define PCM_ENABLED_FLAG PS_FIELD(68, 1)
> +#define PCM_SAMPLE_BIT_DEPTH_LUMA PS_FIELD(69, 4)
> +#define PCM_SAMPLE_BIT_DEPTH_CHROMA PS_FIELD(73, 4)
> +#define PCM_LOOP_FILTER_DISABLED_FLAG PS_FIELD(77, 1)
> +#define LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(78, 3)
> +#define LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE PS_FIELD(81, 3)
> +#define NUM_SHORT_TERM_REF_PIC_SETS PS_FIELD(84, 7)
> +#define LONG_TERM_REF_PICS_PRESENT_FLAG PS_FIELD(91, 1)
> +#define NUM_LONG_TERM_REF_PICS_SPS PS_FIELD(92, 6)
> +#define SPS_TEMPORAL_MVP_ENABLED_FLAG PS_FIELD(98, 1)
> +#define STRONG_INTRA_SMOOTHING_ENABLED_FLAG PS_FIELD(99, 1)
> +#define PPS_MBZ_1 PS_FIELD(100, 7)
> +#define PPS_MBO_1 PS_FIELD(107, 21)
> +/* PPS */
> +#define PIC_PARAMETER_SET_ID PS_FIELD(128, 6)
> +#define PPS_SEQ_PARAMETER_SET_ID PS_FIELD(134, 4)
> +#define DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG PS_FIELD(138, 1)
> +#define OUTPUT_FLAG_PRESENT_FLAG PS_FIELD(139, 1)
> +#define NUM_EXTRA_SLICE_HEADER_BITS PS_FIELD(140, 13)
> +#define SIGN_DATA_HIDING_ENABLED_FLAG PS_FIELD(153, 1)
> +#define CABAC_INIT_PRESENT_FLAG PS_FIELD(154, 1)
> +#define NUM_REF_IDX_L0_DEFAULT_ACTIVE PS_FIELD(155, 4)
> +#define NUM_REF_IDX_L1_DEFAULT_ACTIVE PS_FIELD(159, 4)
> +#define INIT_QP_MINUS26 PS_FIELD(163, 7)
> +#define CONSTRAINED_INTRA_PRED_FLAG PS_FIELD(170, 1)
> +#define TRANSFORM_SKIP_ENABLED_FLAG PS_FIELD(171, 1)
> +#define CU_QP_DELTA_ENABLED_FLAG PS_FIELD(172, 1)
> +#define LOG2_MIN_CU_QP_DELTA_SIZE PS_FIELD(173, 3)
> +#define PPS_CB_QP_OFFSET PS_FIELD(176, 5)
> +#define PPS_CR_QP_OFFSET PS_FIELD(181, 5)
> +#define PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG PS_FIELD(186, 1)
> +#define WEIGHTED_PRED_FLAG PS_FIELD(187, 1)
> +#define WEIGHTED_BIPRED_FLAG PS_FIELD(188, 1)
> +#define TRANSQUANT_BYPASS_ENABLED_FLAG PS_FIELD(189, 1)
> +#define TILES_ENABLED_FLAG PS_FIELD(190, 1)
> +#define ENTROPY_CODING_SYNC_ENABLED_FLAG PS_FIELD(191, 1)
> +#define PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG PS_FIELD(192, 1)
> +#define LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG PS_FIELD(193, 1)
> +#define DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG PS_FIELD(194, 1)
> +#define PPS_DEBLOCKING_FILTER_DISABLED_FLAG PS_FIELD(195, 1)
> +#define PPS_BETA_OFFSET_DIV2 PS_FIELD(196, 4)
> +#define PPS_TC_OFFSET_DIV2 PS_FIELD(200, 4)
> +#define LISTS_MODIFICATION_PRESENT_FLAG PS_FIELD(204, 1)
> +#define LOG2_PARALLEL_MERGE_LEVEL PS_FIELD(205, 3)
> +#define SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG PS_FIELD(208, 1)
> +#define PPS_MBZ_2 PS_FIELD(209, 3)
> +#define NUM_TILE_COLUMNS PS_FIELD(212, 5)
> +#define NUM_TILE_ROWS PS_FIELD(217, 5)
> +#define PPS_M_MODE PS_FIELD(222, 2)
> +#define PPS_MBO_2 PS_FIELD(224, 30)
> +#define COLUMN_WIDTH(i) PS_FIELD(256 + ((i) * 8), 8)
> +#define ROW_HEIGHT(i) PS_FIELD(416 + ((i) * 8), 8)
> +#define SCALING_LIST_ADDRESS PS_FIELD(592, 32)
> +#define PPS_MBO_3 PS_FIELD(624, 16)
> +
> +/* Data structure describing auxiliary buffer format. */
> +struct rkvdec_hevc_priv_tbl {
> + u8 cabac_table[RKV_CABAC_TABLE_SIZE];
> + u8 scaling_list[RKV_SCALING_LIST_SIZE];
> + struct rkvdec_sps_pps_packet param_set[RKV_PPS_LEN];
> + struct rkvdec_rps_packet rps[RKV_RPS_LEN];
> +};
> +
> +struct rkvdec_hevc_run {
> + struct rkvdec_run base;
> + const struct v4l2_ctrl_hevc_slice_params *slices_params;
> + const struct v4l2_ctrl_hevc_decode_params *decode_params;
> + const struct v4l2_ctrl_hevc_sps *sps;
> + const struct v4l2_ctrl_hevc_pps *pps;
> + const struct v4l2_ctrl_hevc_scaling_matrix *scaling_matrix;
> + int num_slices;
> +};
> +
> +struct rkvdec_hevc_ctx {
> + struct rkvdec_aux_buf priv_tbl;
> + struct v4l2_ctrl_hevc_scaling_matrix scaling_matrix_cache;
> +};
> +
> +struct scaling_factor {
> + u8 scalingfactor0[1248];
> + u8 scalingfactor1[96]; /*4X4 TU Rotate, total 16X4*/
> + u8 scalingdc[12]; /*N1005 Vienna Meeting*/
> + u8 reserved[4]; /*16Bytes align*/
> +};
> +
> +static void set_ps_field(u32 *buf, struct rkvdec_ps_field field, u32 value)
> +{
> + u8 bit = field.offset % 32, word = field.offset / 32;
> + u64 mask = GENMASK_ULL(bit + field.len - 1, bit);
> + u64 val = ((u64)value << bit) & mask;
> +
> + buf[word] &= ~mask;
> + buf[word] |= val;
> + if (bit + field.len > 32) {
> + buf[word + 1] &= ~(mask >> 32);
> + buf[word + 1] |= val >> 32;
> + }
> +}
> +
> +static void assemble_hw_pps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
> +{
> + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
> + const struct v4l2_ctrl_hevc_sps *sps = run->sps;
> + const struct v4l2_ctrl_hevc_pps *pps = run->pps;
> + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
> + struct rkvdec_sps_pps_packet *hw_ps;
> + u8 pcm_enabled = 0;
> + u32 min_cb_log2_size_y, ctb_log2_size_y, ctb_size_y;
> + u32 width, height, max_min_cb_size, x, pic_in_cts_width, pic_in_cts_height;
> + u32 log2_min_cu_qp_delta_size, scaling_distance;
> + dma_addr_t scaling_list_address;
> + int i;
> + u32 tmp_w = 0;
> + u32 prev_w = 0;
> + u32 tmp_h = 0;
> + u32 prev_h = 0;
> + u16 column_width[RKV_PPS_MAX_COLUMNS] = {0};
> + u16 row_height[RKV_PPS_MAX_ROWS] = {0};
> +
> + /*
> + * HW read the SPS/PPS information from PPS packet index by PPS id.
> + * offset from the base can be calculated by PPS_id * 80 (size per PPS
> + * packet unit). so the driver copy SPS/PPS information to the exact PPS
> + * packet unit for HW accessing.
> + */
> + hw_ps = &priv_tbl->param_set[pps->pic_parameter_set_id];
> + memset(hw_ps, 0, sizeof(*hw_ps));
> +
> + min_cb_log2_size_y = sps->log2_min_luma_coding_block_size_minus3 + 3;
> + width = sps->pic_width_in_luma_samples;
> + height = sps->pic_height_in_luma_samples;
> + max_min_cb_size = sps->log2_diff_max_min_luma_coding_block_size;
> +
> +#define WRITE_PPS(value, field) set_ps_field(hw_ps->info, field, value)

The macro is called WRITE_PPS

> + /* write sps */

yet you apparently write an SPS here.

> + WRITE_PPS(sps->video_parameter_set_id, VIDEO_PARAMETER_SET_ID);
> + WRITE_PPS(sps->seq_parameter_set_id, SEQ_PARAMETER_SET_ID);
> + WRITE_PPS(sps->chroma_format_idc, CHROMA_FORMAT_IDC);
> + WRITE_PPS(sps->pic_width_in_luma_samples, PIC_WIDTH_IN_LUMA_SAMPLES);
> + WRITE_PPS(sps->pic_height_in_luma_samples, PIC_HEIGHT_IN_LUMA_SAMPLES);
> + WRITE_PPS(sps->bit_depth_luma_minus8 + 8, BIT_DEPTH_LUMA);
> + WRITE_PPS(sps->bit_depth_chroma_minus8 + 8, BIT_DEPTH_CHROMA);
> + WRITE_PPS(sps->log2_max_pic_order_cnt_lsb_minus4 + 4,
> + LOG2_MAX_PIC_ORDER_CNT_LSB);
> + WRITE_PPS(sps->log2_diff_max_min_luma_coding_block_size,
> + LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE);
> + WRITE_PPS(sps->log2_min_luma_coding_block_size_minus3 + 3,
> + LOG2_MIN_LUMA_CODING_BLOCK_SIZE);
> + WRITE_PPS(sps->log2_min_luma_transform_block_size_minus2 + 2,
> + LOG2_MIN_TRANSFORM_BLOCK_SIZE);
> + WRITE_PPS(sps->log2_diff_max_min_luma_transform_block_size,
> + LOG2_DIFF_MAX_MIN_LUMA_TRANSFORM_BLOCK_SIZE);
> + WRITE_PPS(sps->max_transform_hierarchy_depth_inter,
> + MAX_TRANSFORM_HIERARCHY_DEPTH_INTER);
> + WRITE_PPS(sps->max_transform_hierarchy_depth_intra,
> + MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED),
> + SCALING_LIST_ENABLED_FLAG);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_AMP_ENABLED),
> + AMP_ENABLED_FLAG);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET),
> + SAMPLE_ADAPTIVE_OFFSET_ENABLED_FLAG);
> + pcm_enabled = !!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_ENABLED);
> + WRITE_PPS(pcm_enabled, PCM_ENABLED_FLAG);
> + WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_luma_minus1 + 1 : 0,
> + PCM_SAMPLE_BIT_DEPTH_LUMA);
> + WRITE_PPS(pcm_enabled ? sps->pcm_sample_bit_depth_chroma_minus1 + 1 : 0,
> + PCM_SAMPLE_BIT_DEPTH_CHROMA);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED),
> + PCM_LOOP_FILTER_DISABLED_FLAG);
> + WRITE_PPS(sps->log2_diff_max_min_pcm_luma_coding_block_size,
> + LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
> + WRITE_PPS(pcm_enabled ? sps->log2_min_pcm_luma_coding_block_size_minus3 + 3 : 0,
> + LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE);
> + WRITE_PPS(sps->num_short_term_ref_pic_sets, NUM_SHORT_TERM_REF_PIC_SETS);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_LONG_TERM_REF_PICS_PRESENT),
> + LONG_TERM_REF_PICS_PRESENT_FLAG);
> + WRITE_PPS(sps->num_long_term_ref_pics_sps, NUM_LONG_TERM_REF_PICS_SPS);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED),
> + SPS_TEMPORAL_MVP_ENABLED_FLAG);
> + WRITE_PPS(!!(sps->flags & V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED),
> + STRONG_INTRA_SMOOTHING_ENABLED_FLAG);
> + WRITE_PPS(0, PPS_MBZ_1);
> + WRITE_PPS(0x1fffff, PPS_MBO_1);
> +
> + /* write pps */
> + WRITE_PPS(pps->pic_parameter_set_id, PIC_PARAMETER_SET_ID);
> + WRITE_PPS(sps->seq_parameter_set_id, PPS_SEQ_PARAMETER_SET_ID);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED),
> + DEPENDENT_SLICE_SEGMENTS_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT),
> + OUTPUT_FLAG_PRESENT_FLAG);
> + WRITE_PPS(pps->num_extra_slice_header_bits, NUM_EXTRA_SLICE_HEADER_BITS);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED),
> + SIGN_DATA_HIDING_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT),
> + CABAC_INIT_PRESENT_FLAG);
> + WRITE_PPS(pps->num_ref_idx_l0_default_active_minus1 + 1,
> + NUM_REF_IDX_L0_DEFAULT_ACTIVE);
> + WRITE_PPS(pps->num_ref_idx_l1_default_active_minus1 + 1,
> + NUM_REF_IDX_L1_DEFAULT_ACTIVE);
> + WRITE_PPS(pps->init_qp_minus26, INIT_QP_MINUS26);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED),
> + CONSTRAINED_INTRA_PRED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED),
> + TRANSFORM_SKIP_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED),
> + CU_QP_DELTA_ENABLED_FLAG);
> +
> + ctb_log2_size_y = min_cb_log2_size_y +
> + sps->log2_diff_max_min_luma_coding_block_size;
> + ctb_size_y = 1 << ctb_log2_size_y;
> + log2_min_cu_qp_delta_size = ctb_log2_size_y - pps->diff_cu_qp_delta_depth;
> + WRITE_PPS(log2_min_cu_qp_delta_size, LOG2_MIN_CU_QP_DELTA_SIZE);
> + WRITE_PPS(pps->pps_cb_qp_offset, PPS_CB_QP_OFFSET);
> + WRITE_PPS(pps->pps_cr_qp_offset, PPS_CR_QP_OFFSET);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT),
> + PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED),
> + WEIGHTED_PRED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED),
> + WEIGHTED_BIPRED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED),
> + TRANSQUANT_BYPASS_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED),
> + TILES_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED),
> + ENTROPY_CODING_SYNC_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED),
> + PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED),
> + LOOP_FILTER_ACROSS_TILES_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED),
> + DEBLOCKING_FILTER_OVERRIDE_ENABLED_FLAG);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER),
> + PPS_DEBLOCKING_FILTER_DISABLED_FLAG);
> + WRITE_PPS(pps->pps_beta_offset_div2, PPS_BETA_OFFSET_DIV2);
> + WRITE_PPS(pps->pps_tc_offset_div2, PPS_TC_OFFSET_DIV2);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT),
> + LISTS_MODIFICATION_PRESENT_FLAG);
> + WRITE_PPS(pps->log2_parallel_merge_level_minus2 + 2, LOG2_PARALLEL_MERGE_LEVEL);
> + WRITE_PPS(!!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT),
> + SLICE_SEGMENT_HEADER_EXTENSION_PRESENT_FLAG);
> + WRITE_PPS(0, PPS_MBZ_2);
> + WRITE_PPS(pps->num_tile_columns_minus1 + 1, NUM_TILE_COLUMNS);
> + WRITE_PPS(pps->num_tile_rows_minus1 + 1, NUM_TILE_ROWS);
> + WRITE_PPS(3, PPS_M_MODE);
> + WRITE_PPS(0x3fffffff, PPS_MBO_2);
> +
> + if (pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED) {
> + if (pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING) {
> + x = 1 << (min_cb_log2_size_y + max_min_cb_size);
> + pic_in_cts_width = (width + x - 1) / (x);
> + pic_in_cts_height = (height + x - 1) / (x);
> + for (i = 0; i <= pps->num_tile_columns_minus1; i++) {
> + tmp_w = ((i + 1) * pic_in_cts_width) /
> + (pps->num_tile_columns_minus1 + 1);
> + column_width[i] = tmp_w - prev_w - 1;
> + prev_w = tmp_w;
> + }
> + for (i = 0; i <= pps->num_tile_rows_minus1; i++) {
> + tmp_h = ((i + 1) * pic_in_cts_height) /
> + (pps->num_tile_rows_minus1 + 1);
> + row_height[i] = tmp_h - prev_h - 1;
> + prev_h = tmp_h;
> + }
> + } else {
> + for (i = 0; i <= pps->num_tile_columns_minus1; i++)
> + column_width[i] = pps->column_width_minus1[i];
> + for (i = 0; i <= pps->num_tile_rows_minus1; i++)
> + row_height[i] = pps->row_height_minus1[i];
> + }
> + } else {
> + column_width[0] =
> + ((sps->pic_width_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1;
> + row_height[0] =
> + ((sps->pic_height_in_luma_samples + ctb_size_y - 1) / ctb_size_y) - 1;
> + }
> +
> + for (i = 0; i < RKV_PPS_MAX_COLUMNS; i++)
> + WRITE_PPS(column_width[i], COLUMN_WIDTH(i));
> + for (i = 0; i < RKV_PPS_MAX_ROWS; i++)
> + WRITE_PPS(row_height[i], ROW_HEIGHT(i));
> +
> + scaling_distance = offsetof(struct rkvdec_hevc_priv_tbl, scaling_list);
> + scaling_list_address = hevc_ctx->priv_tbl.dma + scaling_distance;
> + WRITE_PPS(scaling_list_address, SCALING_LIST_ADDRESS);
> + WRITE_PPS(0xffff, PPS_MBO_3);
> +}
> +
> +/*
> + * Creation of the Reference Picture Set memory blob for the hardware.
> + * The layout looks like this:
> + * [0] 32 bits for L0 (6 references + 2 bits of the 7th reference)
> + * [1] 32 bits for L0 (remaining 3 bits of the 7th reference + 5 references
> + * + 4 bits of the 13th reference)
> + * [2] 11 bits for L0 (remaining bit for 13 and 2 references) and
> + * 21 bits for L1 (4 references + first bit of 5)
> + * [3] 32 bits of padding with 0s
> + * [4] 32 bits for L1 (remaining 4 bits for 5 + 5 references + 3 bits of 11)
> + * [5] 22 bits for L1 (remaining 2 bits of 11 and 4 references)
> + * lowdelay flag (bit 23), rps bit offset long term (bit 24 - 32)
> + * [6] rps bit offset long term (bit 1 - 3), rps bit offset short term (bit 4 - 12)
> + * number of references (bit 13 - 16), remaining 16 bits of padding with 0s
> + * [7] 32 bits of padding with 0s
> + *
> + * Thus we have to set up padding in between reference 5 of the L1 list.
> + */
> +static void assemble_hw_rps(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
> +{
> + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
> + const struct v4l2_ctrl_hevc_sps *sps = run->sps;
> + const struct v4l2_ctrl_hevc_slice_params *sl_params;
> + const struct v4l2_hevc_dpb_entry *dpb;
> + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
> + struct rkvdec_hevc_priv_tbl *priv_tbl = hevc_ctx->priv_tbl.cpu;
> + struct rkvdec_rps_packet *hw_ps;
> + int i, j;
> + unsigned int lowdelay;
> +
> +#define WRITE_RPS(value, field) set_ps_field(hw_ps->info, field, value)

This expands to exactly the same thing as WRITE_PPS. Maybe instead define it
once and call it WRITE_PS(.....)? But leaving it as-is is also ok, as long,
as you don't have to modify the macro definition. If you ever need to do so,
it is better, if it is in one place. Maybe even define WRITE_PS() and _then_
define WRITE_SPS() and WRITE_RPS() in terms of WRITE_PS()?

> +
> +#define REF_PIC_LONG_TERM_L0(i) PS_FIELD((i) * 5, 1)
> +#define REF_PIC_IDX_L0(i) PS_FIELD(1 + ((i) * 5), 4)
> +#define REF_PIC_LONG_TERM_L1(i) PS_FIELD(((i) < 5 ? 75 : 132) + ((i) * 5), 1)
> +#define REF_PIC_IDX_L1(i) PS_FIELD(((i) < 4 ? 76 : 128) + ((i) * 5), 4)
> +
> +#define LOWDELAY PS_FIELD(182, 1)
> +#define LONG_TERM_RPS_BIT_OFFSET PS_FIELD(183, 10)
> +#define SHORT_TERM_RPS_BIT_OFFSET PS_FIELD(193, 9)
> +#define NUM_RPS_POC PS_FIELD(202, 4)
> +
> + for (j = 0; j < run->num_slices; j++) {
> + uint st_bit_offset = 0;
> + uint num_l0_refs = 0;
> + uint num_l1_refs = 0;
> +
> + sl_params = &run->slices_params[j];
> + dpb = decode_params->dpb;
> +
lowdelay = 0; //and then...
> + if (sl_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
> + num_l0_refs = sl_params->num_ref_idx_l0_active_minus1 + 1;
> +
> + if (sl_params->slice_type == V4L2_HEVC_SLICE_TYPE_B)
> + num_l1_refs = sl_params->num_ref_idx_l1_active_minus1 + 1;
> +
> + lowdelay = 1;
> + } else {
> + lowdelay = 0;
> + }

you can eliminate the "else" branch. _Theoretically_ you lose some
performance this way, because lowdelay is always set to 0 even if
a moment later it is overwritten with 1. But then the compiler,
if told to fight for performance, might do its job. I usually opt
for less lines of code read by humans (which, given how smart the
compilers are, does not necessarily mean less lines of machine
code). No strong opinion, though, I'm fine either way.

> +
> + hw_ps = &priv_tbl->rps[j];
> + memset(hw_ps, 0, sizeof(*hw_ps));
> +
> + for (i = 0; i < num_l0_refs; i++) {
> + const struct v4l2_hevc_dpb_entry dpb_l0 = dpb[sl_params->ref_idx_l0[i]];
> +
> + WRITE_RPS(!!(dpb_l0.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE),
> + REF_PIC_LONG_TERM_L0(i));
> + WRITE_RPS(sl_params->ref_idx_l0[i], REF_PIC_IDX_L0(i));
> +
> + if (dpb_l0.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
> + lowdelay = 0;
> + }
> +
> + for (i = 0; i < num_l1_refs; i++) {
> + const struct v4l2_hevc_dpb_entry dpb_l1 = dpb[sl_params->ref_idx_l1[i]];
> + int is_long_term =
> + !!(dpb_l1.flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE);
> +
> + WRITE_RPS(is_long_term, REF_PIC_LONG_TERM_L1(i));
> + WRITE_RPS(sl_params->ref_idx_l1[i], REF_PIC_IDX_L1(i));
> +
> + if (dpb_l1.pic_order_cnt_val > sl_params->slice_pic_order_cnt)
> + lowdelay = 0;
> + }
> +
> + WRITE_RPS(lowdelay, LOWDELAY);
> +
> + if (!(decode_params->flags & V4L2_HEVC_DECODE_PARAM_FLAG_IDR_PIC)) {
> + if (sl_params->short_term_ref_pic_set_size)
> + st_bit_offset = sl_params->short_term_ref_pic_set_size;
> + else if (sps->num_short_term_ref_pic_sets > 1)
> + st_bit_offset = fls(sps->num_short_term_ref_pic_sets - 1);
> + }
> +
> + WRITE_RPS(st_bit_offset + sl_params->long_term_ref_pic_set_size,
> + LONG_TERM_RPS_BIT_OFFSET);
> + WRITE_RPS(sl_params->short_term_ref_pic_set_size,
> + SHORT_TERM_RPS_BIT_OFFSET);
> +
> + WRITE_RPS(decode_params->num_poc_st_curr_before +
> + decode_params->num_poc_st_curr_after +
> + decode_params->num_poc_lt_curr,
> + NUM_RPS_POC);
> + }
> +}
> +
> +/*
> + * Flip one or more matrices along their main diagonal and flatten them
> + * before writing it to the memory.
> + * Convert:
> + * ABCD AEIM
> + * EFGH => BFJN => AEIMBFJNCGKODHLP
> + * IJKL CGKO
> + * MNOP DHLP
> + */
> +static void rotate_and_flatten_matrices(u8 *output, const u8 *input, int matrices, int row_length)

Isn't flipping/rotating (i.e. replacing rows with columns, and colums with rows)
called "transposition" of a matrix? So transpose_and_flatten_matrices() ?

Then, what is actually the "flatten" part? Isn't it a no-op?
The function treats "matrices" as blocks of u8 elements without any internal
structure, just a sequence of u8 (well, even a 2-dimensional array would
effectively be the same thing). So IMO there's no any additional "flattening"
happening, so the name just as well could become transpose_matrices().

> +{
> + int i, j, row, x_offset, matrix_offset, rot_index, y_offset, matrix_size, new_value;
> +
> + matrix_size = row_length * row_length;
> + for (i = 0; i < matrices; i++) {
> + row = 0;
> + x_offset = 0;
> + matrix_offset = i * matrix_size;
> + for (j = 0; j < matrix_size; j++) {
> + y_offset = j - (row * row_length);
> + rot_index = y_offset * row_length + x_offset;
> + new_value = *(input + i * matrix_size + j);
> + output[matrix_offset + rot_index] = *(input + i * matrix_size + j);
> + if ((j + 1) % row_length == 0) {
> + row += 1;
> + x_offset += 1;
> + }
> + }
> + }
> +}
> +
> +static void assemble_scalingfactor0(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
> +{
> + int offset = 0;
> +
> + rotate_and_flatten_matrices(output, (const u8 *)input->scaling_list_4x4, 6, 4);
> + offset = 6 * 16 * sizeof(u8);
> + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_8x8, 6, 8);
> + offset += 6 * 64 * sizeof(u8);
> + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_16x16, 6, 8);
> + offset += 6 * 64 * sizeof(u8);
> + /* Add a 128 byte padding with 0s between the two 32x32 matrices */
> + rotate_and_flatten_matrices(output + offset, (const u8 *)input->scaling_list_32x32, 1, 8);
> + offset += 64 * sizeof(u8);
> + memset(output + offset, 0, 128);
> + offset += 128 * sizeof(u8);
> + rotate_and_flatten_matrices(output + offset,
> + (const u8 *)input->scaling_list_32x32 + (64 * sizeof(u8)),
> + 1, 8);
> + offset += 64 * sizeof(u8);
> + memset(output + offset, 0, 128);
> +}
> +
> +/*
> + * Required layout:
> + * A = scaling_list_dc_coef_16x16
> + * B = scaling_list_dc_coef_32x32
> + * 0 = Padding
> + *
> + * A, A, A, A, A, A, B, 0, 0, B, 0, 0
> + */
> +static void assemble_scalingdc(u8 *output, const struct v4l2_ctrl_hevc_scaling_matrix *input)
> +{
> + u8 list_32x32[6] = {0};
> +
> + memcpy(output, input->scaling_list_dc_coef_16x16, 6 * sizeof(u8));
> + list_32x32[0] = input->scaling_list_dc_coef_32x32[0];
> + list_32x32[3] = input->scaling_list_dc_coef_32x32[1];
> + memcpy(output + 6 * sizeof(u8), list_32x32, 6 * sizeof(u8));
> +}
> +
> +static void translate_scaling_list(struct scaling_factor *output,
> + const struct v4l2_ctrl_hevc_scaling_matrix *input)
> +{
> + assemble_scalingfactor0(output->scalingfactor0, input);
> + memcpy(output->scalingfactor1, (const u8 *)input->scaling_list_4x4, 96);
> + assemble_scalingdc(output->scalingdc, input);
> + memset(output->reserved, 0, 4 * sizeof(u8));
> +}
> +
> +static void assemble_hw_scaling_list(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
> +{
> + const struct v4l2_ctrl_hevc_scaling_matrix *scaling = run->scaling_matrix;
> + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
> + struct rkvdec_hevc_priv_tbl *tbl = hevc_ctx->priv_tbl.cpu;
> + u8 *dst;
> +
> + if (!memcmp((void *)&hevc_ctx->scaling_matrix_cache, scaling,
> + sizeof(struct v4l2_ctrl_hevc_scaling_matrix)))
> + return;
> +
> + dst = tbl->scaling_list;
> + translate_scaling_list((struct scaling_factor *)dst, scaling);
> +
> + memcpy((void *)&hevc_ctx->scaling_matrix_cache, scaling,
> + sizeof(struct v4l2_ctrl_hevc_scaling_matrix));
> +}
> +
> +static struct vb2_buffer *
> +get_ref_buf(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run, unsigned int dpb_idx)
> +{
> + struct v4l2_m2m_ctx *m2m_ctx = ctx->fh.m2m_ctx;
> + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
> + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
> + struct vb2_queue *cap_q = &m2m_ctx->cap_q_ctx.q;
> + struct vb2_buffer *buf = NULL;
> +
> + if (dpb_idx < decode_params->num_active_dpb_entries)
> + buf = vb2_find_buffer(cap_q, dpb[dpb_idx].timestamp);
> +
> + /*
> + * If a DPB entry is unused or invalid, the address of current destination
> + * buffer is returned.
> + */
> + if (!buf)
> + return &run->base.bufs.dst->vb2_buf;
> +
> + return buf;
> +}
> +
> +static void config_registers(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
> +{
> + struct rkvdec_dev *rkvdec = ctx->dev;
> + const struct v4l2_ctrl_hevc_decode_params *decode_params = run->decode_params;
> + const struct v4l2_ctrl_hevc_slice_params *sl_params = &run->slices_params[0];
> + const struct v4l2_hevc_dpb_entry *dpb = decode_params->dpb;
> + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
> + dma_addr_t priv_start_addr = hevc_ctx->priv_tbl.dma;
> + const struct v4l2_pix_format_mplane *dst_fmt;
> + struct vb2_v4l2_buffer *src_buf = run->base.bufs.src;
> + struct vb2_v4l2_buffer *dst_buf = run->base.bufs.dst;
> + const struct v4l2_format *f;
> + dma_addr_t rlc_addr;
> + dma_addr_t refer_addr;
> + u32 rlc_len;
> + u32 hor_virstride;
> + u32 ver_virstride;
> + u32 y_virstride;
> + u32 uv_virstride;
> + u32 yuv_virstride;
> + u32 offset;
> + dma_addr_t dst_addr;
> + u32 reg, i;
> +
> + reg = RKVDEC_MODE(RKVDEC_MODE_HEVC);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_SYSCTRL);
> +
> + f = &ctx->decoded_fmt;
> + dst_fmt = &f->fmt.pix_mp;
> + hor_virstride = dst_fmt->plane_fmt[0].bytesperline;
> + ver_virstride = dst_fmt->height;
> + y_virstride = hor_virstride * ver_virstride;
> + uv_virstride = y_virstride / 2;
> + yuv_virstride = y_virstride + uv_virstride;
> +
> + reg = RKVDEC_Y_HOR_VIRSTRIDE(hor_virstride / 16) |
> + RKVDEC_UV_HOR_VIRSTRIDE(hor_virstride / 16) |
> + RKVDEC_SLICE_NUM_LOWBITS(run->num_slices);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_PICPAR);
> +
> + /* config rlc base address */

Given the function is called config_registers() maybe you can drop
the word "config" from these comments, but no strong opinion,
I'm fine with either. Or perhaps you can instead

/* rlc base address register */

but then the word "register" keeps repeating. But if I were to choose
between /* config rlc base address */ and /* rlc base address register */
I'd rather choose the latter, because all the function does is configuring
some registers and the comments are meant to indicate which particular one
is being configured.

Anyway, this is a really minor thing and if you choose to do nothing
about it, I'm fine with that, too.

> + rlc_addr = vb2_dma_contig_plane_dma_addr(&src_buf->vb2_buf, 0);
> + writel_relaxed(rlc_addr, rkvdec->regs + RKVDEC_REG_STRM_RLC_BASE);
> +
> + rlc_len = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
> + reg = RKVDEC_STRM_LEN(round_up(rlc_len, 16) + 64);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_STRM_LEN);
> +
> + /* config cabac table */
> + offset = offsetof(struct rkvdec_hevc_priv_tbl, cabac_table);
> + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_CABACTBL_PROB_BASE);
> +
> + /* config output base address */
> + dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
> + writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
> +
> + reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
> +
> + reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
> +
> + /* config ref pic address */
> + for (i = 0; i < 15; i++) {
> + struct vb2_buffer *vb_buf = get_ref_buf(ctx, run, i);
> +
> + if (i < 4 && decode_params->num_active_dpb_entries) {
> + reg = GENMASK(decode_params->num_active_dpb_entries - 1, 0);
> + reg = (reg >> (i * 4)) & 0xf;
> + } else {
> + reg = 0;
> + }
> +
> + refer_addr = vb2_dma_contig_plane_dma_addr(vb_buf, 0);
> + writel_relaxed(refer_addr | reg, rkvdec->regs + RKVDEC_REG_H264_BASE_REFER(i));
> +
> + reg = RKVDEC_POC_REFER(i < decode_params->num_active_dpb_entries ?
> + dpb[i].pic_order_cnt_val : 0);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_H264_POC_REFER0(i));
> + }
> +
> + reg = RKVDEC_CUR_POC(sl_params->slice_pic_order_cnt);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_CUR_POC0);
> +
> + /* config hw pps address */
> + offset = offsetof(struct rkvdec_hevc_priv_tbl, param_set);
> + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_PPS_BASE);
> +
> + /* config hw rps address */
> + offset = offsetof(struct rkvdec_hevc_priv_tbl, rps);
> + writel_relaxed(priv_start_addr + offset, rkvdec->regs + RKVDEC_REG_RPS_BASE);
> +
> + reg = RKVDEC_AXI_DDR_RDATA(0);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_RDATA);
> +
> + reg = RKVDEC_AXI_DDR_WDATA(0);
> + writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_AXI_DDR_WDATA);
> +}
> +
> +static int rkvdec_hevc_adjust_fmt(struct rkvdec_ctx *ctx, struct v4l2_format *f)
> +{
> + struct v4l2_pix_format_mplane *fmt = &f->fmt.pix_mp;
> +
> + fmt->num_planes = 1;
> + if (!fmt->plane_fmt[0].sizeimage)
> + fmt->plane_fmt[0].sizeimage =
> + fmt->width * fmt->height * RKV_MAX_DEPTH_IN_BYTES;
> + return 0;
> +}
> +
> +static int rkvdec_hevc_start(struct rkvdec_ctx *ctx)
> +{
> + struct rkvdec_dev *rkvdec = ctx->dev;
> + struct rkvdec_hevc_priv_tbl *priv_tbl;
> + struct rkvdec_hevc_ctx *hevc_ctx;
> + int ret;
> +
> + hevc_ctx = kzalloc(sizeof(*hevc_ctx), GFP_KERNEL);
> + if (!hevc_ctx)
> + return -ENOMEM;
> +
> + priv_tbl = dma_alloc_coherent(rkvdec->dev, sizeof(*priv_tbl),
> + &hevc_ctx->priv_tbl.dma, GFP_KERNEL);
> + if (!priv_tbl) {
> + ret = -ENOMEM;
> + goto err_free_ctx;
> + }
> +
> + hevc_ctx->priv_tbl.size = sizeof(*priv_tbl);
> + hevc_ctx->priv_tbl.cpu = priv_tbl;
> + memset(priv_tbl, 0, sizeof(*priv_tbl));
> + memcpy(priv_tbl->cabac_table, rkvdec_hevc_cabac_table, sizeof(rkvdec_hevc_cabac_table));
> +
> + ctx->priv = hevc_ctx;
> + return 0;
> +
> +err_free_ctx:
> + kfree(hevc_ctx);
> + return ret;
> +}
> +
> +static void rkvdec_hevc_stop(struct rkvdec_ctx *ctx)
> +{
> + struct rkvdec_hevc_ctx *hevc_ctx = ctx->priv;
> + struct rkvdec_dev *rkvdec = ctx->dev;
> +
> + dma_free_coherent(rkvdec->dev, hevc_ctx->priv_tbl.size,
> + hevc_ctx->priv_tbl.cpu, hevc_ctx->priv_tbl.dma);
> + kfree(hevc_ctx);
> +}
> +
> +static int rkvdec_hevc_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_hevc_run *run)
> +{
> + struct v4l2_ctrl *ctrl;
> +
> + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_DECODE_PARAMS);
> + run->decode_params = ctrl ? ctrl->p_cur.p : NULL;

This is not the first time I'm saying we keep repeating this pattern in drivers.
See hantro_get_ctrl(). It tends to be used rather a lot, so maybe a helper is
in order? Maybe an opt-in helper could be used so that you don't have to change
all the drivers that follow this pattern. The invocation is repeated 5 times
here, so it already makes sense to have a wrapper. Why not make it available to
all interested drivers?

> + if (WARN_ON(!run->decode_params))
> + return -EINVAL;
> + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SLICE_PARAMS);
> + run->slices_params = ctrl ? ctrl->p_cur.p : NULL;
> + if (WARN_ON(!run->slices_params))
> + return -EINVAL;
> + run->num_slices = ctrl->new_elems;
> + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SPS);
> + run->sps = ctrl ? ctrl->p_cur.p : NULL;
> + if (WARN_ON(!run->sps))
> + return -EINVAL;
> + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_PPS);
> + run->pps = ctrl ? ctrl->p_cur.p : NULL;
> + if (WARN_ON(!run->pps))
> + return -EINVAL;
> + ctrl = v4l2_ctrl_find(&ctx->ctrl_hdl, V4L2_CID_STATELESS_HEVC_SCALING_MATRIX);
> + run->scaling_matrix = ctrl ? ctrl->p_cur.p : NULL;
> + if (WARN_ON(!run->scaling_matrix))
> + return -EINVAL;
> +
> + rkvdec_run_preamble(ctx, &run->base);
> + return 0;
> +}
> +
> +static void start_hardware(struct rkvdec_dev *rkvdec)
> +{
> + void __iomem *register_base_addr = rkvdec->regs;
> + struct delayed_work *watchdog_worker = &rkvdec->watchdog_work;
> + /*
> + * RkVDEC error detection doesn't work really well and seems racy
> + * and unstable. Disable it.
> + */
> + writel_relaxed(0, register_base_addr + RKVDEC_REG_STRMD_ERR_EN);
> + writel_relaxed(0, register_base_addr + RKVDEC_REG_H264_ERR_E);
> +
> + schedule_delayed_work(watchdog_worker, msecs_to_jiffies(2000));
> +
> + writel(1, register_base_addr + RKVDEC_REG_PREF_LUMA_CACHE_COMMAND);
> + writel(1, register_base_addr + RKVDEC_REG_PREF_CHR_CACHE_COMMAND);
> +
> + /* Start decoding! */
> + writel(RKVDEC_INTERRUPT_DEC_E | RKVDEC_CONFIG_DEC_CLK_GATE_E |
> + RKVDEC_TIMEOUT_E | RKVDEC_BUF_EMPTY_E,
> + register_base_addr + RKVDEC_REG_INTERRUPT);
> +}
> +
> +static u32 rkvdec_hevc_valid_fmt(struct rkvdec_ctx *ctx)
> +{
> + const struct v4l2_ctrl_hevc_sps *sps = ctx->sps;
> +
> + /*
> + * No need to check chroma_format_idc, currently only 4:2:0 formats
> + * supported.
> + */
> + if (sps && sps->bit_depth_luma_minus8 == 2)
> + return V4L2_PIX_FMT_NV15;
> + else
> + return V4L2_PIX_FMT_NV12;
> +}
> +
> +/*
> + * Convert some fields from the SPS structure into human readable attributes.
> + */
> +static int rkvdec_hevc_get_sps_attributes(struct rkvdec_ctx *ctx, void *sps,
> + struct sps_attributes *attributes)
> +{
> + struct v4l2_ctrl_hevc_sps *hevc_sps = sps;
> + unsigned int width = hevc_sps->pic_width_in_luma_samples;
> + unsigned int height = hevc_sps->pic_height_in_luma_samples;
> +
> + if (!(width % 64 == 0))
> + width = ALIGN(width, 64);
> +
> + if (!(height % 16 == 0))
> + height = ALIGN(height, 16);
> +
> + attributes->width = width;
> + attributes->height = height;
> + attributes->luma_bitdepth = hevc_sps->bit_depth_luma_minus8 + 8;
> + attributes->chroma_bitdepth = hevc_sps->bit_depth_chroma_minus8 + 8;
> + switch (hevc_sps->chroma_format_idc) {
> + case 0:
> + attributes->subsampling = 400;
> + break;
> + case 1:
> + attributes->subsampling = 420;
> + break;
> + case 2:
> + attributes->subsampling = 422;
> + break;
> + case 3:
> + attributes->subsampling = 444;
> + break;
> + };
> +
> + return 0;
> +}
> +
> +static int rkvdec_hevc_validate_sps(struct rkvdec_ctx *ctx, void *sps,
> + struct v4l2_pix_format_mplane *pix_mp)
> +{
> + struct sps_attributes attributes = {0};
> +
> + rkvdec_hevc_get_sps_attributes(ctx, sps, &attributes);
> +
> + if ((attributes.width != pix_mp->width) || (attributes.height != pix_mp->height)) {
> + dev_err(ctx->dev->dev,
> + "Incompatible SPS dimension, SPS %dx%d, Pixel format %dx%d.",
> + attributes.width, attributes.height, pix_mp->width, pix_mp->height);
> + return -EINVAL;
> + }
> +
> + if ((attributes.luma_bitdepth == 8 && pix_mp->pixelformat != V4L2_PIX_FMT_NV12) ||
> + (attributes.luma_bitdepth == 10 && pix_mp->pixelformat != V4L2_PIX_FMT_NV15)) {
> + dev_err(ctx->dev->dev,
> + "Incompatible SPS bit-depth, SPS %d, Pixel format %d.",
> + attributes.luma_bitdepth,
> + pix_mp->pixelformat == V4L2_PIX_FMT_NV12 ? 8 : 10);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int rkvdec_hevc_try_ctrl(struct rkvdec_ctx *ctx, struct v4l2_ctrl *ctrl)
> +{
> + struct sps_attributes attributes = {0};
> +
> + rkvdec_hevc_get_sps_attributes(ctx, ctrl->p_new.p_hevc_sps, &attributes);
> +
> + if (attributes.subsampling > 420)
> + return -EINVAL;
> + if (attributes.luma_bitdepth != 8 && attributes.luma_bitdepth != 10)
> + return -EINVAL;
> + return 0;
> +}
> +
> +static int rkvdec_hevc_run(struct rkvdec_ctx *ctx)
> +{
> + struct rkvdec_dev *rkvdec = ctx->dev;
> + struct rkvdec_hevc_run run;
> + int ret;
> +
> + ret = rkvdec_hevc_run_preamble(ctx, &run);
> + if (ret) {
> + dev_err(ctx->dev->dev, "Missing required controls for the RkVDEC HEVC decoder.");
> + return ret;
> + }
> +
> + assemble_hw_scaling_list(ctx, &run);
> + assemble_hw_pps(ctx, &run);
> + assemble_hw_rps(ctx, &run);
> + config_registers(ctx, &run);
> + rkvdec_run_postamble(ctx, &run.base);
> + start_hardware(rkvdec);
> +
> + return 0;
> +}
> +
> +const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops = {
> + .adjust_fmt = rkvdec_hevc_adjust_fmt,
> + .start = rkvdec_hevc_start,
> + .stop = rkvdec_hevc_stop,
> + .run = rkvdec_hevc_run,
> + .try_ctrl = rkvdec_hevc_try_ctrl,
> + .valid_fmt = rkvdec_hevc_valid_fmt,
> + .sps_check = rkvdec_hevc_validate_sps,
> + .get_sps_attributes = rkvdec_hevc_get_sps_attributes,
> +};
> diff --git a/drivers/staging/media/rkvdec/rkvdec-regs.h b/drivers/staging/media/rkvdec/rkvdec-regs.h
> index 15b9bee92016..83bf790ed9b7 100644
> --- a/drivers/staging/media/rkvdec/rkvdec-regs.h
> +++ b/drivers/staging/media/rkvdec/rkvdec-regs.h
> @@ -43,6 +43,7 @@
> #define RKVDEC_RLC_MODE BIT(11)
> #define RKVDEC_STRM_START_BIT(x) (((x) & 0x7f) << 12)
> #define RKVDEC_MODE(x) (((x) & 0x03) << 20)
> +#define RKVDEC_MODE_HEVC 0
> #define RKVDEC_MODE_H264 1
> #define RKVDEC_MODE_VP9 2
> #define RKVDEC_RPS_MODE BIT(24)
> diff --git a/drivers/staging/media/rkvdec/rkvdec.c b/drivers/staging/media/rkvdec/rkvdec.c
> index 3d413c5ad1d2..6462dd83ea6d 100644
> --- a/drivers/staging/media/rkvdec/rkvdec.c
> +++ b/drivers/staging/media/rkvdec/rkvdec.c
> @@ -13,6 +13,7 @@
> #include <linux/interrupt.h>
> #include <linux/module.h>
> #include <linux/of.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/pm.h>
> #include <linux/pm_runtime.h>
> @@ -230,6 +231,62 @@ static const struct rkvdec_ctrl_desc rkvdec_h264_ctrl_descs[] = {
> },
> };
>
> +static const struct rkvdec_ctrl_desc rkvdec_hevc_ctrl_descs[] = {
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_SLICE_PARAMS,
> + .cfg.name = "Slice parameters",
> + .cfg.flags = V4L2_CTRL_FLAG_DYNAMIC_ARRAY,
> + .cfg.type = V4L2_CTRL_TYPE_HEVC_SLICE_PARAMS,
> + .cfg.dims = { 600 },
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_SPS,
> + .cfg.ops = &rkvdec_ctrl_ops,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_PPS,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_SCALING_MATRIX,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_PARAMS,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_DECODE_MODE,
> + .cfg.min = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + .cfg.max = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + .cfg.def = V4L2_STATELESS_HEVC_DECODE_MODE_FRAME_BASED,
> + },
> + {
> + .cfg.id = V4L2_CID_STATELESS_HEVC_START_CODE,
> + .cfg.min = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + .cfg.def = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + .cfg.max = V4L2_STATELESS_HEVC_START_CODE_ANNEX_B,
> + },
> + {
> + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_PROFILE,
> + .cfg.min = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + .cfg.max = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN_10,
> + .cfg.def = V4L2_MPEG_VIDEO_HEVC_PROFILE_MAIN,
> + },
> + {
> + .cfg.id = V4L2_CID_MPEG_VIDEO_HEVC_LEVEL,
> + .cfg.min = V4L2_MPEG_VIDEO_HEVC_LEVEL_1,
> + .cfg.max = V4L2_MPEG_VIDEO_HEVC_LEVEL_5_1,
> + },
> +};
> +
> +static const struct rkvdec_ctrls rkvdec_hevc_ctrls = {
> + .ctrls = rkvdec_hevc_ctrl_descs,
> + .num_ctrls = ARRAY_SIZE(rkvdec_hevc_ctrl_descs),
> +};
> +
> +static const u32 rkvdec_hevc_decoded_fmts[] = {
> + V4L2_PIX_FMT_NV12,
> + V4L2_PIX_FMT_NV15,
> +};
> +
> static const struct rkvdec_ctrls rkvdec_h264_ctrls = {
> .ctrls = rkvdec_h264_ctrl_descs,
> .num_ctrls = ARRAY_SIZE(rkvdec_h264_ctrl_descs),
> @@ -260,6 +317,21 @@ static const struct rkvdec_ctrls rkvdec_vp9_ctrls = {
> };
>
> static const struct rkvdec_coded_fmt_desc rkvdec_coded_fmts[] = {
> + {
> + .fourcc = V4L2_PIX_FMT_HEVC_SLICE,
> + .frmsize = {
> + .min_width = 64,
> + .max_width = 4096,
> + .step_width = 64,
> + .min_height = 64,
> + .max_height = 2304,
> + .step_height = 16,
> + },
> + .ctrls = &rkvdec_hevc_ctrls,
> + .ops = &rkvdec_hevc_fmt_ops,
> + .num_decoded_fmts = ARRAY_SIZE(rkvdec_hevc_decoded_fmts),
> + .decoded_fmts = rkvdec_hevc_decoded_fmts,
> + },
> {
> .fourcc = V4L2_PIX_FMT_H264_SLICE,
> .frmsize = {
> diff --git a/drivers/staging/media/rkvdec/rkvdec.h b/drivers/staging/media/rkvdec/rkvdec.h
> index d74821f9fd0b..9cf354968d52 100644
> --- a/drivers/staging/media/rkvdec/rkvdec.h
> +++ b/drivers/staging/media/rkvdec/rkvdec.h
> @@ -135,6 +135,7 @@ void rkvdec_run_preamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
> void rkvdec_run_postamble(struct rkvdec_ctx *ctx, struct rkvdec_run *run);
>
> extern const struct rkvdec_coded_fmt_ops rkvdec_h264_fmt_ops;
> +extern const struct rkvdec_coded_fmt_ops rkvdec_hevc_fmt_ops;
> extern const struct rkvdec_coded_fmt_ops rkvdec_vp9_fmt_ops;
>
> #endif /* RKVDEC_H_ */
>

2023-02-16 08:58:11

by Hsia-Jun Li

[permalink] [raw]
Subject: Re: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format



On 1/12/23 20:56, Sebastian Fricke wrote:
> CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> From: Jonas Karlman <[email protected]>
>
> Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers.
>
I think this pixel format in the Rockchip platform supports multiple
planes buffers. It is all right not to add more variant until the ext
pixel format and buffer APIs are merged.

I just want to mention the need of this.
> NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no
> padding between components. Instead, luminance and chrominance samples are grouped
> into 4s so that each group is packed into an integer number of bytes:
>
> YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
>
> The '15' suffix refers to the optimum effective bits per pixel
> which is achieved when the total number of luminance samples is a multiple
> of 8 for NV15.
>
> Signed-off-by: Jonas Karlman <[email protected]>
> Signed-off-by: Sebastian Fricke <[email protected]>
> ---
> .../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 ++++++++++++++++++++++
> drivers/media/v4l2-core/v4l2-common.c | 2 +
> drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
> include/uapi/linux/videodev2.h | 1 +
> 4 files changed, 79 insertions(+)
>
> diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> index f1d5bb7b806d..7d8d228f8063 100644
> --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> @@ -79,6 +79,13 @@ All components are stored with the same number of bits per component.
> - Cr, Cb
> - Yes
> - Linear
> + * - V4L2_PIX_FMT_NV15
> + - 'NV15'
> + - 15
> + - 4:2:0
> + - Cb, Cr
> + - Yes
> + - Linear
> * - V4L2_PIX_FMT_NV12M
> - 'NM12'
> - 8
> @@ -183,6 +190,7 @@ horizontally.
>
> .. _V4L2-PIX-FMT-NV12:
> .. _V4L2-PIX-FMT-NV21:
> +.. _V4L2-PIX-FMT-NV15:
> .. _V4L2-PIX-FMT-NV12M:
> .. _V4L2-PIX-FMT-NV21M:
> .. _V4L2-PIX-FMT-P010:
> @@ -586,6 +594,73 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord
> - Cb\ :sub:`11`
> - Cr\ :sub:`11`
>
> +.. _V4L2_PIX_FMT_NV15:
> +
> +NV15
> +----
> +
> +Similar to P010, a semi-planar 10-bit Y/CbCr format, but all components are
> +packed without any padding between each other. As a side-effect, each group of
> +4 components are stored over 5 bytes (YYYY or UVUV = 4 * 10 bits = 40 bits = 5
> +bytes).
> +
> +.. flat-table:: Sample 4x4 NV15 Image
> + :header-rows: 0
> + :stub-columns: 0
> +
> + * - start + 0:
> + - Y'\ :sub:`00`
> + - Y'\ :sub:`01`
> + - Y'\ :sub:`02`
> + - Y'\ :sub:`03`
> + * - start + 8:
> + - Y'\ :sub:`04`
> + - Y'\ :sub:`10`
> + - Y'\ :sub:`11`
> + - Y'\ :sub:`12`
> + * - start + 16:
> + - Y'\ :sub:`13`
> + - Y'\ :sub:`14`
> + - Y'\ :sub:`20`
> + - Y'\ :sub:`21`
> + * - start + 24:
> + - Y'\ :sub:`22`
> + - Y'\ :sub:`23`
> + - Y'\ :sub:`24`
> + - Y'\ :sub:`30`
> + * - start + 32:
> + - Y'\ :sub:`31`
> + - Y'\ :sub:`32`
> + - Y'\ :sub:`33`
> + - Y'\ :sub:`34`
> +
> + * - start + 0:
> + - Cb\ :sub:`00`
> + - Cr\ :sub:`00`
> + - Cb\ :sub:`01`
> + - Cr\ :sub:`01`
> + * - start + 8:
> + - Cb\ :sub:`02`
> + - Cr\ :sub:`02`
> + - Cb\ :sub:`03`
> + - Cr\ :sub:`03`
> + * - start + 16:
> + - Cb\ :sub:`04`
> + - Cr\ :sub:`04`
> + - Cb\ :sub:`10`
> + - Cr\ :sub:`10`
> + * - start + 24:
> + - Cb\ :sub:`11`
> + - Cr\ :sub:`11`
> + - Cb\ :sub:`12`
> + - Cr\ :sub:`12`
> + * - start + 32:
> + - Cb\ :sub:`13`
> + - Cr\ :sub:`13`
> + - Cb\ :sub:`14`
> + - Cr\ :sub:`14`
> +
> +.. raw:: latex
>
> Fully Planar YUV Formats
> ========================
> diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
> index 40f56e044640..be23e319fb3a 100644
> --- a/drivers/media/v4l2-core/v4l2-common.c
> +++ b/drivers/media/v4l2-core/v4l2-common.c
> @@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
> /* YUV planar formats */
> { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
> { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
> + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2,
> + .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
> { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
> { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
> { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
> diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
> index 8e0a0ff62a70..1c80ad78ef00 100644
> --- a/drivers/media/v4l2-core/v4l2-ioctl.c
> +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
> @@ -1343,6 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
> case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
> case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
> case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
> + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
> case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
> case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
> case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> index 1befd181a4cc..e9731286dc77 100644
> --- a/include/uapi/linux/videodev2.h
> +++ b/include/uapi/linux/videodev2.h
> @@ -621,6 +621,7 @@ struct v4l2_pix_format {
> /* two planes -- one Y, one Cr + Cb interleaved */
> #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
> #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
> +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
> #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
> #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
> #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
>
> --
> 2.25.1

--
Hsia-Jun(Randy) Li

2023-02-16 17:00:27

by Nicolas Dufresne

[permalink] [raw]
Subject: Re: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format

Le jeudi 16 février 2023 à 16:57 +0800, Hsia-Jun Li a écrit :
>
> On 1/12/23 20:56, Sebastian Fricke wrote:
> > CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe.
> >
> >
> > From: Jonas Karlman <[email protected]>
> >
> > Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers.
> >
> I think this pixel format in the Rockchip platform supports multiple
> planes buffers. It is all right not to add more variant until the ext
> pixel format and buffer APIs are merged.
>
> I just want to mention the need of this.

Can you extend, I don't see that support in rkvdec driver (nor in mpp).

/* config output base address */
dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);

reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);

reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);

That looks like a base address and 2 strides only. For NV15M (multiple
allocation) you'd need 2 addresses. It could be that RGA or newer chip have that
support, but as you know, we add formats only when actually using them.

regards,
Nicolas

> > NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no
> > padding between components. Instead, luminance and chrominance samples are grouped
> > into 4s so that each group is packed into an integer number of bytes:
> >
> > YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
> >
> > The '15' suffix refers to the optimum effective bits per pixel
> > which is achieved when the total number of luminance samples is a multiple
> > of 8 for NV15.
> >
> > Signed-off-by: Jonas Karlman <[email protected]>
> > Signed-off-by: Sebastian Fricke <[email protected]>
> > ---
> > .../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 ++++++++++++++++++++++
> > drivers/media/v4l2-core/v4l2-common.c | 2 +
> > drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
> > include/uapi/linux/videodev2.h | 1 +
> > 4 files changed, 79 insertions(+)
> >
> > diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> > index f1d5bb7b806d..7d8d228f8063 100644
> > --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> > +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
> > @@ -79,6 +79,13 @@ All components are stored with the same number of bits per component.
> > - Cr, Cb
> > - Yes
> > - Linear
> > + * - V4L2_PIX_FMT_NV15
> > + - 'NV15'
> > + - 15
> > + - 4:2:0
> > + - Cb, Cr
> > + - Yes
> > + - Linear
> > * - V4L2_PIX_FMT_NV12M
> > - 'NM12'
> > - 8
> > @@ -183,6 +190,7 @@ horizontally.
> >
> > .. _V4L2-PIX-FMT-NV12:
> > .. _V4L2-PIX-FMT-NV21:
> > +.. _V4L2-PIX-FMT-NV15:
> > .. _V4L2-PIX-FMT-NV12M:
> > .. _V4L2-PIX-FMT-NV21M:
> > .. _V4L2-PIX-FMT-P010:
> > @@ -586,6 +594,73 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord
> > - Cb\ :sub:`11`
> > - Cr\ :sub:`11`
> >
> > +.. _V4L2_PIX_FMT_NV15:
> > +
> > +NV15
> > +----
> > +
> > +Similar to P010, a semi-planar 10-bit Y/CbCr format, but all components are
> > +packed without any padding between each other. As a side-effect, each group of
> > +4 components are stored over 5 bytes (YYYY or UVUV = 4 * 10 bits = 40 bits = 5
> > +bytes).
> > +
> > +.. flat-table:: Sample 4x4 NV15 Image
> > + :header-rows: 0
> > + :stub-columns: 0
> > +
> > + * - start + 0:
> > + - Y'\ :sub:`00`
> > + - Y'\ :sub:`01`
> > + - Y'\ :sub:`02`
> > + - Y'\ :sub:`03`
> > + * - start + 8:
> > + - Y'\ :sub:`04`
> > + - Y'\ :sub:`10`
> > + - Y'\ :sub:`11`
> > + - Y'\ :sub:`12`
> > + * - start + 16:
> > + - Y'\ :sub:`13`
> > + - Y'\ :sub:`14`
> > + - Y'\ :sub:`20`
> > + - Y'\ :sub:`21`
> > + * - start + 24:
> > + - Y'\ :sub:`22`
> > + - Y'\ :sub:`23`
> > + - Y'\ :sub:`24`
> > + - Y'\ :sub:`30`
> > + * - start + 32:
> > + - Y'\ :sub:`31`
> > + - Y'\ :sub:`32`
> > + - Y'\ :sub:`33`
> > + - Y'\ :sub:`34`
> > +
> > + * - start + 0:
> > + - Cb\ :sub:`00`
> > + - Cr\ :sub:`00`
> > + - Cb\ :sub:`01`
> > + - Cr\ :sub:`01`
> > + * - start + 8:
> > + - Cb\ :sub:`02`
> > + - Cr\ :sub:`02`
> > + - Cb\ :sub:`03`
> > + - Cr\ :sub:`03`
> > + * - start + 16:
> > + - Cb\ :sub:`04`
> > + - Cr\ :sub:`04`
> > + - Cb\ :sub:`10`
> > + - Cr\ :sub:`10`
> > + * - start + 24:
> > + - Cb\ :sub:`11`
> > + - Cr\ :sub:`11`
> > + - Cb\ :sub:`12`
> > + - Cr\ :sub:`12`
> > + * - start + 32:
> > + - Cb\ :sub:`13`
> > + - Cr\ :sub:`13`
> > + - Cb\ :sub:`14`
> > + - Cr\ :sub:`14`
> > +
> > +.. raw:: latex
> >
> > Fully Planar YUV Formats
> > ========================
> > diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
> > index 40f56e044640..be23e319fb3a 100644
> > --- a/drivers/media/v4l2-core/v4l2-common.c
> > +++ b/drivers/media/v4l2-core/v4l2-common.c
> > @@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
> > /* YUV planar formats */
> > { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
> > { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
> > + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2,
> > + .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
> > { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
> > { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
> > { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
> > diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
> > index 8e0a0ff62a70..1c80ad78ef00 100644
> > --- a/drivers/media/v4l2-core/v4l2-ioctl.c
> > +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
> > @@ -1343,6 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
> > case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
> > case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
> > case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
> > + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
> > case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
> > case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
> > case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
> > diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
> > index 1befd181a4cc..e9731286dc77 100644
> > --- a/include/uapi/linux/videodev2.h
> > +++ b/include/uapi/linux/videodev2.h
> > @@ -621,6 +621,7 @@ struct v4l2_pix_format {
> > /* two planes -- one Y, one Cr + Cb interleaved */
> > #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
> > #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
> > +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
> > #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
> > #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
> > #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
> >
> > --
> > 2.25.1
>


2023-02-17 02:41:14

by Hsia-Jun Li

[permalink] [raw]
Subject: Re: [PATCH v2 01/12] media: v4l2: Add NV15 pixel format



On 2/17/23 01:00, Nicolas Dufresne wrote:
> CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> Le jeudi 16 février 2023 à 16:57 +0800, Hsia-Jun Li a écrit :
>>
>> On 1/12/23 20:56, Sebastian Fricke wrote:
>>> CAUTION: Email originated externally, do not click links or open attachments unless you recognize the sender and know the content is safe.
>>>
>>>
>>> From: Jonas Karlman <[email protected]>
>>>
>>> Add the NV15 pixel format used by the Rockchip Video Decoder for 10-bit buffers.
>>>
>> I think this pixel format in the Rockchip platform supports multiple
>> planes buffers. It is all right not to add more variant until the ext
>> pixel format and buffer APIs are merged.
>>
>> I just want to mention the need of this.
>
> Can you extend, I don't see that support in rkvdec driver (nor in mpp).
>
> /* config output base address */
> dst_addr = vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
> writel_relaxed(dst_addr, rkvdec->regs + RKVDEC_REG_DECOUT_BASE);
>
> reg = RKVDEC_Y_VIRSTRIDE(y_virstride / 16);
> writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_Y_VIRSTRIDE);
>
> reg = RKVDEC_YUV_VIRSTRIDE(yuv_virstride / 16);
> writel_relaxed(reg, rkvdec->regs + RKVDEC_REG_YUV_VIRSTRIDE);
>
> That looks like a base address and 2 strides only. For NV15M (multiple
I think the rockchip drm does
VOP_WIN_SET(vop, win, uv_vir, DIV_ROUND_UP(fb->pitches[1], 4));
VOP_WIN_SET(vop, win, uv_mst, dma_addr);

vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);

> allocation) you'd need 2 addresses. It could be that RGA or newer chip have that
> support, but as you know, we add formats only when actually using them.
From the public info, it is not just rockchip but also NXP and xilinx
support this 10bits format. I am not sure whether they would support that.

Besides, I think the rockchip decoder needs some spare space between its
Y plane and UV plane. It would be hard to present such thing with the
single plane format unless you want to get the wrong start address of
the chroma plane.
>
> regards,
> Nicolas
>
>>> NV15 is a packed 10-bit 4:2:0 Y/CbCr format similar to P010 and P210 but has no
>>> padding between components. Instead, luminance and chrominance samples are grouped
>>> into 4s so that each group is packed into an integer number of bytes:
>>>
>>> YYYY = UVUV = 4 * 10 bits = 40 bits = 5 bytes
>>>
>>> The '15' suffix refers to the optimum effective bits per pixel
>>> which is achieved when the total number of luminance samples is a multiple
>>> of 8 for NV15.
>>>
>>> Signed-off-by: Jonas Karlman <[email protected]>
>>> Signed-off-by: Sebastian Fricke <[email protected]>
>>> ---
>>> .../userspace-api/media/v4l/pixfmt-yuv-planar.rst | 75 ++++++++++++++++++++++
>>> drivers/media/v4l2-core/v4l2-common.c | 2 +
>>> drivers/media/v4l2-core/v4l2-ioctl.c | 1 +
>>> include/uapi/linux/videodev2.h | 1 +
>>> 4 files changed, 79 insertions(+)
>>>
>>> diff --git a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
>>> index f1d5bb7b806d..7d8d228f8063 100644
>>> --- a/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
>>> +++ b/Documentation/userspace-api/media/v4l/pixfmt-yuv-planar.rst
>>> @@ -79,6 +79,13 @@ All components are stored with the same number of bits per component.
>>> - Cr, Cb
>>> - Yes
>>> - Linear
>>> + * - V4L2_PIX_FMT_NV15
>>> + - 'NV15'
>>> + - 15
>>> + - 4:2:0
>>> + - Cb, Cr
>>> + - Yes
>>> + - Linear
>>> * - V4L2_PIX_FMT_NV12M
>>> - 'NM12'
>>> - 8
>>> @@ -183,6 +190,7 @@ horizontally.
>>>
>>> .. _V4L2-PIX-FMT-NV12:
>>> .. _V4L2-PIX-FMT-NV21:
>>> +.. _V4L2-PIX-FMT-NV15:
>>> .. _V4L2-PIX-FMT-NV12M:
>>> .. _V4L2-PIX-FMT-NV21M:
>>> .. _V4L2-PIX-FMT-P010:
>>> @@ -586,6 +594,73 @@ Data in the 10 high bits, zeros in the 6 low bits, arranged in little endian ord
>>> - Cb\ :sub:`11`
>>> - Cr\ :sub:`11`
>>>
>>> +.. _V4L2_PIX_FMT_NV15:
>>> +
>>> +NV15
>>> +----
>>> +
>>> +Similar to P010, a semi-planar 10-bit Y/CbCr format, but all components are
>>> +packed without any padding between each other. As a side-effect, each group of
>>> +4 components are stored over 5 bytes (YYYY or UVUV = 4 * 10 bits = 40 bits = 5
>>> +bytes).
>>> +
>>> +.. flat-table:: Sample 4x4 NV15 Image
>>> + :header-rows: 0
>>> + :stub-columns: 0
>>> +
>>> + * - start + 0:
>>> + - Y'\ :sub:`00`
>>> + - Y'\ :sub:`01`
>>> + - Y'\ :sub:`02`
>>> + - Y'\ :sub:`03`
>>> + * - start + 8:
>>> + - Y'\ :sub:`04`
>>> + - Y'\ :sub:`10`
>>> + - Y'\ :sub:`11`
>>> + - Y'\ :sub:`12`
>>> + * - start + 16:
>>> + - Y'\ :sub:`13`
>>> + - Y'\ :sub:`14`
>>> + - Y'\ :sub:`20`
>>> + - Y'\ :sub:`21`
>>> + * - start + 24:
>>> + - Y'\ :sub:`22`
>>> + - Y'\ :sub:`23`
>>> + - Y'\ :sub:`24`
>>> + - Y'\ :sub:`30`
>>> + * - start + 32:
>>> + - Y'\ :sub:`31`
>>> + - Y'\ :sub:`32`
>>> + - Y'\ :sub:`33`
>>> + - Y'\ :sub:`34`
>>> +
>>> + * - start + 0:
>>> + - Cb\ :sub:`00`
>>> + - Cr\ :sub:`00`
>>> + - Cb\ :sub:`01`
>>> + - Cr\ :sub:`01`
>>> + * - start + 8:
>>> + - Cb\ :sub:`02`
>>> + - Cr\ :sub:`02`
>>> + - Cb\ :sub:`03`
>>> + - Cr\ :sub:`03`
>>> + * - start + 16:
>>> + - Cb\ :sub:`04`
>>> + - Cr\ :sub:`04`
>>> + - Cb\ :sub:`10`
>>> + - Cr\ :sub:`10`
>>> + * - start + 24:
>>> + - Cb\ :sub:`11`
>>> + - Cr\ :sub:`11`
>>> + - Cb\ :sub:`12`
>>> + - Cr\ :sub:`12`
>>> + * - start + 32:
>>> + - Cb\ :sub:`13`
>>> + - Cr\ :sub:`13`
>>> + - Cb\ :sub:`14`
>>> + - Cr\ :sub:`14`
>>> +
>>> +.. raw:: latex
>>>
>>> Fully Planar YUV Formats
>>> ========================
>>> diff --git a/drivers/media/v4l2-core/v4l2-common.c b/drivers/media/v4l2-core/v4l2-common.c
>>> index 40f56e044640..be23e319fb3a 100644
>>> --- a/drivers/media/v4l2-core/v4l2-common.c
>>> +++ b/drivers/media/v4l2-core/v4l2-common.c
>>> @@ -262,6 +262,8 @@ const struct v4l2_format_info *v4l2_format_info(u32 format)
>>> /* YUV planar formats */
>>> { .format = V4L2_PIX_FMT_NV12, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
>>> { .format = V4L2_PIX_FMT_NV21, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 2 },
>>> + { .format = V4L2_PIX_FMT_NV15, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 5, 5, 0, 0 }, .hdiv = 2, .vdiv = 2,
>>> + .block_w = { 4, 2, 0, 0 }, .block_h = { 1, 1, 0, 0 } },
>>> { .format = V4L2_PIX_FMT_NV16, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
>>> { .format = V4L2_PIX_FMT_NV61, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 2, .vdiv = 1 },
>>> { .format = V4L2_PIX_FMT_NV24, .pixel_enc = V4L2_PIXEL_ENC_YUV, .mem_planes = 1, .comp_planes = 2, .bpp = { 1, 2, 0, 0 }, .hdiv = 1, .vdiv = 1 },
>>> diff --git a/drivers/media/v4l2-core/v4l2-ioctl.c b/drivers/media/v4l2-core/v4l2-ioctl.c
>>> index 8e0a0ff62a70..1c80ad78ef00 100644
>>> --- a/drivers/media/v4l2-core/v4l2-ioctl.c
>>> +++ b/drivers/media/v4l2-core/v4l2-ioctl.c
>>> @@ -1343,6 +1343,7 @@ static void v4l_fill_fmtdesc(struct v4l2_fmtdesc *fmt)
>>> case V4L2_PIX_FMT_M420: descr = "YUV 4:2:0 (M420)"; break;
>>> case V4L2_PIX_FMT_NV12: descr = "Y/UV 4:2:0"; break;
>>> case V4L2_PIX_FMT_NV21: descr = "Y/VU 4:2:0"; break;
>>> + case V4L2_PIX_FMT_NV15: descr = "10-bit Y/UV 4:2:0 (Packed)"; break;
>>> case V4L2_PIX_FMT_NV16: descr = "Y/UV 4:2:2"; break;
>>> case V4L2_PIX_FMT_NV61: descr = "Y/VU 4:2:2"; break;
>>> case V4L2_PIX_FMT_NV24: descr = "Y/UV 4:4:4"; break;
>>> diff --git a/include/uapi/linux/videodev2.h b/include/uapi/linux/videodev2.h
>>> index 1befd181a4cc..e9731286dc77 100644
>>> --- a/include/uapi/linux/videodev2.h
>>> +++ b/include/uapi/linux/videodev2.h
>>> @@ -621,6 +621,7 @@ struct v4l2_pix_format {
>>> /* two planes -- one Y, one Cr + Cb interleaved */
>>> #define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
>>> #define V4L2_PIX_FMT_NV21 v4l2_fourcc('N', 'V', '2', '1') /* 12 Y/CrCb 4:2:0 */
>>> +#define V4L2_PIX_FMT_NV15 v4l2_fourcc('N', 'V', '1', '5') /* 15 Y/CbCr 4:2:0 10-bit packed */
>>> #define V4L2_PIX_FMT_NV16 v4l2_fourcc('N', 'V', '1', '6') /* 16 Y/CbCr 4:2:2 */
>>> #define V4L2_PIX_FMT_NV61 v4l2_fourcc('N', 'V', '6', '1') /* 16 Y/CrCb 4:2:2 */
>>> #define V4L2_PIX_FMT_NV24 v4l2_fourcc('N', 'V', '2', '4') /* 24 Y/CbCr 4:4:4 */
>>>
>>> --
>>> 2.25.1
>>
>

--
Hsia-Jun(Randy) Li