Hi, Chunfeng:
Chunfeng Yun <[email protected]> 於 2020年12月16日 週三 下午5:30寫道：
>
> Convert MIPI DSI PHY binding to YAML schema mediatek,dsi-phy.yaml
>
Reviewed-by: Chun-Kuang Hu <[email protected]>
> Cc: Chun-Kuang Hu <[email protected]>
> Cc: Philipp Zabel <[email protected]>
> Signed-off-by: Chunfeng Yun <[email protected]>
> ---
> v4:
> 1. add maintainer Philipp add support mt8183 suggested by Chun-Kuang
> 2. use keyword multipleOf suggested by Rob
> 3. fix typo of 'MIPI' in title
>
> v3: new patch
> ---
> .../display/mediatek/mediatek,dsi.txt | 18 +---
> .../bindings/phy/mediatek,dsi-phy.yaml | 85 +++++++++++++++++++
> 2 files changed, 86 insertions(+), 17 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> index f06f24d405a5..8238a86686be 100644
> --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dsi.txt
> @@ -22,23 +22,7 @@ Required properties:
> MIPI TX Configuration Module
> ============================
>
> -The MIPI TX configuration module controls the MIPI D-PHY.
> -
> -Required properties:
> -- compatible: "mediatek,<chip>-mipi-tx"
> -- the supported chips are mt2701, 7623, mt8173 and mt8183.
> -- reg: Physical base address and length of the controller's registers
> -- clocks: PLL reference clock
> -- clock-output-names: name of the output clock line to the DSI encoder
> -- #clock-cells: must be <0>;
> -- #phy-cells: must be <0>.
> -
> -Optional properties:
> -- drive-strength-microamp: adjust driving current, should be 3000 ~ 6000. And
> - the step is 200.
> -- nvmem-cells: A phandle to the calibration data provided by a nvmem device. If
> - unspecified default values shall be used.
> -- nvmem-cell-names: Should be "calibration-data"
> +See phy/mediatek,dsi-phy.yaml
>
> Example:
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
> new file mode 100644
> index 000000000000..71d4acea1f66
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/mediatek,dsi-phy.yaml
> @@ -0,0 +1,85 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +# Copyright (c) 2020 MediaTek
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/mediatek,dsi-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek MIPI Display Serial Interface (DSI) PHY binding
> +
> +maintainers:
> + - Chun-Kuang Hu <[email protected]>
> + - Philipp Zabel <[email protected]>
> + - Chunfeng Yun <[email protected]>
> +
> +description: The MIPI DSI PHY supports up to 4-lane output.
> +
> +properties:
> + $nodename:
> + pattern: "^dsi-phy@[0-9a-f]+$"
> +
> + compatible:
> + enum:
> + - mediatek,mt2701-mipi-tx
> + - mediatek,mt7623-mipi-tx
> + - mediatek,mt8173-mipi-tx
> + - mediatek,mt8183-mipi-tx
> +
> + reg:
> + maxItems: 1
> +
> + clocks:
> + items:
> + - description: PLL reference clock
> +
> + clock-output-names:
> + maxItems: 1
> +
> + "#phy-cells":
> + const: 0
> +
> + "#clock-cells":
> + const: 0
> +
> + nvmem-cells:
> + maxItems: 1
> + description: A phandle to the calibration data provided by a nvmem device,
> + if unspecified, default values shall be used.
> +
> + nvmem-cell-names:
> + items:
> + - const: calibration-data
> +
> + drive-strength-microamp:
> + description: adjust driving current
> + multipleOf: 200
> + minimum: 2000
> + maximum: 6000
> + default: 4600
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-output-names
> + - "#phy-cells"
> + - "#clock-cells"
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8173-clk.h>
> + dsi-phy@10215000 {
> + compatible = "mediatek,mt8173-mipi-tx";
> + reg = <0x10215000 0x1000>;
> + clocks = <&clk26m>;
> + clock-output-names = "mipi_tx0_pll";
> + drive-strength-microamp = <4000>;
> + nvmem-cells= <&mipi_tx_calibration>;
> + nvmem-cell-names = "calibration-data";
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + };
> +
> +...
> --
> 2.18.0
>