2021-06-15 17:35:41

by Tinghan Shen

Subject: [PATCH 23/27] arm64: dts: mt8195: add gce node

From: Jason-JH Lin <[email protected]>

add gce node on dts file.

Signed-off-by: Jason-JH Lin <[email protected]>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index d7d2c2a8f461..51edb8ee35a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -7,6 +7,7 @@
/dts-v1/;

#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
@@ -1075,6 +1076,26 @@
#clock-cells = <1>;
};

+ gce0: mdp_mailbox@10320000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+ <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ clock-names = "gce0", "gce1";
+ };
+
+ gce1: disp_mailbox@10330000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <3>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
+ <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ clock-names = "gce0", "gce1";
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
reg = <0 0x11001100 0 0x100>;
--
2.18.0

2021-06-18 17:38:23

by Chun-Kuang Hu

Subject: Re: [PATCH 23/27] arm64: dts: mt8195: add gce node

Hi, Tinghan:

Tinghan Shen <[email protected]> 於 2021年6月16日 週三 上午5:35寫道：
>
> From: Jason-JH Lin <[email protected]>
>
> add gce node on dts file.
>
> Signed-off-by: Jason-JH Lin <[email protected]>
> ---
> arch/arm64/boot/dts/mediatek/mt8195.dtsi | 21 +++++++++++++++++++++
> 1 file changed, 21 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> index d7d2c2a8f461..51edb8ee35a8 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
> @@ -7,6 +7,7 @@
> /dts-v1/;
>
> #include <dt-bindings/clock/mt8195-clk.h>
> +#include <dt-bindings/gce/mt8195-gce.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/memory/mt8195-memory-port.h>
> @@ -1075,6 +1076,26 @@
> #clock-cells = <1>;
> };
>
> + gce0: mdp_mailbox@10320000 {
> + compatible = "mediatek,mt8195-gce";

Where is the definition of this compatible?

> + reg = <0 0x10320000 0 0x4000>;
> + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <3>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> + clock-names = "gce0", "gce1";

According to the binding document [1], clock-names should be "gce".

[1] https://www.kernel.org/doc/Documentation/devicetree/bindings/mailbox/mtk-gce.txt

Regards,
Chun-Kuang.

> + };
> +
> + gce1: disp_mailbox@10330000 {
> + compatible = "mediatek,mt8195-gce";
> + reg = <0 0x10330000 0 0x4000>;
> + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <3>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>,
> + <&infracfg_ao CLK_INFRA_AO_GCE2>;
> + clock-names = "gce0", "gce1";
> + };
> +
> uart0: serial@11001100 {
> compatible = "mediatek,mt8195-uart", "mediatek,mt6577-uart";
> reg = <0 0x11001100 0 0x100>;
> --
> 2.18.0
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