In all MediaTek PLL design, bit0 of CON0 register is always
the enable bit.
However, there's a special case of usbpll on MT8192.
The enable bit of usbpll is moved to bit2 of other register.
Add configurable en_reg and pll_en_bit for enable control or
default 0 where pll data are static variables.
Hence, CON0_BASE_EN could also be removed.
And there might have another special case on other chips,
the enable bit is still on CON0 register but not at bit0.
Signed-off-by: Weiyi Lu <[email protected]>
---
drivers/clk/mediatek/clk-mtk.h | 2 ++
drivers/clk/mediatek/clk-pll.c | 15 ++++++++++-----
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index c3d6756..c580663 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -233,6 +233,8 @@ struct mtk_pll_data {
uint32_t pcw_chg_reg;
const struct mtk_pll_div_table *div_table;
const char *parent_name;
+ uint32_t en_reg;
+ uint8_t pll_en_bit; /* Assume 0, indicates BIT(0) by default */
};
void mtk_clk_register_plls(struct device_node *node,
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index 11ed5d1..7fb001a 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -44,6 +44,7 @@ struct mtk_clk_pll {
void __iomem *tuner_en_addr;
void __iomem *pcw_addr;
void __iomem *pcw_chg_addr;
+ void __iomem *en_addr;
const struct mtk_pll_data *data;
};
@@ -56,7 +57,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
- return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
+ return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
}
static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
@@ -248,8 +249,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
writel(r, pll->pwr_addr);
udelay(1);
- r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
- writel(r, pll->base_addr + REG_CON0);
+ r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
+ writel(r, pll->en_addr);
div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
if (div_en_mask) {
@@ -290,8 +291,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
writel(r, pll->base_addr + REG_CON0);
}
- r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;
- writel(r, pll->base_addr + REG_CON0);
+ r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
+ writel(r, pll->en_addr);
r = readl(pll->pwr_addr) | CON0_ISO_EN;
writel(r, pll->pwr_addr);
@@ -333,6 +334,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
pll->tuner_addr = base + data->tuner_reg;
if (data->tuner_en_reg)
pll->tuner_en_addr = base + data->tuner_en_reg;
+ if (data->en_reg)
+ pll->en_addr = base + data->en_reg;
+ else
+ pll->en_addr = pll->base_addr + REG_CON0;
pll->hw.init = &init;
pll->data = data;
--
1.8.1.1.dirty
On Tue, Dec 22, 2020 at 9:11 PM Weiyi Lu <[email protected]> wrote:
>
> In all MediaTek PLL design, bit0 of CON0 register is always
> the enable bit.
> However, there's a special case of usbpll on MT8192.
> The enable bit of usbpll is moved to bit2 of other register.
> Add configurable en_reg and pll_en_bit for enable control or
> default 0 where pll data are static variables.
> Hence, CON0_BASE_EN could also be removed.
> And there might have another special case on other chips,
> the enable bit is still on CON0 register but not at bit0.
>
> Signed-off-by: Weiyi Lu <[email protected]>
Reviewed-by: Ikjoon Jang <[email protected]>
> ---
> drivers/clk/mediatek/clk-mtk.h | 2 ++
> drivers/clk/mediatek/clk-pll.c | 15 ++++++++++-----
> 2 files changed, 12 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> index c3d6756..c580663 100644
> --- a/drivers/clk/mediatek/clk-mtk.h
> +++ b/drivers/clk/mediatek/clk-mtk.h
> @@ -233,6 +233,8 @@ struct mtk_pll_data {
> uint32_t pcw_chg_reg;
> const struct mtk_pll_div_table *div_table;
> const char *parent_name;
> + uint32_t en_reg;
> + uint8_t pll_en_bit; /* Assume 0, indicates BIT(0) by default */
> };
>
> void mtk_clk_register_plls(struct device_node *node,
> diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
> index 11ed5d1..7fb001a 100644
> --- a/drivers/clk/mediatek/clk-pll.c
> +++ b/drivers/clk/mediatek/clk-pll.c
> @@ -44,6 +44,7 @@ struct mtk_clk_pll {
> void __iomem *tuner_en_addr;
> void __iomem *pcw_addr;
> void __iomem *pcw_chg_addr;
> + void __iomem *en_addr;
> const struct mtk_pll_data *data;
> };
>
> @@ -56,7 +57,7 @@ static int mtk_pll_is_prepared(struct clk_hw *hw)
> {
> struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
>
> - return (readl(pll->base_addr + REG_CON0) & CON0_BASE_EN) != 0;
> + return (readl(pll->en_addr) & BIT(pll->data->pll_en_bit)) != 0;
> }
>
> static unsigned long __mtk_pll_recalc_rate(struct mtk_clk_pll *pll, u32 fin,
> @@ -248,8 +249,8 @@ static int mtk_pll_prepare(struct clk_hw *hw)
> writel(r, pll->pwr_addr);
> udelay(1);
>
> - r = readl(pll->base_addr + REG_CON0) | CON0_BASE_EN;
> - writel(r, pll->base_addr + REG_CON0);
> + r = readl(pll->en_addr) | BIT(pll->data->pll_en_bit);
> + writel(r, pll->en_addr);
>
> div_en_mask = pll->data->en_mask & ~CON0_BASE_EN;
> if (div_en_mask) {
> @@ -290,8 +291,8 @@ static void mtk_pll_unprepare(struct clk_hw *hw)
> writel(r, pll->base_addr + REG_CON0);
> }
>
> - r = readl(pll->base_addr + REG_CON0) & ~CON0_BASE_EN;
> - writel(r, pll->base_addr + REG_CON0);
> + r = readl(pll->en_addr) & ~BIT(pll->data->pll_en_bit);
> + writel(r, pll->en_addr);
>
> r = readl(pll->pwr_addr) | CON0_ISO_EN;
> writel(r, pll->pwr_addr);
> @@ -333,6 +334,10 @@ static struct clk *mtk_clk_register_pll(const struct mtk_pll_data *data,
> pll->tuner_addr = base + data->tuner_reg;
> if (data->tuner_en_reg)
> pll->tuner_en_addr = base + data->tuner_en_reg;
> + if (data->en_reg)
> + pll->en_addr = base + data->en_reg;
> + else
> + pll->en_addr = pll->base_addr + REG_CON0;
> pll->hw.init = &init;
> pll->data = data;
>
> --
> 1.8.1.1.dirty
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