2023-05-07 16:16:58

by David Yang

[permalink] [raw]
Subject: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100

Hisilicon also uses phy-hisi-inno-usb2 on Hi3798MV100, with a slightly
different register convention.

Signed-off-by: David Yang <[email protected]>
---
drivers/phy/hisilicon/Kconfig | 2 +-
drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 67 ++++++++++++++++------
2 files changed, 51 insertions(+), 18 deletions(-)

diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
index d3b92c288554..6c89136fc8c2 100644
--- a/drivers/phy/hisilicon/Kconfig
+++ b/drivers/phy/hisilicon/Kconfig
@@ -54,7 +54,7 @@ config PHY_HISTB_COMBPHY

config PHY_HISI_INNO_USB2
tristate "HiSilicon INNO USB2 PHY support"
- depends on (ARCH_HISI && ARM64) || COMPILE_TEST
+ depends on ARCH_HISI || COMPILE_TEST
select GENERIC_PHY
select MFD_SYSCON
help
diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
index b133ae06757a..b5d006f38934 100644
--- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
+++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
@@ -9,7 +9,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/module.h>
-#include <linux/platform_device.h>
+#include <linux/of_device.h>
#include <linux/phy/phy.h>
#include <linux/reset.h>

@@ -20,12 +20,28 @@
#define PHY_CLK_STABLE_TIME 2 /* unit:ms */
#define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
#define POR_RST_COMPLETE_TIME 300 /* unit:us */
-#define PHY_TEST_DATA GENMASK(7, 0)
-#define PHY_TEST_ADDR GENMASK(15, 8)
-#define PHY_TEST_PORT GENMASK(18, 16)
-#define PHY_TEST_WREN BIT(21)
-#define PHY_TEST_CLK BIT(22) /* rising edge active */
-#define PHY_TEST_RST BIT(23) /* low active */
+
+#define PHY_TYPE_0 0
+#define PHY_TYPE_1 1
+
+#define PHY0_TEST_DATA GENMASK(7, 0)
+#define PHY0_TEST_ADDR_OFFSET 8
+#define PHY0_TEST_ADDR GENMASK(15, 8)
+#define PHY0_TEST_PORT_OFFSET 16
+#define PHY0_TEST_PORT GENMASK(18, 16)
+#define PHY0_TEST_WREN BIT(21)
+#define PHY0_TEST_CLK BIT(22) /* rising edge active */
+#define PHY0_TEST_RST BIT(23) /* low active */
+
+#define PHY1_TEST_DATA GENMASK(7, 0)
+#define PHY1_TEST_ADDR_OFFSET 8
+#define PHY1_TEST_ADDR GENMASK(11, 8)
+#define PHY1_TEST_PORT_OFFSET 12
+#define PHY1_TEST_PORT BIT(12)
+#define PHY1_TEST_WREN BIT(13)
+#define PHY1_TEST_CLK BIT(14) /* rising edge active */
+#define PHY1_TEST_RST BIT(15) /* low active */
+
#define PHY_CLK_ENABLE BIT(2)

struct hisi_inno_phy_port {
@@ -37,6 +53,7 @@ struct hisi_inno_phy_priv {
void __iomem *mmio;
struct clk *ref_clk;
struct reset_control *por_rst;
+ unsigned int type;
struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
};

@@ -45,17 +62,27 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
{
void __iomem *reg = priv->mmio;
u32 val;
-
- val = (data & PHY_TEST_DATA) |
- ((addr << 8) & PHY_TEST_ADDR) |
- ((port << 16) & PHY_TEST_PORT) |
- PHY_TEST_WREN | PHY_TEST_RST;
+ u32 value;
+
+ if (priv->type == PHY_TYPE_0)
+ val = (data & PHY0_TEST_DATA) |
+ ((addr << PHY0_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) |
+ ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) |
+ PHY0_TEST_WREN | PHY0_TEST_RST;
+ else
+ val = (data & PHY1_TEST_DATA) |
+ ((addr << PHY1_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) |
+ ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) |
+ PHY1_TEST_WREN | PHY1_TEST_RST;
writel(val, reg);

- val |= PHY_TEST_CLK;
- writel(val, reg);
+ value = val;
+ if (priv->type == PHY_TYPE_0)
+ value |= PHY0_TEST_CLK;
+ else
+ value |= PHY1_TEST_CLK;
+ writel(value, reg);

- val &= ~PHY_TEST_CLK;
writel(val, reg);
}

@@ -135,6 +162,8 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
if (IS_ERR(priv->por_rst))
return PTR_ERR(priv->por_rst);

+ priv->type = (unsigned int) of_device_get_match_data(dev);
+
for_each_child_of_node(np, child) {
struct reset_control *rst;
struct phy *phy;
@@ -170,8 +199,12 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
}

static const struct of_device_id hisi_inno_phy_of_match[] = {
- { .compatible = "hisilicon,inno-usb2-phy", },
- { .compatible = "hisilicon,hi3798cv200-usb2-phy", },
+ { .compatible = "hisilicon,inno-usb2-phy",
+ .data = (void *) PHY_TYPE_0 },
+ { .compatible = "hisilicon,hi3798cv200-usb2-phy",
+ .data = (void *) PHY_TYPE_0 },
+ { .compatible = "hisilicon,hi3798mv100-usb2-phy",
+ .data = (void *) PHY_TYPE_1 },
{ },
};
MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
--
2.39.2


2023-05-07 17:03:45

by kernel test robot

[permalink] [raw]
Subject: Re: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100

Hi David,

kernel test robot noticed the following build warnings:

[auto build test WARNING on linus/master]
[also build test WARNING on v6.3 next-20230505]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/David-Yang/phy-hisilicon-Adopt-phy-hisi-inno-usb2-to-Hi3798MV100/20230507-234747
base: linus/master
patch link: https://lore.kernel.org/r/20230507154615.793942-1-mmyangfl%40gmail.com
patch subject: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100
config: arm64-buildonly-randconfig-r001-20230507 (https://download.01.org/0day-ci/archive/20230508/[email protected]/config)
compiler: aarch64-linux-gcc (GCC) 12.1.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/fe830916b152e401719061112b0b4fb140502d08
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review David-Yang/phy-hisilicon-Adopt-phy-hisi-inno-usb2-to-Hi3798MV100/20230507-234747
git checkout fe830916b152e401719061112b0b4fb140502d08
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-12.1.0 make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/phy/hisilicon/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <[email protected]>
| Link: https://lore.kernel.org/oe-kbuild-all/[email protected]/

All warnings (new ones prefixed by >>):

drivers/phy/hisilicon/phy-hisi-inno-usb2.c: In function 'hisi_inno_phy_probe':
>> drivers/phy/hisilicon/phy-hisi-inno-usb2.c:165:22: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
165 | priv->type = (unsigned int) of_device_get_match_data(dev);
| ^


vim +165 drivers/phy/hisilicon/phy-hisi-inno-usb2.c

136
137 static int hisi_inno_phy_probe(struct platform_device *pdev)
138 {
139 struct device *dev = &pdev->dev;
140 struct device_node *np = dev->of_node;
141 struct hisi_inno_phy_priv *priv;
142 struct phy_provider *provider;
143 struct device_node *child;
144 int i = 0;
145 int ret;
146
147 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
148 if (!priv)
149 return -ENOMEM;
150
151 priv->mmio = devm_platform_ioremap_resource(pdev, 0);
152 if (IS_ERR(priv->mmio)) {
153 ret = PTR_ERR(priv->mmio);
154 return ret;
155 }
156
157 priv->ref_clk = devm_clk_get(dev, NULL);
158 if (IS_ERR(priv->ref_clk))
159 return PTR_ERR(priv->ref_clk);
160
161 priv->por_rst = devm_reset_control_get_exclusive(dev, NULL);
162 if (IS_ERR(priv->por_rst))
163 return PTR_ERR(priv->por_rst);
164
> 165 priv->type = (unsigned int) of_device_get_match_data(dev);
166
167 for_each_child_of_node(np, child) {
168 struct reset_control *rst;
169 struct phy *phy;
170
171 rst = of_reset_control_get_exclusive(child, NULL);
172 if (IS_ERR(rst)) {
173 of_node_put(child);
174 return PTR_ERR(rst);
175 }
176
177 priv->ports[i].utmi_rst = rst;
178 priv->ports[i].priv = priv;
179
180 phy = devm_phy_create(dev, child, &hisi_inno_phy_ops);
181 if (IS_ERR(phy)) {
182 of_node_put(child);
183 return PTR_ERR(phy);
184 }
185
186 phy_set_bus_width(phy, 8);
187 phy_set_drvdata(phy, &priv->ports[i]);
188 i++;
189
190 if (i > INNO_PHY_PORT_NUM) {
191 dev_warn(dev, "Support %d ports in maximum\n", i);
192 of_node_put(child);
193 break;
194 }
195 }
196
197 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
198 return PTR_ERR_OR_ZERO(provider);
199 }
200

--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests

2023-05-08 08:26:47

by Vinod Koul

[permalink] [raw]
Subject: Re: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100

On 07-05-23, 23:46, David Yang wrote:
> Hisilicon also uses phy-hisi-inno-usb2 on Hi3798MV100, with a slightly
> different register convention.

OK, so what should I expect from this patch, pls document that here...

>
> Signed-off-by: David Yang <[email protected]>
> ---
> drivers/phy/hisilicon/Kconfig | 2 +-
> drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 67 ++++++++++++++++------
> 2 files changed, 51 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
> index d3b92c288554..6c89136fc8c2 100644
> --- a/drivers/phy/hisilicon/Kconfig
> +++ b/drivers/phy/hisilicon/Kconfig
> @@ -54,7 +54,7 @@ config PHY_HISTB_COMBPHY
>
> config PHY_HISI_INNO_USB2
> tristate "HiSilicon INNO USB2 PHY support"
> - depends on (ARCH_HISI && ARM64) || COMPILE_TEST
> + depends on ARCH_HISI || COMPILE_TEST

why this change?

> select GENERIC_PHY
> select MFD_SYSCON
> help
> diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> index b133ae06757a..b5d006f38934 100644
> --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> @@ -9,7 +9,7 @@
> #include <linux/delay.h>
> #include <linux/io.h>
> #include <linux/module.h>
> -#include <linux/platform_device.h>
> +#include <linux/of_device.h>
> #include <linux/phy/phy.h>
> #include <linux/reset.h>
>
> @@ -20,12 +20,28 @@
> #define PHY_CLK_STABLE_TIME 2 /* unit:ms */
> #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
> #define POR_RST_COMPLETE_TIME 300 /* unit:us */
> -#define PHY_TEST_DATA GENMASK(7, 0)
> -#define PHY_TEST_ADDR GENMASK(15, 8)
> -#define PHY_TEST_PORT GENMASK(18, 16)
> -#define PHY_TEST_WREN BIT(21)
> -#define PHY_TEST_CLK BIT(22) /* rising edge active */
> -#define PHY_TEST_RST BIT(23) /* low active */
> +
> +#define PHY_TYPE_0 0
> +#define PHY_TYPE_1 1
> +
> +#define PHY0_TEST_DATA GENMASK(7, 0)

same as previous what changed??

> +#define PHY0_TEST_ADDR_OFFSET 8
> +#define PHY0_TEST_ADDR GENMASK(15, 8)
> +#define PHY0_TEST_PORT_OFFSET 16
> +#define PHY0_TEST_PORT GENMASK(18, 16)
> +#define PHY0_TEST_WREN BIT(21)
> +#define PHY0_TEST_CLK BIT(22) /* rising edge active */
> +#define PHY0_TEST_RST BIT(23) /* low active */
> +
> +#define PHY1_TEST_DATA GENMASK(7, 0)
> +#define PHY1_TEST_ADDR_OFFSET 8
> +#define PHY1_TEST_ADDR GENMASK(11, 8)
> +#define PHY1_TEST_PORT_OFFSET 12
> +#define PHY1_TEST_PORT BIT(12)
> +#define PHY1_TEST_WREN BIT(13)
> +#define PHY1_TEST_CLK BIT(14) /* rising edge active */
> +#define PHY1_TEST_RST BIT(15) /* low active */
> +
> #define PHY_CLK_ENABLE BIT(2)
>
> struct hisi_inno_phy_port {
> @@ -37,6 +53,7 @@ struct hisi_inno_phy_priv {
> void __iomem *mmio;
> struct clk *ref_clk;
> struct reset_control *por_rst;
> + unsigned int type;
> struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
> };
>
> @@ -45,17 +62,27 @@ static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
> {
> void __iomem *reg = priv->mmio;
> u32 val;
> -
> - val = (data & PHY_TEST_DATA) |
> - ((addr << 8) & PHY_TEST_ADDR) |
> - ((port << 16) & PHY_TEST_PORT) |
> - PHY_TEST_WREN | PHY_TEST_RST;
> + u32 value;
> +
> + if (priv->type == PHY_TYPE_0)
> + val = (data & PHY0_TEST_DATA) |
> + ((addr << PHY0_TEST_ADDR_OFFSET) & PHY0_TEST_ADDR) |
> + ((port << PHY0_TEST_PORT_OFFSET) & PHY0_TEST_PORT) |
> + PHY0_TEST_WREN | PHY0_TEST_RST;
> + else
> + val = (data & PHY1_TEST_DATA) |
> + ((addr << PHY1_TEST_ADDR_OFFSET) & PHY1_TEST_ADDR) |
> + ((port << PHY1_TEST_PORT_OFFSET) & PHY1_TEST_PORT) |
> + PHY1_TEST_WREN | PHY1_TEST_RST;
> writel(val, reg);
>
> - val |= PHY_TEST_CLK;
> - writel(val, reg);
> + value = val;
> + if (priv->type == PHY_TYPE_0)
> + value |= PHY0_TEST_CLK;
> + else
> + value |= PHY1_TEST_CLK;
> + writel(value, reg);
>
> - val &= ~PHY_TEST_CLK;
> writel(val, reg);
> }
>
> @@ -135,6 +162,8 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
> if (IS_ERR(priv->por_rst))
> return PTR_ERR(priv->por_rst);
>
> + priv->type = (unsigned int) of_device_get_match_data(dev);
> +
> for_each_child_of_node(np, child) {
> struct reset_control *rst;
> struct phy *phy;
> @@ -170,8 +199,12 @@ static int hisi_inno_phy_probe(struct platform_device *pdev)
> }
>
> static const struct of_device_id hisi_inno_phy_of_match[] = {
> - { .compatible = "hisilicon,inno-usb2-phy", },
> - { .compatible = "hisilicon,hi3798cv200-usb2-phy", },
> + { .compatible = "hisilicon,inno-usb2-phy",
> + .data = (void *) PHY_TYPE_0 },
> + { .compatible = "hisilicon,hi3798cv200-usb2-phy",
> + .data = (void *) PHY_TYPE_0 },
> + { .compatible = "hisilicon,hi3798mv100-usb2-phy",
> + .data = (void *) PHY_TYPE_1 },
> { },
> };
> MODULE_DEVICE_TABLE(of, hisi_inno_phy_of_match);
> --
> 2.39.2

--
~Vinod

2023-05-08 11:55:49

by Vinod Koul

[permalink] [raw]
Subject: Re: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100

On 08-05-23, 19:39, Yangfl wrote:
> Vinod Koul <[email protected]> 于2023年5月8日周一 15:41写道:
> >
> > On 07-05-23, 23:46, David Yang wrote:
> > > Hisilicon also uses phy-hisi-inno-usb2 on Hi3798MV100, with a slightly
> > > different register convention.
> >
> > OK, so what should I expect from this patch, pls document that here...
>
> Hi3798MV100 usb2 phy. Which kind of document should I put here?

Pls add the details on what is being changed in this patch. this is the
place where patch description is provided, what are all the things that
are getting changed

>
> >
> > >
> > > Signed-off-by: David Yang <[email protected]>
> > > ---
> > > drivers/phy/hisilicon/Kconfig | 2 +-
> > > drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 67 ++++++++++++++++------
> > > 2 files changed, 51 insertions(+), 18 deletions(-)
> > >
> > > diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
> > > index d3b92c288554..6c89136fc8c2 100644
> > > --- a/drivers/phy/hisilicon/Kconfig
> > > +++ b/drivers/phy/hisilicon/Kconfig
> > > @@ -54,7 +54,7 @@ config PHY_HISTB_COMBPHY
> > >
> > > config PHY_HISI_INNO_USB2
> > > tristate "HiSilicon INNO USB2 PHY support"
> > > - depends on (ARCH_HISI && ARM64) || COMPILE_TEST
> > > + depends on ARCH_HISI || COMPILE_TEST
> >
> > why this change?
>
> Hi3798MV100 is a A9 ARM32 only soc.

OK pls document that, also suspect that might a separate patch..?

>
> >
> > > select GENERIC_PHY
> > > select MFD_SYSCON
> > > help
> > > diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > > index b133ae06757a..b5d006f38934 100644
> > > --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > > +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > > @@ -9,7 +9,7 @@
> > > #include <linux/delay.h>
> > > #include <linux/io.h>
> > > #include <linux/module.h>
> > > -#include <linux/platform_device.h>
> > > +#include <linux/of_device.h>
> > > #include <linux/phy/phy.h>
> > > #include <linux/reset.h>
> > >
> > > @@ -20,12 +20,28 @@
> > > #define PHY_CLK_STABLE_TIME 2 /* unit:ms */
> > > #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
> > > #define POR_RST_COMPLETE_TIME 300 /* unit:us */
> > > -#define PHY_TEST_DATA GENMASK(7, 0)
> > > -#define PHY_TEST_ADDR GENMASK(15, 8)
> > > -#define PHY_TEST_PORT GENMASK(18, 16)
> > > -#define PHY_TEST_WREN BIT(21)
> > > -#define PHY_TEST_CLK BIT(22) /* rising edge active */
> > > -#define PHY_TEST_RST BIT(23) /* low active */
> > > +
> > > +#define PHY_TYPE_0 0
> > > +#define PHY_TYPE_1 1
> > > +
> > > +#define PHY0_TEST_DATA GENMASK(7, 0)
> >
> > same as previous what changed??
>
> Register convention for PHY1 below, as mentioned in commit message.

It is _exactly_ same as previous, so pls dont introduce unnecessary
changes..

--
~Vinod

2023-05-08 11:59:01

by David Yang

[permalink] [raw]
Subject: Re: [PATCH] phy: hisilicon: Adopt phy-hisi-inno-usb2 to Hi3798MV100

Vinod Koul <[email protected]> 于2023年5月8日周一 15:41写道:
>
> On 07-05-23, 23:46, David Yang wrote:
> > Hisilicon also uses phy-hisi-inno-usb2 on Hi3798MV100, with a slightly
> > different register convention.
>
> OK, so what should I expect from this patch, pls document that here...

Hi3798MV100 usb2 phy. Which kind of document should I put here?

>
> >
> > Signed-off-by: David Yang <[email protected]>
> > ---
> > drivers/phy/hisilicon/Kconfig | 2 +-
> > drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 67 ++++++++++++++++------
> > 2 files changed, 51 insertions(+), 18 deletions(-)
> >
> > diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
> > index d3b92c288554..6c89136fc8c2 100644
> > --- a/drivers/phy/hisilicon/Kconfig
> > +++ b/drivers/phy/hisilicon/Kconfig
> > @@ -54,7 +54,7 @@ config PHY_HISTB_COMBPHY
> >
> > config PHY_HISI_INNO_USB2
> > tristate "HiSilicon INNO USB2 PHY support"
> > - depends on (ARCH_HISI && ARM64) || COMPILE_TEST
> > + depends on ARCH_HISI || COMPILE_TEST
>
> why this change?

Hi3798MV100 is a A9 ARM32 only soc.

>
> > select GENERIC_PHY
> > select MFD_SYSCON
> > help
> > diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > index b133ae06757a..b5d006f38934 100644
> > --- a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > +++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
> > @@ -9,7 +9,7 @@
> > #include <linux/delay.h>
> > #include <linux/io.h>
> > #include <linux/module.h>
> > -#include <linux/platform_device.h>
> > +#include <linux/of_device.h>
> > #include <linux/phy/phy.h>
> > #include <linux/reset.h>
> >
> > @@ -20,12 +20,28 @@
> > #define PHY_CLK_STABLE_TIME 2 /* unit:ms */
> > #define UTMI_RST_COMPLETE_TIME 2 /* unit:ms */
> > #define POR_RST_COMPLETE_TIME 300 /* unit:us */
> > -#define PHY_TEST_DATA GENMASK(7, 0)
> > -#define PHY_TEST_ADDR GENMASK(15, 8)
> > -#define PHY_TEST_PORT GENMASK(18, 16)
> > -#define PHY_TEST_WREN BIT(21)
> > -#define PHY_TEST_CLK BIT(22) /* rising edge active */
> > -#define PHY_TEST_RST BIT(23) /* low active */
> > +
> > +#define PHY_TYPE_0 0
> > +#define PHY_TYPE_1 1
> > +
> > +#define PHY0_TEST_DATA GENMASK(7, 0)
>
> same as previous what changed??

Register convention for PHY1 below, as mentioned in commit message.