On Mon, Oct 25, 2021 at 9:36 AM <[email protected]> wrote:
>
> From: Wei Fu <[email protected]>
>
> Previous patch has added svpbmt in arch/riscv and changed the
> DT mmu-type. Update dt-bindings related property here.
>
> Signed-off-by: Wei Fu <[email protected]>
> Co-developed-by: Guo Ren <[email protected]>
> Signed-off-by: Guo Ren <[email protected]>
> Cc: Anup Patel <[email protected]>
> Cc: Palmer Dabbelt <[email protected]>
> Cc: Rob Herring <[email protected]>
> ---
> Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> index e534f6a7cfa1..76f324d85e12 100644
> --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> @@ -59,6 +59,11 @@ properties:
> - riscv,sv48
> - riscv,none
>
> + mmu-supports-svpbmt:
> + description:
> + Describes the CPU's mmu-supports-svpbmt support
> + $ref: '/schemas/types.yaml#/definitions/phandle'
There were various proposals from different folks in the previous
email threads.
I think most of us were converging on:
1) Don't modify "mmu-type" DT property for backward
compatibility
2) Add boolean DT property "riscv,svpmbt" under
"mmu" child DT node of each CPU DT node. Same will apply
to boolean DT property "riscv,svnapot" as well.
We also have bitmanip and vector broken down into smaller
extensions so grouping related extensions as separate DT node
under each CPU node will be more readable and easy to parse.
Regards,
Anup
> +
> riscv,isa:
> description:
> Identifies the specific RISC-V instruction set architecture
> --
> 2.25.4
>
On Mon, Oct 25, 2021 at 12:17 PM Anup Patel <[email protected]> wrote:
>
> On Mon, Oct 25, 2021 at 9:36 AM <[email protected]> wrote:
> >
> > From: Wei Fu <[email protected]>
> >
> > Previous patch has added svpbmt in arch/riscv and changed the
> > DT mmu-type. Update dt-bindings related property here.
> >
> > Signed-off-by: Wei Fu <[email protected]>
> > Co-developed-by: Guo Ren <[email protected]>
> > Signed-off-by: Guo Ren <[email protected]>
> > Cc: Anup Patel <[email protected]>
> > Cc: Palmer Dabbelt <[email protected]>
> > Cc: Rob Herring <[email protected]>
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index e534f6a7cfa1..76f324d85e12 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -59,6 +59,11 @@ properties:
> > - riscv,sv48
> > - riscv,none
> >
> > + mmu-supports-svpbmt:
> > + description:
> > + Describes the CPU's mmu-supports-svpbmt support
> > + $ref: '/schemas/types.yaml#/definitions/phandle'
>
> There were various proposals from different folks in the previous
> email threads.
>
> I think most of us were converging on:
> 1) Don't modify "mmu-type" DT property for backward
> compatibility
I agree. FuWei has followed that in the patch.
> 2) Add boolean DT property "riscv,svpmbt" under
> "mmu" child DT node of each CPU DT node. Same will apply
> to boolean DT property "riscv,svnapot" as well.
We have various proposals here:
@Philipp suggests firstly, but break the backward compatibility:
cpu@0 {
...
mmu {
type = "riscv,sv39";
supports-svpbmt;
supports-svnapot;
};
@guoren suggests reusing the mmu-type, but seems not clean.
cpu@0 {
...
mmu-type = "riscv,sv39,svpbmt,svnapot";
@fuwei suggests simple name property in CPU section:
cpu@0 {
...
mmu-type = "riscv,sv39";
mmu-supports-svpbmt;
mmu-supports-svnapot;
@Anup suggests:
cpu@0 {
...
mmu-type = "riscv,sv39";
mmu {
supports-svpbmt;
supports-svnapot;
};
Any other suggestions? Thx.
>
> We also have bitmanip and vector broken down into smaller
> extensions so grouping related extensions as separate DT node
> under each CPU node will be more readable and easy to parse.
Do you mean combine mmu extensions with them together?
cpu@0 {
...
extensions {
supports-svpbmt;
supports-svnapot;
supports-bitmanip;
supports-vector-v0p7;
};
>
> Regards,
> Anup
>
> > +
> > riscv,isa:
> > description:
> > Identifies the specific RISC-V instruction set architecture
> > --
> > 2.25.4
> >
--
Best Regards
Guo Ren
ML: https://lore.kernel.org/linux-csky/
On Mon, Oct 25, 2021 at 11:30 AM Guo Ren <[email protected]> wrote:
>
> On Mon, Oct 25, 2021 at 12:17 PM Anup Patel <[email protected]> wrote:
> >
> > On Mon, Oct 25, 2021 at 9:36 AM <[email protected]> wrote:
> > >
> > > From: Wei Fu <[email protected]>
> > >
> > > Previous patch has added svpbmt in arch/riscv and changed the
> > > DT mmu-type. Update dt-bindings related property here.
> > >
> > > Signed-off-by: Wei Fu <[email protected]>
> > > Co-developed-by: Guo Ren <[email protected]>
> > > Signed-off-by: Guo Ren <[email protected]>
> > > Cc: Anup Patel <[email protected]>
> > > Cc: Palmer Dabbelt <[email protected]>
> > > Cc: Rob Herring <[email protected]>
> > > ---
> > > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> > > 1 file changed, 5 insertions(+)
> > >
> > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > index e534f6a7cfa1..76f324d85e12 100644
> > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > @@ -59,6 +59,11 @@ properties:
> > > - riscv,sv48
> > > - riscv,none
> > >
> > > + mmu-supports-svpbmt:
> > > + description:
> > > + Describes the CPU's mmu-supports-svpbmt support
> > > + $ref: '/schemas/types.yaml#/definitions/phandle'
> >
> > There were various proposals from different folks in the previous
> > email threads.
> >
> > I think most of us were converging on:
> > 1) Don't modify "mmu-type" DT property for backward
> > compatibility
> I agree. FuWei has followed that in the patch.
>
> > 2) Add boolean DT property "riscv,svpmbt" under
> > "mmu" child DT node of each CPU DT node. Same will apply
> > to boolean DT property "riscv,svnapot" as well.
> We have various proposals here:
> @Philipp suggests firstly, but break the backward compatibility:
> cpu@0 {
> ...
> mmu {
> type = "riscv,sv39";
> supports-svpbmt;
> supports-svnapot;
> };
>
> @guoren suggests reusing the mmu-type, but seems not clean.
> cpu@0 {
> ...
> mmu-type = "riscv,sv39,svpbmt,svnapot";
>
>
> @fuwei suggests simple name property in CPU section:
> cpu@0 {
> ...
> mmu-type = "riscv,sv39";
> mmu-supports-svpbmt;
> mmu-supports-svnapot;
>
> @Anup suggests:
> cpu@0 {
> ...
> mmu-type = "riscv,sv39";
> mmu {
> supports-svpbmt;
> supports-svnapot;
> };
>
> Any other suggestions? Thx.
>
> >
> > We also have bitmanip and vector broken down into smaller
> > extensions so grouping related extensions as separate DT node
> > under each CPU node will be more readable and easy to parse.
> Do you mean combine mmu extensions with them together?
> cpu@0 {
> ...
> extensions {
> supports-svpbmt;
> supports-svnapot;
> supports-bitmanip;
> supports-vector-v0p7;
> };
I meant separate group nodes like this:
cpu@0 {
...
mmu-type = "riscv,sv39";
mmu { /* Only considered when mmu-type is present and mmu-type !=
"riscv,sv32" */
riscv,svpmbt;
riscv,svnapot;
};
bitmanip { /* Only considered when "B" is present in the ISA string */
...
};
vector { /* Only considered when "V" is present in the ISA string */
...
};
...
};
Regards,
Anup
>
> >
> > Regards,
> > Anup
> >
> > > +
> > > riscv,isa:
> > > description:
> > > Identifies the specific RISC-V instruction set architecture
> > > --
> > > 2.25.4
> > >
>
>
>
> --
> Best Regards
> Guo Ren
>
> ML: https://lore.kernel.org/linux-csky/
On Mon, 25 Oct 2021 at 08:08, Anup Patel <[email protected]> wrote:
>
> On Mon, Oct 25, 2021 at 11:30 AM Guo Ren <[email protected]> wrote:
> >
> > On Mon, Oct 25, 2021 at 12:17 PM Anup Patel <[email protected]> wrote:
> > >
> > > On Mon, Oct 25, 2021 at 9:36 AM <[email protected]> wrote:
> > > >
> > > > From: Wei Fu <[email protected]>
> > > >
> > > > Previous patch has added svpbmt in arch/riscv and changed the
> > > > DT mmu-type. Update dt-bindings related property here.
> > > >
> > > > Signed-off-by: Wei Fu <[email protected]>
> > > > Co-developed-by: Guo Ren <[email protected]>
> > > > Signed-off-by: Guo Ren <[email protected]>
> > > > Cc: Anup Patel <[email protected]>
> > > > Cc: Palmer Dabbelt <[email protected]>
> > > > Cc: Rob Herring <[email protected]>
> > > > ---
> > > > Documentation/devicetree/bindings/riscv/cpus.yaml | 5 +++++
> > > > 1 file changed, 5 insertions(+)
> > > >
> > > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > index e534f6a7cfa1..76f324d85e12 100644
> > > > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > > > @@ -59,6 +59,11 @@ properties:
> > > > - riscv,sv48
> > > > - riscv,none
> > > >
> > > > + mmu-supports-svpbmt:
> > > > + description:
> > > > + Describes the CPU's mmu-supports-svpbmt support
> > > > + $ref: '/schemas/types.yaml#/definitions/phandle'
> > >
> > > There were various proposals from different folks in the previous
> > > email threads.
> > >
> > > I think most of us were converging on:
> > > 1) Don't modify "mmu-type" DT property for backward
> > > compatibility
> > I agree. FuWei has followed that in the patch.
> >
> > > 2) Add boolean DT property "riscv,svpmbt" under
> > > "mmu" child DT node of each CPU DT node. Same will apply
> > > to boolean DT property "riscv,svnapot" as well.
> > We have various proposals here:
> > @Philipp suggests firstly, but break the backward compatibility:
> > cpu@0 {
> > ...
> > mmu {
> > type = "riscv,sv39";
> > supports-svpbmt;
> > supports-svnapot;
> > };
> >
> > @guoren suggests reusing the mmu-type, but seems not clean.
> > cpu@0 {
> > ...
> > mmu-type = "riscv,sv39,svpbmt,svnapot";
> >
> >
> > @fuwei suggests simple name property in CPU section:
> > cpu@0 {
> > ...
> > mmu-type = "riscv,sv39";
> > mmu-supports-svpbmt;
> > mmu-supports-svnapot;
> >
> > @Anup suggests:
> > cpu@0 {
> > ...
> > mmu-type = "riscv,sv39";
> > mmu {
> > supports-svpbmt;
> > supports-svnapot;
> > };
> >
> > Any other suggestions? Thx.
> >
> > >
> > > We also have bitmanip and vector broken down into smaller
> > > extensions so grouping related extensions as separate DT node
> > > under each CPU node will be more readable and easy to parse.
> > Do you mean combine mmu extensions with them together?
> > cpu@0 {
> > ...
> > extensions {
> > supports-svpbmt;
> > supports-svnapot;
> > supports-bitmanip;
> > supports-vector-v0p7;
> > };
>
> I meant separate group nodes like this:
>
> cpu@0 {
> ...
> mmu-type = "riscv,sv39";
> mmu { /* Only considered when mmu-type is present and mmu-type !=
> "riscv,sv32" */
> riscv,svpmbt;
> riscv,svnapot;
> };
>
> bitmanip { /* Only considered when "B" is present in the ISA string */
> ...
> };
Please disregard this comment regarding bitmanip/B.
The B bit in the misa CSR is not used for any signalling regarding
Zb[abcs] (or the other Zb-extensions), so this entire node is not
needed and B in the ISA string is not related to any of the Zb*
extensions).
All Zb* extensions are directly visible from the ISA string.
> vector { /* Only considered when "V" is present in the ISA string */
> ...
> };
> ...
> };
>
> Regards,
> Anup
>
> >
> > >
> > > Regards,
> > > Anup
> > >
> > > > +
> > > > riscv,isa:
> > > > description:
> > > > Identifies the specific RISC-V instruction set architecture
> > > > --
> > > > 2.25.4
> > > >
> >
> >
> >
> > --
> > Best Regards
> > Guo Ren
> >
> > ML: https://lore.kernel.org/linux-csky/