2022-03-24 02:03:40

by Atish Patra

Subject: Re: [PATCH] RISC-V: Enable perf events by default

On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <[email protected]> wrote:
>
> Let us enable perf events by default in RV32 and RV64 defconfigs
> so that we can use RISC-V PMU drivers on various RISC-V platforms.
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> arch/riscv/configs/defconfig | 1 +
> arch/riscv/configs/rv32_defconfig | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> index f120fcc43d0a..57aaedc7cf74 100644
> --- a/arch/riscv/configs/defconfig
> +++ b/arch/riscv/configs/defconfig
> @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> +CONFIG_PERF_EVENTS=y
> CONFIG_SOC_MICROCHIP_POLARFIRE=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> index 8b56a7f1eb06..21d422e740d5 100644
> --- a/arch/riscv/configs/rv32_defconfig
> +++ b/arch/riscv/configs/rv32_defconfig
> @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> CONFIG_BLK_DEV_INITRD=y
> CONFIG_EXPERT=y
> # CONFIG_SYSFS_SYSCALL is not set
> +CONFIG_PERF_EVENTS=y
> CONFIG_SOC_SIFIVE=y
> CONFIG_SOC_VIRT=y
> CONFIG_ARCH_RV32I=y
> --
> 2.25.1
>

I think it is better to enable perf events by adding CONFIG_PROFILING
to the defconfig similar to other ISAs.

--
Regards,
Atish

2022-03-24 23:35:39

by Anup Patel

Subject: Re: [PATCH] RISC-V: Enable perf events by default

On Wed, Mar 23, 2022 at 10:04 PM Atish Patra <[email protected]> wrote:
>
> On Wed, Mar 23, 2022 at 2:00 AM Anup Patel <[email protected]> wrote:
> >
> > Let us enable perf events by default in RV32 and RV64 defconfigs
> > so that we can use RISC-V PMU drivers on various RISC-V platforms.
> >
> > Signed-off-by: Anup Patel <[email protected]>
> > ---
> > arch/riscv/configs/defconfig | 1 +
> > arch/riscv/configs/rv32_defconfig | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
> > index f120fcc43d0a..57aaedc7cf74 100644
> > --- a/arch/riscv/configs/defconfig
> > +++ b/arch/riscv/configs/defconfig
> > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> > CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > +CONFIG_PERF_EVENTS=y
> > CONFIG_SOC_MICROCHIP_POLARFIRE=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_VIRT=y
> > diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig
> > index 8b56a7f1eb06..21d422e740d5 100644
> > --- a/arch/riscv/configs/rv32_defconfig
> > +++ b/arch/riscv/configs/rv32_defconfig
> > @@ -15,6 +15,7 @@ CONFIG_CHECKPOINT_RESTORE=y
> > CONFIG_BLK_DEV_INITRD=y
> > CONFIG_EXPERT=y
> > # CONFIG_SYSFS_SYSCALL is not set
> > +CONFIG_PERF_EVENTS=y
> > CONFIG_SOC_SIFIVE=y
> > CONFIG_SOC_VIRT=y
> > CONFIG_ARCH_RV32I=y
> > --
> > 2.25.1
> >
>
> I think it is better to enable perf events by adding CONFIG_PROFILING
> to the defconfig similar to other ISAs.

Sure, I will update this patch like you suggested.

Regards,
Anup

>
> --
> Regards,
> Atish