This patch-set is based on 'riscv-for-v5.2/fixes-rc6' tag of
git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git
Tested on HiFive Unleashed board with additional patches required for
testing can be found at dev/yashs/ethernet_dt branch of:
https://github.com/yashshah7/riscv-linux.git
Yash Shah (1):
riscv: dts: Add DT node for SiFive FU540 Ethernet controller driver
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
--
1.9.1
DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
Signed-off-by: Yash Shah <[email protected]>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 4e8fbde..584e737 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -225,5 +225,25 @@
#address-cells = <1>;
#size-cells = <0>;
};
+ eth0: ethernet@10090000 {
+ compatible = "sifive,fu540-macb";
+ interrupt-parent = <&plic0>;
+ interrupts = <53>;
+ reg = <0x0 0x10090000 0x0 0x2000
+ 0x0 0x100a0000 0x0 0x1000>;
+ reg-names = "control";
+ local-mac-address = [00 00 00 00 00 00];
+ phy-mode = "gmii";
+ phy-handle = <&phy1>;
+ clock-names = "pclk", "hclk";
+ clocks = <&prci PRCI_CLK_GEMGXLPLL>,
+ <&prci PRCI_CLK_GEMGXLPLL>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+
};
};
--
1.9.1
On Fri, Jun 21, 2019 at 11:40 AM Yash Shah <[email protected]> wrote:
>
> DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
>
> Signed-off-by: Yash Shah <[email protected]>
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> index 4e8fbde..584e737 100644
> --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> @@ -225,5 +225,25 @@
> #address-cells = <1>;
> #size-cells = <0>;
> };
> + eth0: ethernet@10090000 {
> + compatible = "sifive,fu540-macb";
> + interrupt-parent = <&plic0>;
> + interrupts = <53>;
> + reg = <0x0 0x10090000 0x0 0x2000
> + 0x0 0x100a0000 0x0 0x1000>;
> + reg-names = "control";
> + local-mac-address = [00 00 00 00 00 00];
> + phy-mode = "gmii";
> + phy-handle = <&phy1>;
> + clock-names = "pclk", "hclk";
> + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> + <&prci PRCI_CLK_GEMGXLPLL>;
> + #address-cells = <1>;
> + #size-cells = <0>;
Have status = "disabled"; here and have
status = "okay" in board DTS file.
General convention for any SOC device with external
connection (e.g. ethernet, SPI, SDHC, SATA, PCI, etc)
is:
1. Define only device DT node in SOC DTSi file with
status = "disabled"
2. Enable device in Board DTS file with
status = "okay"
3. Define PHY or external PIN connection details
in Board DTS file
> + phy1: ethernet-phy@0 {
> + reg = <0>;
> + };
The PHY DT node should be in Board DTS file.
Of course, same comments apply to SPI DT nodes as well
but I missed reviewing those DT nodes. You can send separate
DT patch to re-organize SPI DT nodes.
Regards,
Anup
On Fri, Jun 21, 2019 at 2:31 PM Anup Patel <[email protected]> wrote:
>
> On Fri, Jun 21, 2019 at 11:40 AM Yash Shah <[email protected]> wrote:
> >
> > DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
> >
> > Signed-off-by: Yash Shah <[email protected]>
> > ---
> > arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 20 ++++++++++++++++++++
> > 1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > index 4e8fbde..584e737 100644
> > --- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > +++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
> > @@ -225,5 +225,25 @@
> > #address-cells = <1>;
> > #size-cells = <0>;
> > };
> > + eth0: ethernet@10090000 {
> > + compatible = "sifive,fu540-macb";
> > + interrupt-parent = <&plic0>;
> > + interrupts = <53>;
> > + reg = <0x0 0x10090000 0x0 0x2000
> > + 0x0 0x100a0000 0x0 0x1000>;
> > + reg-names = "control";
> > + local-mac-address = [00 00 00 00 00 00];
> > + phy-mode = "gmii";
> > + phy-handle = <&phy1>;
> > + clock-names = "pclk", "hclk";
> > + clocks = <&prci PRCI_CLK_GEMGXLPLL>,
> > + <&prci PRCI_CLK_GEMGXLPLL>;
> > + #address-cells = <1>;
> > + #size-cells = <0>;
>
> Have status = "disabled"; here and have
> status = "okay" in board DTS file.
>
> General convention for any SOC device with external
> connection (e.g. ethernet, SPI, SDHC, SATA, PCI, etc)
> is:
>
> 1. Define only device DT node in SOC DTSi file with
> status = "disabled"
> 2. Enable device in Board DTS file with
> status = "okay"
> 3. Define PHY or external PIN connection details
> in Board DTS file
>
> > + phy1: ethernet-phy@0 {
> > + reg = <0>;
> > + };
>
> The PHY DT node should be in Board DTS file.
Will move all PHY related nodes in board DTS file.
>
> Of course, same comments apply to SPI DT nodes as well
> but I missed reviewing those DT nodes. You can send separate
> DT patch to re-organize SPI DT nodes.
Sure, will send a separate patch for SPI DT nodes as well.
Thanks for your comments.
- Yash
>
> Regards,
> Anup
On Fri, 21 Jun 2019, Yash Shah wrote:
> DT node for SiFive FU540-C000 GEMGXL Ethernet controller driver added
>
> Signed-off-by: Yash Shah <[email protected]>
Dropping this one until it's updated to align with whatever you pick for
the new driver DT compatible string, per
https://lore.kernel.org/linux-riscv/[email protected]/T/#me298e16b2feeb481116cca61b94e014433cf2977
Please send an updated DT patch at your earliest convenience so we can get
it into the v5.3-rc series.
- Paul