2020-08-27 08:04:31

by Tiezhu Yang

Subject: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

According to the user's manual chapter 8.2.1 of Loongson 3A2000 CPU [1]
and 3A3000 CPU [2], we should take some event IDs such as 274, 358, 359
and 360 as valid in the check condition, otherwise they are recognized
as "not supported", fix it.

[1] http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf
[2] http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf

Fixes: e9dfbaaeef1c ("MIPS: perf: Add hardware perf events support for new Loongson-3")
Signed-off-by: Tiezhu Yang <[email protected]>
---
arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index efce5de..011eb6bb 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
(base_id >= 64 && base_id < 90) ||
(base_id >= 128 && base_id < 164) ||
(base_id >= 192 && base_id < 200) ||
- (base_id >= 256 && base_id < 274) ||
- (base_id >= 320 && base_id < 358) ||
+ (base_id >= 256 && base_id < 275) ||
+ (base_id >= 320 && base_id < 361) ||
(base_id >= 384 && base_id < 574))
break;

--
2.1.0

2020-08-28 08:52:56

by Huacai Chen

Subject: Re: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

Hi, Pei,

On Thu, Aug 27, 2020 at 4:05 PM Tiezhu Yang <[email protected]> wrote:
>
> According to the user's manual chapter 8.2.1 of Loongson 3A2000 CPU [1]
> and 3A3000 CPU [2], we should take some event IDs such as 274, 358, 359
> and 360 as valid in the check condition, otherwise they are recognized
> as "not supported", fix it.
I think this patch needs you to confirm.

>
> [1] http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf
> [2] http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf
>
> Fixes: e9dfbaaeef1c ("MIPS: perf: Add hardware perf events support for new Loongson-3")
> Signed-off-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> index efce5de..011eb6bb 100644
> --- a/arch/mips/kernel/perf_event_mipsxx.c
> +++ b/arch/mips/kernel/perf_event_mipsxx.c
> @@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
> (base_id >= 64 && base_id < 90) ||
> (base_id >= 128 && base_id < 164) ||
> (base_id >= 192 && base_id < 200) ||
> - (base_id >= 256 && base_id < 274) ||
> - (base_id >= 320 && base_id < 358) ||
> + (base_id >= 256 && base_id < 275) ||
> + (base_id >= 320 && base_id < 361) ||
> (base_id >= 384 && base_id < 574))
> break;
>
> --
> 2.1.0
>

2020-09-01 08:45:13

by Huang Pei

Subject: Re: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

On Fri, Aug 28, 2020 at 04:49:37PM +0800, Huacai Chen wrote:
> Hi, Pei,
>
> On Thu, Aug 27, 2020 at 4:05 PM Tiezhu Yang <[email protected]> wrote:
> >
> > According to the user's manual chapter 8.2.1 of Loongson 3A2000 CPU [1]
> > and 3A3000 CPU [2], we should take some event IDs such as 274, 358, 359
> > and 360 as valid in the check condition, otherwise they are recognized
> > as "not supported", fix it.
> I think this patch needs you to confirm.
>
> >
> > [1] http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf
> > [2] http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf
> >
> > Fixes: e9dfbaaeef1c ("MIPS: perf: Add hardware perf events support for new Loongson-3")
> > Signed-off-by: Tiezhu Yang <[email protected]>
> > ---
> > arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
> > index efce5de..011eb6bb 100644
> > --- a/arch/mips/kernel/perf_event_mipsxx.c
> > +++ b/arch/mips/kernel/perf_event_mipsxx.c
> > @@ -1898,8 +1898,8 @@ static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
> > (base_id >= 64 && base_id < 90) ||
> > (base_id >= 128 && base_id < 164) ||
> > (base_id >= 192 && base_id < 200) ||
> > - (base_id >= 256 && base_id < 274) ||
> > - (base_id >= 320 && base_id < 358) ||
> > + (base_id >= 256 && base_id < 275) ||
> > + (base_id >= 320 && base_id < 361) ||
> > (base_id >= 384 && base_id < 574))
> > break;
> >
> > --
> > 2.1.0
> >
Acked-by: Huang Pei <[email protected]>

2020-09-03 08:30:27

by Thomas Bogendoerfer

Subject: Re: [PATCH] MIPS: perf: Fix wrong check condition of Loongson event IDs

On Thu, Aug 27, 2020 at 04:03:08PM +0800, Tiezhu Yang wrote:
> According to the user's manual chapter 8.2.1 of Loongson 3A2000 CPU [1]
> and 3A3000 CPU [2], we should take some event IDs such as 274, 358, 359
> and 360 as valid in the check condition, otherwise they are recognized
> as "not supported", fix it.
>
> [1] http://www.loongson.cn/uploadfile/cpu/3A2000/Loongson3A2000_user2.pdf
> [2] http://www.loongson.cn/uploadfile/cpu/3A3000/Loongson3A3000_3B3000user2.pdf
>
> Fixes: e9dfbaaeef1c ("MIPS: perf: Add hardware perf events support for new Loongson-3")
> Signed-off-by: Tiezhu Yang <[email protected]>
> ---
> arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)

applied to mips-fixes.

Thomas.

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