These patches support single-core DTS boot to the serial port login
interface, which can be operated using conventional commands.
I have successfully tested it on the Loongson 2K1000 machine.
pmon: http://cgit.loongnix.org/cgit/pmon-loongson3/
Qing Zhang (7):
MIPS: Loongson64: DeviceTree for 2K1000
MIPS: Loongson64: Distinguish firmware dependencies DTB/LEFI
MIPS: Loongson64: Add support for the 2K1000 to get cpu_clock_freq
MIPS: Loongson64: Add 2K1000 early_printk_port
irqchip/loongson-liointc: irqchip add 2.0 version
dt-bindings: interrupt-controller: Add Loongson-2K1000 LIOINTC
MIPS: Loongson64: Add a Loongson-2k default config file
.../loongson,liointc.yaml | 7 +-
arch/mips/boot/dts/loongson/Makefile | 1 +
.../boot/dts/loongson/loongson64-2k1000.dtsi | 243 ++++++++++++
.../dts/loongson/loongson64_2core_2k1000.dts | 10 +
arch/mips/configs/loongson2k_defconfig | 353 ++++++++++++++++++
.../include/asm/mach-loongson64/boot_param.h | 6 +
.../asm/mach-loongson64/builtin_dtbs.h | 1 +
.../include/asm/mach-loongson64/loongson.h | 3 +-
arch/mips/loongson64/env.c | 13 +-
arch/mips/loongson64/init.c | 21 +-
arch/mips/loongson64/time.c | 20 +
drivers/irqchip/irq-loongson-liointc.c | 55 ++-
12 files changed, 716 insertions(+), 17 deletions(-)
create mode 100644 arch/mips/boot/dts/loongson/loongson64-2k1000.dtsi
create mode 100644 arch/mips/boot/dts/loongson/loongson64_2core_2k1000.dts
create mode 100644 arch/mips/configs/loongson2k_defconfig
--
2.20.1
Add liointc-2.0 properties support, so update the maxItems and description.
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Qing Zhang <[email protected]>
---
v2-v3: Fix warnings/errors abount running 'make dt_binding_check'
.../bindings/interrupt-controller/loongson,liointc.yaml | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
index f38e0113f360..5280cf60a9a7 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/loongson,liointc.yaml
@@ -10,9 +10,9 @@ maintainers:
- Jiaxun Yang <[email protected]>
description: |
- This interrupt controller is found in the Loongson-3 family of chips as the primary
- package interrupt controller which can route local I/O interrupt to interrupt lines
- of cores.
+ This interrupt controller is found in the Loongson-3 family of chips and
+ Loongson-2K1000 chip, as the primary package interrupt controller which
+ can route local I/O interrupt to interrupt lines of cores.
allOf:
- $ref: /schemas/interrupt-controller.yaml#
@@ -22,6 +22,7 @@ properties:
oneOf:
- const: loongson,liointc-1.0
- const: loongson,liointc-1.0a
+ - const: loongson,liointc-2.0
reg:
maxItems: 1
--
2.20.1
Distinguish between 3A series CPU and 2K1000 CPU UART0.
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Qing Zhang <[email protected]>
---
v2-v3: No change
arch/mips/loongson64/init.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/mips/loongson64/init.c b/arch/mips/loongson64/init.c
index ed280b73bf89..d5a1eddb8202 100644
--- a/arch/mips/loongson64/init.c
+++ b/arch/mips/loongson64/init.c
@@ -120,7 +120,10 @@ void __init prom_init(void)
#endif
/* Hardcode to CPU UART 0 */
- setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE + 0x1e0), 0, 1024);
+ if ((read_c0_prid() & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
+ setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE), 0, 1024);
+ else
+ setup_8250_early_printk_port(TO_UNCAC(LOONGSON_REG_BASE + 0x1e0), 0, 1024);
register_smp_ops(&loongson3_smp_ops);
board_nmi_handler_setup = mips_nmi_setup;
--
2.20.1
Get the fixed-clock from the CPU0 node of the device tree.
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Qing Zhang <[email protected]>
---
v2-v3: Add error process
arch/mips/loongson64/time.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/mips/loongson64/time.c b/arch/mips/loongson64/time.c
index 91e842b58365..84f01424c8c0 100644
--- a/arch/mips/loongson64/time.c
+++ b/arch/mips/loongson64/time.c
@@ -11,9 +11,29 @@
#include <asm/hpet.h>
#include <loongson.h>
+#include <linux/clk.h>
+#include <linux/of_clk.h>
void __init plat_time_init(void)
{
+ struct clk *clk = NULL;
+ struct device_node *np;
+
+ if (loongson_sysconf.fw_interface != LOONGSON_LEFI) {
+ of_clk_init(NULL);
+
+ np = of_get_cpu_node(0, NULL);
+ if (!np)
+ pr_err("Failed to get CPU node\n");
+
+ clk = of_clk_get(np, 0);
+ if (IS_ERR(clk))
+ pr_err("Failed to get CPU clock: %ld\n", PTR_ERR(clk));
+
+ cpu_clock_freq = clk_get_rate(clk);
+ clk_put(clk);
+ }
+
/* setup mips r4k timer */
mips_hpt_frequency = cpu_clock_freq / 2;
--
2.20.1
Add IO interrupt controller support for Loongson 2k1000, different
from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
correspond to the device tree liointc0 device node, and the other
correspond to liointc1 node.
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Qing Zhang <[email protected]>
---
v2-v3: No change
drivers/irqchip/irq-loongson-liointc.c | 55 +++++++++++++++++++++-----
1 file changed, 46 insertions(+), 9 deletions(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 09b91b81851c..1c3c80f7f9f5 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -20,6 +20,7 @@
#define LIOINTC_CHIP_IRQ 32
#define LIOINTC_NUM_PARENT 4
+#define LIOINTC_NUM_CORES 4
#define LIOINTC_INTC_CHIP_START 0x20
@@ -42,6 +43,7 @@ struct liointc_handler_data {
struct liointc_priv {
struct irq_chip_generic *gc;
struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
+ void __iomem *core_isr[LIOINTC_NUM_CORES];
u8 map_cache[LIOINTC_CHIP_IRQ];
bool has_lpc_irq_errata;
};
@@ -51,11 +53,12 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_chip_generic *gc = handler->priv->gc;
+ int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;
u32 pending;
chained_irq_enter(chip, desc);
- pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
+ pending = readl(handler->priv->core_isr[core]);
if (!pending) {
/* Always blame LPC IRQ if we have that bug */
@@ -141,6 +144,15 @@ static void liointc_resume(struct irq_chip_generic *gc)
}
static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
+static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
+
+static void __iomem *liointc_get_reg_byname(struct device_node *node,
+ const char *name)
+{
+ int index = of_property_match_string(node, "reg-names", name);
+
+ return of_iomap(node, index);
+}
static int __init liointc_of_init(struct device_node *node,
struct device_node *parent)
@@ -159,10 +171,28 @@ static int __init liointc_of_init(struct device_node *node,
if (!priv)
return -ENOMEM;
- base = of_iomap(node, 0);
- if (!base) {
- err = -ENODEV;
- goto out_free_priv;
+ if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
+ base = liointc_get_reg_byname(node, "main");
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+ for (i = 0; i < LIOINTC_NUM_CORES; i++) {
+ priv->core_isr[i] =
+ liointc_get_reg_byname(node, core_reg_names[i]);
+ }
+ if (!priv->core_isr[0]) {
+ err = -ENODEV;
+ goto out_iounmap_base;
+ }
+ } else {
+ base = of_iomap(node, 0);
+ if (!base) {
+ err = -ENODEV;
+ goto out_free_priv;
+ }
+ for (i = 0; i < LIOINTC_NUM_CORES; i++)
+ priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
}
for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
@@ -172,7 +202,7 @@ static int __init liointc_of_init(struct device_node *node,
}
if (!have_parent) {
err = -ENODEV;
- goto out_iounmap;
+ goto out_iounmap_isr;
}
sz = of_property_read_variable_u32_array(node,
@@ -183,7 +213,7 @@ static int __init liointc_of_init(struct device_node *node,
if (sz < 4) {
pr_err("loongson-liointc: No parent_int_map\n");
err = -ENODEV;
- goto out_iounmap;
+ goto out_iounmap_isr;
}
for (i = 0; i < LIOINTC_NUM_PARENT; i++)
@@ -195,7 +225,7 @@ static int __init liointc_of_init(struct device_node *node,
if (!domain) {
pr_err("loongson-liointc: cannot add IRQ domain\n");
err = -EINVAL;
- goto out_iounmap;
+ goto out_iounmap_isr;
}
err = irq_alloc_domain_generic_chips(domain, 32, 1,
@@ -260,7 +290,13 @@ static int __init liointc_of_init(struct device_node *node,
out_free_domain:
irq_domain_remove(domain);
-out_iounmap:
+out_iounmap_isr:
+ for (i = 0; i < LIOINTC_NUM_CORES; i++) {
+ if (!priv->core_isr[i])
+ continue;
+ iounmap(priv->core_isr[i]);
+ }
+out_iounmap_base:
iounmap(base);
out_free_priv:
kfree(priv);
@@ -270,3 +306,4 @@ static int __init liointc_of_init(struct device_node *node,
IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
+IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
--
2.20.1
Add default config for 2K1000.
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Qing Zhang <[email protected]>
---
v2-v3: No change
arch/mips/configs/loongson2k_defconfig | 353 +++++++++++++++++++++++++
1 file changed, 353 insertions(+)
create mode 100644 arch/mips/configs/loongson2k_defconfig
diff --git a/arch/mips/configs/loongson2k_defconfig b/arch/mips/configs/loongson2k_defconfig
new file mode 100644
index 000000000000..e948ca487e2d
--- /dev/null
+++ b/arch/mips/configs/loongson2k_defconfig
@@ -0,0 +1,353 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AUDIT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_MACH_LOONGSON64=y
+# CONFIG_CPU_LOONGSON3_CPUCFG_EMULATION is not set
+CONFIG_HZ_256=y
+CONFIG_MIPS32_O32=y
+CONFIG_MIPS32_N32=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_MQ_IOSCHED_DEADLINE=m
+CONFIG_IOSCHED_BFQ=y
+CONFIG_BFQ_GROUP_IOSCHED=y
+CONFIG_BINFMT_MISC=m
+CONFIG_KSM=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM_USER=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_IP_VS=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_IP_SCTP=m
+CONFIG_L2TP=m
+CONFIG_BRIDGE=m
+CONFIG_CFG80211=m
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=m
+CONFIG_RFKILL=m
+CONFIG_RFKILL_INPUT=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCIEASPM_PERFORMANCE=y
+CONFIG_HOTPLUG_PCI=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=m
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_RAID_ATTRS=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SPI_ATTRS=m
+CONFIG_SCSI_FC_ATTRS=m
+CONFIG_ISCSI_TCP=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=y
+CONFIG_MEGARAID_MAILBOX=y
+CONFIG_MEGARAID_LEGACY=y
+CONFIG_MEGARAID_SAS=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_PATA_ATIIXP=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=m
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_ZERO=m
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_NETDEVICES=y
+CONFIG_TUN=m
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_I825XX is not set
+CONFIG_E1000=y
+CONFIG_E1000E=y
+CONFIG_IGB=y
+CONFIG_IXGB=y
+CONFIG_IXGBE=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MICROSEMI is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETERION is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_NI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set
+# CONFIG_NET_VENDOR_PENSANDO is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RDC is not set
+CONFIG_8139CP=y
+CONFIG_8139TOO=y
+# CONFIG_8139TOO_PIO is not set
+CONFIG_R8169=y
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SOLARFLARE is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+CONFIG_STMMAC_ETH=y
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_TOSHIBA is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_PPP=m
+CONFIG_PPP_BSDCOMP=m
+CONFIG_PPP_DEFLATE=m
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_MPPE=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPPOE=m
+CONFIG_PPPOL2TP=m
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_ATH9K=m
+CONFIG_HOSTAP=m
+CONFIG_INPUT_LEDS=m
+CONFIG_INPUT_SPARSEKMAP=y
+CONFIG_INPUT_EVDEV=y
+# CONFIG_KEYBOARD_ATKBD is not set
+CONFIG_KEYBOARD_XTKBD=m
+# CONFIG_MOUSE_PS2 is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_UINPUT=m
+# CONFIG_SERIO_I8042 is not set
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=16
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_HW_RANDOM=y
+CONFIG_RAW_DRIVER=m
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_PIIX4=y
+CONFIG_GPIO_LOONGSON=y
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_W83627HF=m
+# CONFIG_MEDIA_CEC_SUPPORT is not set
+CONFIG_MEDIA_SUPPORT=m
+# CONFIG_MEDIA_CONTROLLER is not set
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_VIDEO_CLASS=m
+CONFIG_DRM=y
+CONFIG_DRM_RADEON=y
+CONFIG_FB_RADEON=y
+CONFIG_LCD_CLASS_DEVICE=y
+CONFIG_LCD_PLATFORM=m
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_LOGO=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_VERBOSE_PRINTK=y
+CONFIG_SND_SEQUENCER=y
+CONFIG_SND_SEQ_DUMMY=m
+# CONFIG_SND_ISA is not set
+CONFIG_SND_HDA_INTEL=y
+CONFIG_SND_HDA_HWDEP=y
+CONFIG_SND_HDA_PATCH_LOADER=y
+CONFIG_SND_HDA_CODEC_REALTEK=y
+CONFIG_SND_HDA_CODEC_ANALOG=y
+CONFIG_SND_HDA_CODEC_SIGMATEL=y
+CONFIG_SND_HDA_CODEC_VIA=y
+CONFIG_SND_HDA_CODEC_CONEXANT=y
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_HID_A4TECH=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_UHCI_HCD=m
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_OPTION=m
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_CMOS=y
+CONFIG_DMADEVICES=y
+# CONFIG_CPU_HWMON is not set
+CONFIG_PM_DEVFREQ=y
+CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y
+CONFIG_DEVFREQ_GOV_PERFORMANCE=y
+CONFIG_DEVFREQ_GOV_POWERSAVE=y
+CONFIG_DEVFREQ_GOV_USERSPACE=y
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_XFS_FS=y
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+CONFIG_QUOTA=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+CONFIG_AUTOFS4_FS=y
+CONFIG_FUSE_FS=m
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_FAT_DEFAULT_CODEPAGE=936
+CONFIG_FAT_DEFAULT_IOCHARSET="gb2312"
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_CONFIGFS_FS=y
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=m
+CONFIG_NFSD=m
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_CIFS=m
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_936=y
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_UTF8=y
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_PATH=y
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_CRYPTO_SEQIV=m
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_PRINTK_TIME=y
+CONFIG_FRAME_WARN=1024
+CONFIG_STRIP_ASM_SYMS=y
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_DEBUG_PREEMPT is not set
+# CONFIG_FTRACE is not set
--
2.20.1
Hi, Qing,
On Sat, Mar 6, 2021 at 10:36 AM Qing Zhang <[email protected]> wrote:
>
> Add IO interrupt controller support for Loongson 2k1000, different
> from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
> correspond to the device tree liointc0 device node, and the other
> correspond to liointc1 node.
Use the formal name (Loongson-2K1000, Loongson-3A series), please.
Huacai
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
> ---
>
> v2-v3: No change
>
> drivers/irqchip/irq-loongson-liointc.c | 55 +++++++++++++++++++++-----
> 1 file changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 09b91b81851c..1c3c80f7f9f5 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -20,6 +20,7 @@
>
> #define LIOINTC_CHIP_IRQ 32
> #define LIOINTC_NUM_PARENT 4
> +#define LIOINTC_NUM_CORES 4
>
> #define LIOINTC_INTC_CHIP_START 0x20
>
> @@ -42,6 +43,7 @@ struct liointc_handler_data {
> struct liointc_priv {
> struct irq_chip_generic *gc;
> struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
> + void __iomem *core_isr[LIOINTC_NUM_CORES];
> u8 map_cache[LIOINTC_CHIP_IRQ];
> bool has_lpc_irq_errata;
> };
> @@ -51,11 +53,12 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
> struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct irq_chip_generic *gc = handler->priv->gc;
> + int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;
> u32 pending;
>
> chained_irq_enter(chip, desc);
>
> - pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
> + pending = readl(handler->priv->core_isr[core]);
>
> if (!pending) {
> /* Always blame LPC IRQ if we have that bug */
> @@ -141,6 +144,15 @@ static void liointc_resume(struct irq_chip_generic *gc)
> }
>
> static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
> +static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
> +
> +static void __iomem *liointc_get_reg_byname(struct device_node *node,
> + const char *name)
> +{
> + int index = of_property_match_string(node, "reg-names", name);
> +
> + return of_iomap(node, index);
> +}
>
> static int __init liointc_of_init(struct device_node *node,
> struct device_node *parent)
> @@ -159,10 +171,28 @@ static int __init liointc_of_init(struct device_node *node,
> if (!priv)
> return -ENOMEM;
>
> - base = of_iomap(node, 0);
> - if (!base) {
> - err = -ENODEV;
> - goto out_free_priv;
> + if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
> + base = liointc_get_reg_byname(node, "main");
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> + priv->core_isr[i] =
> + liointc_get_reg_byname(node, core_reg_names[i]);
> + }
> + if (!priv->core_isr[0]) {
> + err = -ENODEV;
> + goto out_iounmap_base;
> + }
> + } else {
> + base = of_iomap(node, 0);
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> + for (i = 0; i < LIOINTC_NUM_CORES; i++)
> + priv->core_isr[i] = base + LIOINTC_REG_INTC_STATUS;
> }
>
> for (i = 0; i < LIOINTC_NUM_PARENT; i++) {
> @@ -172,7 +202,7 @@ static int __init liointc_of_init(struct device_node *node,
> }
> if (!have_parent) {
> err = -ENODEV;
> - goto out_iounmap;
> + goto out_iounmap_isr;
> }
>
> sz = of_property_read_variable_u32_array(node,
> @@ -183,7 +213,7 @@ static int __init liointc_of_init(struct device_node *node,
> if (sz < 4) {
> pr_err("loongson-liointc: No parent_int_map\n");
> err = -ENODEV;
> - goto out_iounmap;
> + goto out_iounmap_isr;
> }
>
> for (i = 0; i < LIOINTC_NUM_PARENT; i++)
> @@ -195,7 +225,7 @@ static int __init liointc_of_init(struct device_node *node,
> if (!domain) {
> pr_err("loongson-liointc: cannot add IRQ domain\n");
> err = -EINVAL;
> - goto out_iounmap;
> + goto out_iounmap_isr;
> }
>
> err = irq_alloc_domain_generic_chips(domain, 32, 1,
> @@ -260,7 +290,13 @@ static int __init liointc_of_init(struct device_node *node,
>
> out_free_domain:
> irq_domain_remove(domain);
> -out_iounmap:
> +out_iounmap_isr:
> + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> + if (!priv->core_isr[i])
> + continue;
> + iounmap(priv->core_isr[i]);
> + }
> +out_iounmap_base:
> iounmap(base);
> out_free_priv:
> kfree(priv);
> @@ -270,3 +306,4 @@ static int __init liointc_of_init(struct device_node *node,
>
> IRQCHIP_DECLARE(loongson_liointc_1_0, "loongson,liointc-1.0", liointc_of_init);
> IRQCHIP_DECLARE(loongson_liointc_1_0a, "loongson,liointc-1.0a", liointc_of_init);
> +IRQCHIP_DECLARE(loongson_liointc_2_0, "loongson,liointc-2.0", liointc_of_init);
> --
> 2.20.1
>
On 03/06/2021 11:06 AM, Huacai Chen wrote:
> Hi, Qing,
>
> On Sat, Mar 6, 2021 at 10:36 AM Qing Zhang <[email protected]> wrote:
>> Add IO interrupt controller support for Loongson 2k1000, different
>> from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
>> correspond to the device tree liointc0 device node, and the other
>> correspond to liointc1 node.
> Use the formal name (Loongson-2K1000, Loongson-3A series), please.
Hi, Huacai
Thank you very much for your reply.
I will modify the submission information,
Use the formal name (Loongson-2K1000, Loongson-3A series) in v4,
Before that, I will wait for other people's opinions about this series.
Thanks,
Qing
>
> Huacai
On 03/06/2021 10:36 AM, Qing Zhang wrote:
> Get the fixed-clock from the CPU0 node of the device tree.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
Tested-by: Ming Wang <[email protected]>
Thanks,
Ming
On 03/06/2021 10:36 AM, Qing Zhang wrote:
> Distinguish between 3A series CPU and 2K1000 CPU UART0.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
Tested-by: Ming Wang <[email protected]>
Thanks,
Ming
On 03/06/2021 10:36 AM, Qing Zhang wrote:
> Add default config for 2K1000.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
Tested-by: Ming Wang <[email protected]>
Thanks,
Ming
On 03/06/2021 10:36 AM, Qing Zhang wrote:
> Add IO interrupt controller support for Loongson 2k1000, different
> from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
> correspond to the device tree liointc0 device node, and the other
> correspond to liointc1 node.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
Tested-by: Ming Wang <[email protected]>
Thanks,
Ming
On 03/06/2021 10:36 AM, Qing Zhang wrote:
> Add liointc-2.0 properties support, so update the maxItems and description.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
Tested-by: Ming Wang <[email protected]>
Thanks,
Ming
On Sat, 06 Mar 2021 02:36:31 +0000,
Qing Zhang <[email protected]> wrote:
>
> Add IO interrupt controller support for Loongson 2k1000, different
> from the 3a series is that 2K1000 has 64 interrupt sources, 0-31
> correspond to the device tree liointc0 device node, and the other
> correspond to liointc1 node.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> Signed-off-by: Qing Zhang <[email protected]>
> ---
>
> v2-v3: No change
>
> drivers/irqchip/irq-loongson-liointc.c | 55 +++++++++++++++++++++-----
> 1 file changed, 46 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 09b91b81851c..1c3c80f7f9f5 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -20,6 +20,7 @@
>
> #define LIOINTC_CHIP_IRQ 32
> #define LIOINTC_NUM_PARENT 4
> +#define LIOINTC_NUM_CORES 4
>
> #define LIOINTC_INTC_CHIP_START 0x20
>
> @@ -42,6 +43,7 @@ struct liointc_handler_data {
> struct liointc_priv {
> struct irq_chip_generic *gc;
> struct liointc_handler_data handler[LIOINTC_NUM_PARENT];
> + void __iomem *core_isr[LIOINTC_NUM_CORES];
> u8 map_cache[LIOINTC_CHIP_IRQ];
> bool has_lpc_irq_errata;
> };
> @@ -51,11 +53,12 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
> struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
> struct irq_chip *chip = irq_desc_get_chip(desc);
> struct irq_chip_generic *gc = handler->priv->gc;
> + int core = get_ebase_cpunum() % LIOINTC_NUM_CORES;
> u32 pending;
>
> chained_irq_enter(chip, desc);
>
> - pending = readl(gc->reg_base + LIOINTC_REG_INTC_STATUS);
> + pending = readl(handler->priv->core_isr[core]);
>
> if (!pending) {
> /* Always blame LPC IRQ if we have that bug */
> @@ -141,6 +144,15 @@ static void liointc_resume(struct irq_chip_generic *gc)
> }
>
> static const char * const parent_names[] = {"int0", "int1", "int2", "int3"};
> +static const char * const core_reg_names[] = {"isr0", "isr1", "isr2", "isr3"};
> +
> +static void __iomem *liointc_get_reg_byname(struct device_node *node,
> + const char *name)
> +{
> + int index = of_property_match_string(node, "reg-names", name);
> +
> + return of_iomap(node, index);
So if of_property_match_string() returns an error, you feed that error
to of_iomap()? Somehow, I don't think that's a good idea.
> +}
>
> static int __init liointc_of_init(struct device_node *node,
> struct device_node *parent)
> @@ -159,10 +171,28 @@ static int __init liointc_of_init(struct device_node *node,
> if (!priv)
> return -ENOMEM;
>
> - base = of_iomap(node, 0);
> - if (!base) {
> - err = -ENODEV;
> - goto out_free_priv;
> + if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
> + base = liointc_get_reg_byname(node, "main");
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> + priv->core_isr[i] =
> + liointc_get_reg_byname(node, core_reg_names[i]);
Please write assignments on a single line.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On 03/09/2021 05:10 PM, Marc Zyngier wrote:
>
>> +
>> +static void __iomem *liointc_get_reg_byname(struct device_node *node,
>> + const char *name)
>> +{
>> + int index = of_property_match_string(node, "reg-names", name);
>> +
>> + return of_iomap(node, index);
> So if of_property_match_string() returns an error, you feed that error
> to of_iomap()? Somehow, I don't think that's a good idea.
Hi, Marc
Thank you for your suggestion, error handling is missing here,
+ if (index <0)
+ return NULL;
return of_iomap(node, index);
It has been fixed in the fourth version, and I will send V4 soon.
> + if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
> + base = liointc_get_reg_byname(node, "main");
> + if (!base) {
> + err = -ENODEV;
> + goto out_free_priv;
> + }
> + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> + priv->core_isr[i] =
> + liointc_get_reg_byname(node, core_reg_names[i]);
> Please write assignments on a single line.
In addition, write assignments on a single line
for (i = 0; i <LIOINTC_NUM_CORES; i++)
priv->core_isr[i] =
liointc_get_reg_byname(node, core_reg_names[i]);
It is 92 characters, more than 80 characters...
Thanks
-Qing
>
> Thanks,
>
> M.
>
Hello!
On 10.03.2021 5:26, zhangqing wrote:
[...]
>> + if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
>> + base = liointc_get_reg_byname(node, "main");
>> + if (!base) {
>> + err = -ENODEV;
>> + goto out_free_priv;
>> + }
>> + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
>> + priv->core_isr[i] =
>> + liointc_get_reg_byname(node, core_reg_names[i]);
>> Please write assignments on a single line.
>
> In addition, write assignments on a single line
>
> for (i = 0; i <LIOINTC_NUM_CORES; i++)
> priv->core_isr[i] = liointc_get_reg_byname(node,
> core_reg_names[i]);
>
> It is 92 characters, more than 80 characters...
The new line length limit is 100 chars. :-)
[...]
MBR, Sergei
On Wed, 10 Mar 2021 02:26:24 +0000,
zhangqing <[email protected]> wrote:
>
>
> On 03/09/2021 05:10 PM, Marc Zyngier wrote:
> >
> >> +
> >> +static void __iomem *liointc_get_reg_byname(struct device_node *node,
> >> + const char *name)
> >> +{
> >> + int index = of_property_match_string(node, "reg-names", name);
> >> +
> >> + return of_iomap(node, index);
> > So if of_property_match_string() returns an error, you feed that error
> > to of_iomap()? Somehow, I don't think that's a good idea.
>
> Hi, Marc
>
> Thank you for your suggestion, error handling is missing here,
>
> + if (index <0)
> + return NULL;
>
> return of_iomap(node, index);
>
> It has been fixed in the fourth version, and I will send V4 soon.
>
> > + if (of_device_is_compatible(node, "loongson,liointc-2.0")) {
> > + base = liointc_get_reg_byname(node, "main");
> > + if (!base) {
> > + err = -ENODEV;
> > + goto out_free_priv;
> > + }
> > + for (i = 0; i < LIOINTC_NUM_CORES; i++) {
> > + priv->core_isr[i] =
> > + liointc_get_reg_byname(node, core_reg_names[i]);
> > Please write assignments on a single line.
>
> In addition, write assignments on a single line
>
> for (i = 0; i <LIOINTC_NUM_CORES; i++)
> priv->core_isr[i] =
> liointc_get_reg_byname(node, core_reg_names[i]);
>
> It is 92 characters, more than 80 characters...
I really don't care about whatever arbitrary limit people think there
is. Please put it on a single line.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
On 03/10/2021 04:47 PM, Sergei Shtylyov wrote:
> Hello!
>
> The new line length limit is 100 chars. :-)
Hi,Sergei
Thank you for your reply, I saw it
my $max_line_length = 100;
Soalready fixed it in v4:).
Thanks,
Qing
>
>
> MBR, Sergei
> I really don't care about whatever arbitrary limit people think there
> is. Please put it on a single line.
Hi,Marc
Thank you for your reply, I saw it
my $max_line_length = 100;
So already fixed it in v4:).
Thanks,
Qing
>
> Thanks,
>
> M.
>