IBS Op data3 provides data cache miss latency which can be passed as
sample->weight along with perf_mem_data_src. Note that sample->weight
will be populated only when PERF_SAMPLE_DATA_SRC is also set, although
both sample types are independent.
Signed-off-by: Ravi Bangoria <[email protected]>
---
arch/x86/events/amd/ibs.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index 6626caeed6a1..5a6e278713f4 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -738,6 +738,12 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, u64 op_data2,
return;
}
+ /* Load latency (Data cache miss latency) */
+ if (data_src->mem_op == PERF_MEM_OP_LOAD &&
+ event->attr.sample_type & PERF_SAMPLE_WEIGHT) {
+ data->weight.full = (op_data3 & IBS_DC_MISS_LAT_MASK) >> IBS_DC_MISS_LAT_SHIFT;
+ }
+
/* L2 Hit */
if ((op_data3 & IBS_L2_MISS_MASK) == 0) {
/* Erratum #1293 */
--
2.31.1
On Wed, May 25, 2022 at 12:42 PM Ravi Bangoria <[email protected]> wrote:
>
> IBS Op data3 provides data cache miss latency which can be passed as
> sample->weight along with perf_mem_data_src. Note that sample->weight
> will be populated only when PERF_SAMPLE_DATA_SRC is also set, although
> both sample types are independent.
>
> Signed-off-by: Ravi Bangoria <[email protected]>
> ---
> arch/x86/events/amd/ibs.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
> index 6626caeed6a1..5a6e278713f4 100644
> --- a/arch/x86/events/amd/ibs.c
> +++ b/arch/x86/events/amd/ibs.c
> @@ -738,6 +738,12 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, u64 op_data2,
> return;
> }
>
> + /* Load latency (Data cache miss latency) */
> + if (data_src->mem_op == PERF_MEM_OP_LOAD &&
> + event->attr.sample_type & PERF_SAMPLE_WEIGHT) {
> + data->weight.full = (op_data3 & IBS_DC_MISS_LAT_MASK) >> IBS_DC_MISS_LAT_SHIFT;
> + }
> +
I think here you also need to handle the WEIGHT_STRUCT case and put
the cache miss latency in the right
field. This IBS field covers the cache line movement and not the whole
instruction latency which is the tag to ret field.
In the case of WEIGHT_STRUCT you need to fill out the two fields.
> /* L2 Hit */
> if ((op_data3 & IBS_L2_MISS_MASK) == 0) {
> /* Erratum #1293 */
> --
> 2.31.1
>
On 25-May-22 6:28 PM, Stephane Eranian wrote:
> On Wed, May 25, 2022 at 12:42 PM Ravi Bangoria <[email protected]> wrote:
>>
>> IBS Op data3 provides data cache miss latency which can be passed as
>> sample->weight along with perf_mem_data_src. Note that sample->weight
>> will be populated only when PERF_SAMPLE_DATA_SRC is also set, although
>> both sample types are independent.
>>
>> Signed-off-by: Ravi Bangoria <[email protected]>
>> ---
>> arch/x86/events/amd/ibs.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
>> index 6626caeed6a1..5a6e278713f4 100644
>> --- a/arch/x86/events/amd/ibs.c
>> +++ b/arch/x86/events/amd/ibs.c
>> @@ -738,6 +738,12 @@ static void perf_ibs_get_mem_lvl(struct perf_event *event, u64 op_data2,
>> return;
>> }
>>
>> + /* Load latency (Data cache miss latency) */
>> + if (data_src->mem_op == PERF_MEM_OP_LOAD &&
>> + event->attr.sample_type & PERF_SAMPLE_WEIGHT) {
>> + data->weight.full = (op_data3 & IBS_DC_MISS_LAT_MASK) >> IBS_DC_MISS_LAT_SHIFT;
>> + }
>> +
> I think here you also need to handle the WEIGHT_STRUCT case and put
> the cache miss latency in the right
> field. This IBS field covers the cache line movement and not the whole
> instruction latency which is the tag to ret field.
> In the case of WEIGHT_STRUCT you need to fill out the two fields.
Yeah, will do. Thanks for pointing it.
-Ravi