2012-08-20 09:22:27

by Stephane Eranian

Subject: [PATCH] perf/x86: enable Intel Cedarview Atom suppport

This patch enables perf_events support for Intel Cedarview
Atom (model 54) processors. Support includes PEBS and LBR.
Tested on my Atom N2600 netbook.

Signed-off-by: Stephane Eranian <[email protected]>
---

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index 7f2739e..0d3d63a 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
break;

case 28: /* Atom */
+ case 54: /* Cedariew */
memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
sizeof(hw_cache_event_ids));

diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
index 520b426..da02e9c 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
@@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
* to have an operational LBR which can freeze
* on PMU interrupt
*/
- if (boot_cpu_data.x86_mask < 10) {
+ if (boot_cpu_data.x86_model == 28
+ && boot_cpu_data.x86_mask < 10) {
pr_cont("LBR disabled due to erratum");
return;
}

2012-08-20 09:41:47

by Andi Kleen

Subject: Re: [PATCH] perf/x86: enable Intel Cedarview Atom suppport

> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
> index 7f2739e..0d3d63a 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
> break;
>
> case 28: /* Atom */
> + case 54: /* Cedariew */

Ack. We currently miss some more 32nm Atoms too, will send patches soon.

> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
> sizeof(hw_cache_event_ids));
>
> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> index 520b426..da02e9c 100644
> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
> * to have an operational LBR which can freeze
> * on PMU interrupt
> */
> - if (boot_cpu_data.x86_mask < 10) {
> + if (boot_cpu_data.x86_model == 28
> + && boot_cpu_data.x86_mask < 10) {

Is that correct?

-Andi

--
[email protected] -- Speaking for myself only.

2012-08-20 10:06:47

by Stephane Eranian

Subject: Re: [PATCH] perf/x86: enable Intel Cedarview Atom suppport

On Mon, Aug 20, 2012 at 11:41 AM, Andi Kleen <[email protected]> wrote:
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
>> index 7f2739e..0d3d63a 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>> @@ -2008,6 +2008,7 @@ __init int intel_pmu_init(void)
>> break;
>>
>> case 28: /* Atom */
>> + case 54: /* Cedariew */
>
> Ack. We currently miss some more 32nm Atoms too, will send patches soon.
>
>> memcpy(hw_cache_event_ids, atom_hw_cache_event_ids,
>> sizeof(hw_cache_event_ids));
>>
>> diff --git a/arch/x86/kernel/cpu/perf_event_intel_lbr.c b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> index 520b426..da02e9c 100644
>> --- a/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> +++ b/arch/x86/kernel/cpu/perf_event_intel_lbr.c
>> @@ -686,7 +686,8 @@ void intel_pmu_lbr_init_atom(void)
>> * to have an operational LBR which can freeze
>> * on PMU interrupt
>> */
>> - if (boot_cpu_data.x86_mask < 10) {
>> + if (boot_cpu_data.x86_model == 28
>> + && boot_cpu_data.x86_mask < 10) {
>
> Is that correct?
>
Yes, had to do that to re-enable LBR on Cedarview.
The < 10 is a trick to disable LBR on very old Atom (prior to N4xx generation).