Hello,
This patch series contains a few small device-tree updates for ASRock
BMCs: an LED polarity fix for romed8hm3, enabling the ast2500 PECI
device on e3c246d4i, and a SPI flash clock frequency fix for both.
Thanks,
Zev
Changes since v1 [0]:
- Added patch 3 correcting SPI flash clocks
[0] https://lore.kernel.org/linux-devicetree/[email protected]/
Zev Weiss (3):
ARM: dts: aspeed: romed8hm3: Fix GPIO polarity of system-fault LED
ARM: dts: aspeed: e3c246d4i: Add PECI device
ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 6 +++++-
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 4 ++--
2 files changed, 7 insertions(+), 3 deletions(-)
--
2.39.1.438.gdcb075ea9396.dirty
Now that we've got driver support for it, we might as well enable and
use it.
Signed-off-by: Zev Weiss <[email protected]>
---
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index 9b4cf5ebe6d5..67a75aeafc2b 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -202,3 +202,7 @@ &kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
+
+&peci0 {
+ status = "okay";
+};
--
2.39.1.438.gdcb075ea9396.dirty
While I'm not aware of any problems that have occurred running these
at 100 MHz, the official word from ASRock is that 50 MHz is the
correct speed to use, so let's be safe and use that instead.
Signed-off-by: Zev Weiss <[email protected]>
Cc: [email protected]
Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
---
arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +-
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
index 67a75aeafc2b..c4b2efbfdf56 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
@@ -63,7 +63,7 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-max-frequency = <100000000>; /* 100 MHz */
+ spi-max-frequency = <50000000>; /* 50 MHz */
#include "openbmc-flash-layout.dtsi"
};
};
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index 00efe1a93a69..4554abf0c7cd 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -51,7 +51,7 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
- spi-max-frequency = <100000000>; /* 100 MHz */
+ spi-max-frequency = <50000000>; /* 50 MHz */
#include "openbmc-flash-layout-64.dtsi"
};
};
--
2.39.1.438.gdcb075ea9396.dirty
On Fri, 24 Feb 2023 at 00:04, Zev Weiss <[email protected]> wrote:
>
> While I'm not aware of any problems that have occurred running these
> at 100 MHz, the official word from ASRock is that 50 MHz is the
> correct speed to use, so let's be safe and use that instead.
:(
Validated with which driver?
Cédric, do you have any thoughts on this?
>
> Signed-off-by: Zev Weiss <[email protected]>
> Cc: [email protected]
> Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
> Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> index 67a75aeafc2b..c4b2efbfdf56 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
> @@ -63,7 +63,7 @@ flash@0 {
> status = "okay";
> m25p,fast-read;
> label = "bmc";
> - spi-max-frequency = <100000000>; /* 100 MHz */
> + spi-max-frequency = <50000000>; /* 50 MHz */
> #include "openbmc-flash-layout.dtsi"
> };
> };
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index 00efe1a93a69..4554abf0c7cd 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -51,7 +51,7 @@ flash@0 {
> status = "okay";
> m25p,fast-read;
> label = "bmc";
> - spi-max-frequency = <100000000>; /* 100 MHz */
> + spi-max-frequency = <50000000>; /* 50 MHz */
> #include "openbmc-flash-layout-64.dtsi"
> };
> };
> --
> 2.39.1.438.gdcb075ea9396.dirty
>
On Fri, 24 Feb 2023 at 00:04, Zev Weiss <[email protected]> wrote:
>
> Hello,
>
> This patch series contains a few small device-tree updates for ASRock
> BMCs: an LED polarity fix for romed8hm3, enabling the ast2500 PECI
> device on e3c246d4i, and a SPI flash clock frequency fix for both.
Thanks. I'll apply these once we have a -rc1.
Cheers,
Joel
>
> Thanks,
> Zev
>
> Changes since v1 [0]:
> - Added patch 3 correcting SPI flash clocks
>
> [0] https://lore.kernel.org/linux-devicetree/[email protected]/
>
> Zev Weiss (3):
> ARM: dts: aspeed: romed8hm3: Fix GPIO polarity of system-fault LED
> ARM: dts: aspeed: e3c246d4i: Add PECI device
> ARM: dts: aspeed: asrock: Correct firmware flash SPI clocks
>
> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 6 +++++-
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 4 ++--
> 2 files changed, 7 insertions(+), 3 deletions(-)
>
> --
> 2.39.1.438.gdcb075ea9396.dirty
>
On 3/1/23 02:30, Joel Stanley wrote:
> On Fri, 24 Feb 2023 at 00:04, Zev Weiss <[email protected]> wrote:
>>
>> While I'm not aware of any problems that have occurred running these
>> at 100 MHz, the official word from ASRock is that 50 MHz is the
>> correct speed to use, so let's be safe and use that instead.
>
> :(
>
> Validated with which driver?
>
> Cédric, do you have any thoughts on this?
Transactions on the Firmware SPI controller are usually configured at
50MHz by U-Boot and Linux to stay on the safe side, specially CE0 from
which the board boots. The other SPI controllers are generally set at
a higher freq : 100MHz, because the devices on these buses are not for
booting the BMC, they are mostly only written to (at a default lower
freq). There are some exceptions when the devices and the wiring permit
higher rates.
For the record, we lowered the SPI freq on the AST2400 (palmetto)
because some chips would freak out once in a while at 100MHz.
C.
>> Signed-off-by: Zev Weiss <[email protected]>
>> Cc: [email protected]
>> Fixes: 2b81613ce417 ("ARM: dts: aspeed: Add ASRock E3C246D4I BMC")
>> Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
>> ---
>> arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts | 2 +-
>> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
>> 2 files changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
>> index 67a75aeafc2b..c4b2efbfdf56 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts
>> @@ -63,7 +63,7 @@ flash@0 {
>> status = "okay";
>> m25p,fast-read;
>> label = "bmc";
>> - spi-max-frequency = <100000000>; /* 100 MHz */
>> + spi-max-frequency = <50000000>; /* 50 MHz */
>> #include "openbmc-flash-layout.dtsi"
>> };
>> };
>> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
>> index 00efe1a93a69..4554abf0c7cd 100644
>> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
>> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
>> @@ -51,7 +51,7 @@ flash@0 {
>> status = "okay";
>> m25p,fast-read;
>> label = "bmc";
>> - spi-max-frequency = <100000000>; /* 100 MHz */
>> + spi-max-frequency = <50000000>; /* 50 MHz */
>> #include "openbmc-flash-layout-64.dtsi"
>> };
>> };
>> --
>> 2.39.1.438.gdcb075ea9396.dirty
>>
On Tue, Feb 28, 2023 at 11:33:58PM PST, C?dric Le Goater wrote:
>On 3/1/23 02:30, Joel Stanley wrote:
>>On Fri, 24 Feb 2023 at 00:04, Zev Weiss <[email protected]> wrote:
>>>
>>>While I'm not aware of any problems that have occurred running these
>>>at 100 MHz, the official word from ASRock is that 50 MHz is the
>>>correct speed to use, so let's be safe and use that instead.
>>
>>:(
>>
>>Validated with which driver?
>>
spi-nor, FWIW.
>>C?dric, do you have any thoughts on this?
>
>Transactions on the Firmware SPI controller are usually configured at
>50MHz by U-Boot and Linux to stay on the safe side, specially CE0 from
>which the board boots. The other SPI controllers are generally set at
>a higher freq : 100MHz, because the devices on these buses are not for
>booting the BMC, they are mostly only written to (at a default lower
>freq). There are some exceptions when the devices and the wiring permit
>higher rates.
>
>For the record, we lowered the SPI freq on the AST2400 (palmetto)
>because some chips would freak out once in a while at 100MHz.
>
>C.
>
Yeah, this actually grew out of some OpenBMC bringup work on another
ASRock board -- I started out with a 100MHz clock since that's what I'd
been using without a hitch on previous ASRock systems (such as these),
but saw sporadic data corruption. Some discussion on the OpenBMC
Discord
(https://discord.com/channels/775381525260664832/775694683589574659/1074904879023263774
and
https://discord.com/channels/775381525260664832/775694683589574659/1075336116212875335)
prompted me to try 50MHz instead, which seemed to solve the problem --
then after enquiring about it with ASRock I discovered that the 100MHz
clocks we've been using on these boards are also officially out of spec.
Zev