Hi folks,
This short series adds a few quirks needed to make the card readers in
Apple M1 Pro/Max MacBook laptops work properly.
The first patch should be straightforward; it just allows configuring
the CD/WP polarity based on device tree settings. There is already a
standard DT binding for this.
The second patch bugs me. I don't understand why this problem happens
on these machines, and not on e.g. x86 laptops (which presumably work
with this driver). 8/16-bit MMIO reads work fine on other PCIe devices
on these machines, so it is not a generalized problem with the PCIe
controller in these SoCs. The problem also happens when running macOS
(it also uses 32-bit reads). Ben, is there any chance you might know
of some vendor-specific knob somewhere that can fix this issue without
requiring the MMIO read workaround? Interestingly, 8/16-bit writes
work perfectly fine.
Hector Martin (2):
mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF
platforms
mmc: sdhci-pci-gli: GL9755: Issue 8/16-bit MMIO reads as 32-bit reads.
drivers/mmc/host/sdhci-pci-gli.c | 38 ++++++++++++++++++++++++++++++--
1 file changed, 36 insertions(+), 2 deletions(-)
--
2.33.0
This is required on some Apple ARM64 laptops using this controller.
As is typical on DT platforms, pull these quirks from the device tree
using the standard mmc bindings.
See Documentation/devicetree/bindings/mmc/mmc-controller.yaml
Signed-off-by: Hector Martin <[email protected]>
---
drivers/mmc/host/sdhci-pci-gli.c | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index 4fd99c1e82ba..ad742743a494 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -12,6 +12,7 @@
#include <linux/pci.h>
#include <linux/mmc/mmc.h>
#include <linux/delay.h>
+#include <linux/of.h>
#include "sdhci.h"
#include "sdhci-pci.h"
#include "cqhci.h"
@@ -114,8 +115,10 @@
#define GLI_9755_WT_EN_OFF 0x0
#define PCI_GLI_9755_PECONF 0x44
-#define PCI_GLI_9755_LFCLK GENMASK(14, 12)
-#define PCI_GLI_9755_DMACLK BIT(29)
+#define PCI_GLI_9755_LFCLK GENMASK(14, 12)
+#define PCI_GLI_9755_DMACLK BIT(29)
+#define PCI_GLI_9755_INVERT_CD BIT(30)
+#define PCI_GLI_9755_INVERT_WP BIT(31)
#define PCI_GLI_9755_CFG2 0x48
#define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24)
@@ -570,6 +573,18 @@ static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
gl9755_wt_on(pdev);
pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
+#ifdef CONFIG_OF
+ if (pdev->dev.of_node) {
+ /*
+ * Apple ARM64 platforms using these chips may have
+ * inverted CD/WP detection.
+ */
+ if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
+ value |= PCI_GLI_9755_INVERT_CD;
+ if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
+ value |= PCI_GLI_9755_INVERT_WP;
+ }
+#endif
value &= ~PCI_GLI_9755_LFCLK;
value &= ~PCI_GLI_9755_DMACLK;
pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
--
2.33.0
For some reason, <32-bit reads do not work on Apple ARM64 platforms with
these chips (even though they do on other PCIe devices). Issue them as
32-bit reads instead. This is done unconditionally, as it shouldn't hurt
even if not necessary.
Signed-off-by: Hector Martin <[email protected]>
---
drivers/mmc/host/sdhci-pci-gli.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index ad742743a494..31547fed0952 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -906,7 +906,26 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
return 0;
}
+#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
+
+static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
+{
+ u32 val = readl(host->ioaddr + (reg & ~3));
+ u16 word;
+ word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
+ return word;
+}
+
+static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
+{
+ u32 val = readl(host->ioaddr + (reg & ~3));
+ u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
+ return byte;
+}
+
static const struct sdhci_ops sdhci_gl9755_ops = {
+ .read_w = sdhci_gli_readw,
+ .read_b = sdhci_gli_readb,
.set_clock = sdhci_gl9755_set_clock,
.enable_dma = sdhci_pci_enable_dma,
.set_bus_width = sdhci_set_bus_width,
--
2.33.0
Argh, forgot to Cc Ben...
Ben, please let me know what you think about this series. I can resend
it CCing you if you want, or you can also find it here:
https://lore.kernel.org/all/[email protected]/
Sorry for missing the Cc...
-Hector
On 07/12/2021 15.40, Hector Martin wrote:
> Hi folks,
>
> This short series adds a few quirks needed to make the card readers in
> Apple M1 Pro/Max MacBook laptops work properly.
>
> The first patch should be straightforward; it just allows configuring
> the CD/WP polarity based on device tree settings. There is already a
> standard DT binding for this.
>
> The second patch bugs me. I don't understand why this problem happens
> on these machines, and not on e.g. x86 laptops (which presumably work
> with this driver). 8/16-bit MMIO reads work fine on other PCIe devices
> on these machines, so it is not a generalized problem with the PCIe
> controller in these SoCs. The problem also happens when running macOS
> (it also uses 32-bit reads). Ben, is there any chance you might know
> of some vendor-specific knob somewhere that can fix this issue without
> requiring the MMIO read workaround? Interestingly, 8/16-bit writes
> work perfectly fine.
>
> Hector Martin (2):
> mmc: sdhci-pci-gli: GL9755: Support for CD/WP inversion on OF
> platforms
> mmc: sdhci-pci-gli: GL9755: Issue 8/16-bit MMIO reads as 32-bit reads.
>
> drivers/mmc/host/sdhci-pci-gli.c | 38 ++++++++++++++++++++++++++++++--
> 1 file changed, 36 insertions(+), 2 deletions(-)
>
--
Hector Martin ([email protected])
Public Key: https://mrcn.st/pub
Hi Ben,
On 07/12/2021 21.25, Ben Chuang wrote:
> Hi Hector,
>
> I got your two patches so you don't need to resend them.
> About the 8/16-bits MMIO read patch as the second patch, it is necessary.
> I don't know some vendor-specific knobs, sorry.
Is this only required on these Apple platforms? I'm very curious about
what's different about them. I assume these chips don't need the
workaround on x86 laptops, right?
> ps. Do you make Asahi Linux now? It's a cool project. :)
Along with a lot of other talented folks, yes :)
-Hector
--
Hector Martin ([email protected])
Public Key: https://mrcn.st/pub
Hi Hector,
On Tue, Dec 7, 2021 at 10:10 PM Hector Martin <[email protected]> wrote:
>
> Hi Ben,
>
> On 07/12/2021 21.25, Ben Chuang wrote:
> > Hi Hector,
> >
> > I got your two patches so you don't need to resend them.
> > About the 8/16-bits MMIO read patch as the second patch, it is necessary.
> > I don't know some vendor-specific knobs, sorry.
>
> Is this only required on these Apple platforms? I'm very curious about
> what's different about them. I assume these chips don't need the
> workaround on x86 laptops, right?
I'm not sure if it only happens on these Apple platforms.
Right, the workaround is not needed on x86.
>
> > ps. Do you make Asahi Linux now? It's a cool project. :)
>
> Along with a lot of other talented folks, yes :)
>
> -Hector
>
> --
> Hector Martin ([email protected])
> Public Key: https://mrcn.st/pub
Best regards,
Ben
Hi Hector,
On Tue, 7 Dec 2021 15:40:19 +0900, Hector Martin <[email protected]> wrote:
>
> For some reason, <32-bit reads do not work on Apple ARM64 platforms with
> these chips (even though they do on other PCIe devices). Issue them as
> 32-bit reads instead. This is done unconditionally, as it shouldn't hurt
> even if not necessary.
>
> Signed-off-by: Hector Martin <[email protected]>
> ---
> drivers/mmc/host/sdhci-pci-gli.c | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
> index ad742743a494..31547fed0952 100644
> --- a/drivers/mmc/host/sdhci-pci-gli.c
> +++ b/drivers/mmc/host/sdhci-pci-gli.c
> @@ -906,7 +906,26 @@ static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
> return 0;
> }
>
> +#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
> +
> +static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
> +{
> + u32 val = readl(host->ioaddr + (reg & ~3));
> + u16 word;
> + word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
checkpatch says "
WARNING: Missing a blank line after declarations
#71: FILE: drivers/mmc/host/sdhci-pci-gli.c:915:
+ u16 word;
+ word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
"
> + return word;
> +}
> +
> +static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
> +{
> + u32 val = readl(host->ioaddr + (reg & ~3));
> + u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
> + return byte;
> +}
> +
> static const struct sdhci_ops sdhci_gl9755_ops = {
> + .read_w = sdhci_gli_readw,
> + .read_b = sdhci_gli_readb,
I think GL9750 also need this patch.
Can you help to add these two functions to sdhci_gl9750_ops?
Best regards,
Ben
> .set_clock = sdhci_gl9755_set_clock,
> .enable_dma = sdhci_pci_enable_dma,
> .set_bus_width = sdhci_set_bus_width,
> --
> 2.33.0