To support Thunderbolt compatibility mode, synchronize
ec_response_usb_pd_control_v2 with the Chrome EC version, so that
we get the Thunderbolt related control fields and macros.
Signed-off-by: Prashant Malani <[email protected]>
---
.../linux/platform_data/cros_ec_commands.h | 19 +++++++++++++++----
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h
index a7b0fc440c35..b808570bdd04 100644
--- a/include/linux/platform_data/cros_ec_commands.h
+++ b/include/linux/platform_data/cros_ec_commands.h
@@ -4917,15 +4917,26 @@ struct ec_response_usb_pd_control_v1 {
#define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */
#define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */
+/* Active/Passive Cable */
+#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
+/* Optical/Non-optical cable */
+#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
+/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
+#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
+/* Active Link Uni-Direction */
+#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
+
struct ec_response_usb_pd_control_v2 {
uint8_t enabled;
uint8_t role;
uint8_t polarity;
char state[32];
- uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */
- uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
- /* CL:1500994 Current cable type */
- uint8_t reserved_cable_type;
+ uint8_t cc_state; /* enum pd_cc_states representing cc state */
+ uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
+ uint8_t reserved; /* Reserved for future use */
+ uint8_t control_flags; /* USB_PD_CTRL_*flags */
+ uint8_t cable_speed; /* TBT_SS_* cable speed */
+ uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
} __ec_align1;
#define EC_CMD_USB_PD_PORTS 0x0102
--
2.27.0.111.gc72c7da667-goog
Add mux control support for Thunderbolt compatibility mode.
Suggested-by: Heikki Krogerus <[email protected]>
Co-developed-by: Azhar Shaikh <[email protected]>
Co-developed-by: Casey Bowman <[email protected]>
Signed-off-by: Prashant Malani <[email protected]>
---
drivers/platform/chrome/cros_ec_typec.c | 70 ++++++++++++++++++++++++-
1 file changed, 69 insertions(+), 1 deletion(-)
diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
index 1df1386f32e4..0c041b79cbba 100644
--- a/drivers/platform/chrome/cros_ec_typec.c
+++ b/drivers/platform/chrome/cros_ec_typec.c
@@ -17,6 +17,7 @@
#include <linux/usb/typec_altmode.h>
#include <linux/usb/typec_dp.h>
#include <linux/usb/typec_mux.h>
+#include <linux/usb/typec_tbt.h>
#include <linux/usb/role.h>
#define DRV_NAME "cros-ec-typec"
@@ -24,6 +25,7 @@
/* Supported alt modes. */
enum {
CROS_EC_ALTMODE_DP = 0,
+ CROS_EC_ALTMODE_TBT,
CROS_EC_ALTMODE_MAX,
};
@@ -165,6 +167,14 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec,
port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
+ /*
+ * Register TBT compatibility alt mode. The EC will not enter the mode
+ * if it doesn't support it, so it's safe to register it unconditionally
+ * here for now.
+ */
+ port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
+ port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
+
port->state.alt = NULL;
port->state.mode = TYPEC_STATE_USB;
port->state.data = NULL;
@@ -391,6 +401,62 @@ static int cros_typec_usb_safe_state(struct cros_typec_port *port)
return typec_mux_set(port->mux, &port->state);
}
+/*
+ * Spoof the VDOs that were likely communicated by the partner for TBT alt
+ * mode.
+ */
+static int cros_typec_enable_tbt(struct cros_typec_data *typec,
+ int port_num,
+ struct ec_response_usb_pd_control_v2 *pd_ctrl)
+{
+ struct cros_typec_port *port = typec->ports[port_num];
+ struct typec_thunderbolt_data data;
+ int ret;
+
+ if (typec->pd_ctrl_ver < 2) {
+ dev_err(typec->dev,
+ "PD_CTRL version too old: %d\n", typec->pd_ctrl_ver);
+ return -ENOTSUPP;
+ }
+
+ /* Device Discover Mode VDO */
+ data.device_mode = TBT_MODE;
+
+ if (pd_ctrl->control_flags & USB_PD_CTRL_TBT_LEGACY_ADAPTER)
+ data.device_mode = TBT_SET_ADAPTER(TBT_ADAPTER_TBT3);
+
+ /* Cable Discover Mode VDO */
+ data.cable_mode = TBT_MODE;
+ data.cable_mode |= TBT_SET_CABLE_SPEED(pd_ctrl->cable_speed);
+
+ if (pd_ctrl->control_flags & USB_PD_CTRL_OPTICAL_CABLE)
+ data.cable_mode |= TBT_CABLE_OPTICAL;
+
+ if (pd_ctrl->control_flags & USB_PD_CTRL_ACTIVE_LINK_UNIDIR)
+ data.cable_mode |= TBT_CABLE_LINK_TRAINING;
+
+ if (pd_ctrl->cable_gen)
+ data.cable_mode |= TBT_CABLE_ROUNDED;
+
+ /* Enter Mode VDO */
+ data.enter_vdo = TBT_SET_CABLE_SPEED(pd_ctrl->cable_speed);
+
+ if (pd_ctrl->control_flags & USB_PD_CTRL_ACTIVE_CABLE)
+ data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE;
+
+ if (!port->state.alt) {
+ port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT];
+ ret = cros_typec_usb_safe_state(port);
+ if (ret)
+ return ret;
+ }
+
+ port->state.data = &data;
+ port->state.mode = TYPEC_TBT_MODE;
+
+ return typec_mux_set(port->mux, &port->state);
+}
+
/* Spoof the VDOs that were likely communicated by the partner. */
static int cros_typec_enable_dp(struct cros_typec_data *typec,
int port_num,
@@ -448,7 +514,9 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
if (ret)
return ret;
- if (mux_flags & USB_PD_MUX_DP_ENABLED) {
+ if (mux_flags & USB_PD_MUX_TBT_COMPAT_ENABLED) {
+ ret = cros_typec_enable_tbt(typec, port_num, pd_ctrl);
+ } else if (mux_flags & USB_PD_MUX_DP_ENABLED) {
ret = cros_typec_enable_dp(typec, port_num, pd_ctrl);
} else if (mux_flags & USB_PD_MUX_SAFE_MODE) {
ret = cros_typec_usb_safe_state(port);
--
2.27.0.111.gc72c7da667-goog
On Wed, Jun 24, 2020 at 01:09:24AM -0700, Prashant Malani wrote:
> Add mux control support for Thunderbolt compatibility mode.
>
> Suggested-by: Heikki Krogerus <[email protected]>
> Co-developed-by: Azhar Shaikh <[email protected]>
> Co-developed-by: Casey Bowman <[email protected]>
> Signed-off-by: Prashant Malani <[email protected]>
> ---
> drivers/platform/chrome/cros_ec_typec.c | 70 ++++++++++++++++++++++++-
> 1 file changed, 69 insertions(+), 1 deletion(-)
Cool! Can you guys test also USB4 with the attached patch (still work
in progress)? It should apply on top of these.
The mux driver is still missing USB4 support, but I'll send the
patches needed for that right now...
thanks,
--
heikki
On Wed, Jun 24, 2020 at 12:15:20PM +0300, Heikki Krogerus wrote:
> On Wed, Jun 24, 2020 at 01:09:24AM -0700, Prashant Malani wrote:
> > Add mux control support for Thunderbolt compatibility mode.
> >
> > Suggested-by: Heikki Krogerus <[email protected]>
> > Co-developed-by: Azhar Shaikh <[email protected]>
> > Co-developed-by: Casey Bowman <[email protected]>
> > Signed-off-by: Prashant Malani <[email protected]>
> > ---
> > drivers/platform/chrome/cros_ec_typec.c | 70 ++++++++++++++++++++++++-
> > 1 file changed, 69 insertions(+), 1 deletion(-)
>
> Cool! Can you guys test also USB4 with the attached patch (still work
> in progress)? It should apply on top of these.
>
> The mux driver is still missing USB4 support, but I'll send the
> patches needed for that right now...
Actually, I'll just attach that one here as well. Let me know if you
guys can test these.
thanks,
--
heikki
Hi Heikki,
On Wed, Jun 24, 2020 at 12:20:40PM +0300, Heikki Krogerus wrote:
> On Wed, Jun 24, 2020 at 12:15:20PM +0300, Heikki Krogerus wrote:
> > On Wed, Jun 24, 2020 at 01:09:24AM -0700, Prashant Malani wrote:
> > > Add mux control support for Thunderbolt compatibility mode.
> > >
> > > Suggested-by: Heikki Krogerus <[email protected]>
> > > Co-developed-by: Azhar Shaikh <[email protected]>
> > > Co-developed-by: Casey Bowman <[email protected]>
> > > Signed-off-by: Prashant Malani <[email protected]>
> > > ---
> > > drivers/platform/chrome/cros_ec_typec.c | 70 ++++++++++++++++++++++++-
> > > 1 file changed, 69 insertions(+), 1 deletion(-)
> >
> > Cool! Can you guys test also USB4 with the attached patch (still work
> > in progress)? It should apply on top of these.
> >
> > The mux driver is still missing USB4 support, but I'll send the
> > patches needed for that right now...
>
> Actually, I'll just attach that one here as well. Let me know if you
> guys can test these.
Thanks for the patches. Will try them out today and compare the PMC IPC
buffers against what extcon is doing.
Best regards,
-Prashant
>
> thanks,
>
> --
> heikki
> From 396bd399ac815165ec4992739d45d52ecf234acc Mon Sep 17 00:00:00 2001
> From: Heikki Krogerus <[email protected]>
> Date: Wed, 3 Jun 2020 17:00:14 +0300
> Subject: [PATCH] usb: typec: intel_pmc_mux: Add support for USB4
>
> The PMC mux-agent can be used also when Enter_USB is used in
> order to enter USB4 mode. The mux-agent does not have USB4
> specific message, but instead needs to be put into TBT
> alternate mode also with USB4. That is OK as the controller
> is in any case the same with TBT3 and USB4.
>
> Signed-off-by: Heikki Krogerus <[email protected]>
> ---
> drivers/usb/typec/mux/intel_pmc_mux.c | 65 +++++++++++++++++++++++----
> 1 file changed, 56 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/usb/typec/mux/intel_pmc_mux.c b/drivers/usb/typec/mux/intel_pmc_mux.c
> index 70ddc9d6d49e4..6d223bd360b8e 100644
> --- a/drivers/usb/typec/mux/intel_pmc_mux.c
> +++ b/drivers/usb/typec/mux/intel_pmc_mux.c
> @@ -10,6 +10,7 @@
> #include <linux/module.h>
> #include <linux/platform_device.h>
> #include <linux/property.h>
> +#include <linux/usb/pd.h>
> #include <linux/usb/role.h>
> #include <linux/usb/typec_mux.h>
> #include <linux/usb/typec_dp.h>
> @@ -227,6 +228,41 @@ pmc_usb_mux_tbt(struct pmc_usb_port *port, struct typec_mux_state *state)
> return pmc_usb_command(port, (void *)&req, sizeof(req));
> }
>
> +static int
> +pmc_usb_mux_usb4(struct pmc_usb_port *port, struct typec_mux_state *state)
> +{
> + u32 eudo = *(u32 *)state->data;
> + struct altmode_req req = { };
> + u8 cable_speed;
> +
> + req.usage = PMC_USB_ALT_MODE;
> + req.usage |= port->usb3_port << PMC_USB_MSG_USB3_PORT_SHIFT;
> + req.mode_type = PMC_USB_MODE_TYPE_TBT << PMC_USB_MODE_TYPE_SHIFT;
> +
> + /* USB4 Mode */
> + req.mode_data = PMC_USB_ALTMODE_FORCE_LSR;
> + req.mode_data |= PMC_USB_ALTMODE_ACTIVE_LINK;
> +
> + req.mode_data |= (port->orientation - 1) << PMC_USB_ALTMODE_ORI_SHIFT;
> + req.mode_data |= (port->role - 1) << PMC_USB_ALTMODE_UFP_SHIFT;
> +
> + switch ((eudo & EUDO_CABLE_TYPE_MASK) >> EUDO_CABLE_TYPE_SHIFT) {
> + case EUDO_CABLE_TYPE_PASSIVE:
> + break;
> + case EUDO_CABLE_TYPE_OPTICAL:
> + req.mode_data |= PMC_USB_ALTMODE_CABLE_TYPE;
> + /* fall through */
> + default:
> + req.mode_data |= PMC_USB_ALTMODE_ACTIVE_CABLE;
> + break;
> + }
> +
> + cable_speed = (eudo & EUDO_CABLE_SPEED_MASK) >> EUDO_CABLE_SPEED_SHIFT;
> + req.mode_data |= PMC_USB_ALTMODE_CABLE_SPD(cable_speed);
> +
> + return pmc_usb_command(port, (void *)&req, sizeof(req));
> +}
> +
> static int pmc_usb_mux_safe_state(struct pmc_usb_port *port)
> {
> u8 msg;
> @@ -268,17 +304,28 @@ pmc_usb_mux_set(struct typec_mux *mux, struct typec_mux_state *state)
> {
> struct pmc_usb_port *port = typec_mux_get_drvdata(mux);
>
> - if (!state->alt)
> - return 0;
> -
> if (state->mode == TYPEC_STATE_SAFE)
> return pmc_usb_mux_safe_state(port);
> -
> - switch (state->alt->svid) {
> - case USB_TYPEC_TBT_SID:
> - return pmc_usb_mux_tbt(port, state);
> - case USB_TYPEC_DP_SID:
> - return pmc_usb_mux_dp(port, state);
> + if (state->mode == TYPEC_STATE_USB)
> + return pmc_usb_connect(port);
> +
> + if (state->alt) {
> + switch (state->alt->svid) {
> + case USB_TYPEC_TBT_SID:
> + return pmc_usb_mux_tbt(port, state);
> + case USB_TYPEC_DP_SID:
> + return pmc_usb_mux_dp(port, state);
> + }
> + } else {
> + switch (state->mode) {
> + case TYPEC_MODE_USB2:
> + /* REVISIT: Try with usb3_port set to 0? */
> + break;
> + case TYPEC_MODE_USB3:
> + return pmc_usb_connect(port);
> + case TYPEC_MODE_USB4:
> + return pmc_usb_mux_usb4(port, state);
> + }
> }
>
> return -EOPNOTSUPP;
> --
> 2.27.0
>
On Wed, Jun 24, 2020 at 01:09:24AM -0700, Prashant Malani wrote:
> Add mux control support for Thunderbolt compatibility mode.
>
> Suggested-by: Heikki Krogerus <[email protected]>
> Co-developed-by: Azhar Shaikh <[email protected]>
> Co-developed-by: Casey Bowman <[email protected]>
> Signed-off-by: Prashant Malani <[email protected]>
Reviewed-by: Heikki Krogerus <[email protected]>
> ---
> drivers/platform/chrome/cros_ec_typec.c | 70 ++++++++++++++++++++++++-
> 1 file changed, 69 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/platform/chrome/cros_ec_typec.c b/drivers/platform/chrome/cros_ec_typec.c
> index 1df1386f32e4..0c041b79cbba 100644
> --- a/drivers/platform/chrome/cros_ec_typec.c
> +++ b/drivers/platform/chrome/cros_ec_typec.c
> @@ -17,6 +17,7 @@
> #include <linux/usb/typec_altmode.h>
> #include <linux/usb/typec_dp.h>
> #include <linux/usb/typec_mux.h>
> +#include <linux/usb/typec_tbt.h>
> #include <linux/usb/role.h>
>
> #define DRV_NAME "cros-ec-typec"
> @@ -24,6 +25,7 @@
> /* Supported alt modes. */
> enum {
> CROS_EC_ALTMODE_DP = 0,
> + CROS_EC_ALTMODE_TBT,
> CROS_EC_ALTMODE_MAX,
> };
>
> @@ -165,6 +167,14 @@ static void cros_typec_register_port_altmodes(struct cros_typec_data *typec,
> port->p_altmode[CROS_EC_ALTMODE_DP].svid = USB_TYPEC_DP_SID;
> port->p_altmode[CROS_EC_ALTMODE_DP].mode = USB_TYPEC_DP_MODE;
>
> + /*
> + * Register TBT compatibility alt mode. The EC will not enter the mode
> + * if it doesn't support it, so it's safe to register it unconditionally
> + * here for now.
> + */
> + port->p_altmode[CROS_EC_ALTMODE_TBT].svid = USB_TYPEC_TBT_SID;
> + port->p_altmode[CROS_EC_ALTMODE_TBT].mode = TYPEC_ANY_MODE;
> +
> port->state.alt = NULL;
> port->state.mode = TYPEC_STATE_USB;
> port->state.data = NULL;
> @@ -391,6 +401,62 @@ static int cros_typec_usb_safe_state(struct cros_typec_port *port)
> return typec_mux_set(port->mux, &port->state);
> }
>
> +/*
> + * Spoof the VDOs that were likely communicated by the partner for TBT alt
> + * mode.
> + */
> +static int cros_typec_enable_tbt(struct cros_typec_data *typec,
> + int port_num,
> + struct ec_response_usb_pd_control_v2 *pd_ctrl)
> +{
> + struct cros_typec_port *port = typec->ports[port_num];
> + struct typec_thunderbolt_data data;
> + int ret;
> +
> + if (typec->pd_ctrl_ver < 2) {
> + dev_err(typec->dev,
> + "PD_CTRL version too old: %d\n", typec->pd_ctrl_ver);
> + return -ENOTSUPP;
> + }
> +
> + /* Device Discover Mode VDO */
> + data.device_mode = TBT_MODE;
> +
> + if (pd_ctrl->control_flags & USB_PD_CTRL_TBT_LEGACY_ADAPTER)
> + data.device_mode = TBT_SET_ADAPTER(TBT_ADAPTER_TBT3);
> +
> + /* Cable Discover Mode VDO */
> + data.cable_mode = TBT_MODE;
> + data.cable_mode |= TBT_SET_CABLE_SPEED(pd_ctrl->cable_speed);
> +
> + if (pd_ctrl->control_flags & USB_PD_CTRL_OPTICAL_CABLE)
> + data.cable_mode |= TBT_CABLE_OPTICAL;
> +
> + if (pd_ctrl->control_flags & USB_PD_CTRL_ACTIVE_LINK_UNIDIR)
> + data.cable_mode |= TBT_CABLE_LINK_TRAINING;
> +
> + if (pd_ctrl->cable_gen)
> + data.cable_mode |= TBT_CABLE_ROUNDED;
> +
> + /* Enter Mode VDO */
> + data.enter_vdo = TBT_SET_CABLE_SPEED(pd_ctrl->cable_speed);
> +
> + if (pd_ctrl->control_flags & USB_PD_CTRL_ACTIVE_CABLE)
> + data.enter_vdo |= TBT_ENTER_MODE_ACTIVE_CABLE;
> +
> + if (!port->state.alt) {
> + port->state.alt = &port->p_altmode[CROS_EC_ALTMODE_TBT];
> + ret = cros_typec_usb_safe_state(port);
> + if (ret)
> + return ret;
> + }
> +
> + port->state.data = &data;
> + port->state.mode = TYPEC_TBT_MODE;
> +
> + return typec_mux_set(port->mux, &port->state);
> +}
> +
> /* Spoof the VDOs that were likely communicated by the partner. */
> static int cros_typec_enable_dp(struct cros_typec_data *typec,
> int port_num,
> @@ -448,7 +514,9 @@ static int cros_typec_configure_mux(struct cros_typec_data *typec, int port_num,
> if (ret)
> return ret;
>
> - if (mux_flags & USB_PD_MUX_DP_ENABLED) {
> + if (mux_flags & USB_PD_MUX_TBT_COMPAT_ENABLED) {
> + ret = cros_typec_enable_tbt(typec, port_num, pd_ctrl);
> + } else if (mux_flags & USB_PD_MUX_DP_ENABLED) {
> ret = cros_typec_enable_dp(typec, port_num, pd_ctrl);
> } else if (mux_flags & USB_PD_MUX_SAFE_MODE) {
> ret = cros_typec_usb_safe_state(port);
> --
> 2.27.0.111.gc72c7da667-goog
thanks,
--
heikki
Hi Prashant,
On 24/6/20 10:09, Prashant Malani wrote:
> To support Thunderbolt compatibility mode, synchronize
> ec_response_usb_pd_control_v2 with the Chrome EC version, so that
> we get the Thunderbolt related control fields and macros.
>
> Signed-off-by: Prashant Malani <[email protected]>
Applied both patches for 5.9
> ---
> .../linux/platform_data/cros_ec_commands.h | 19 +++++++++++++++----
> 1 file changed, 15 insertions(+), 4 deletions(-)
>
> diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h
> index a7b0fc440c35..b808570bdd04 100644
> --- a/include/linux/platform_data/cros_ec_commands.h
> +++ b/include/linux/platform_data/cros_ec_commands.h
> @@ -4917,15 +4917,26 @@ struct ec_response_usb_pd_control_v1 {
> #define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */
> #define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */
>
> +/* Active/Passive Cable */
> +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
> +/* Optical/Non-optical cable */
> +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
> +/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
> +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
> +/* Active Link Uni-Direction */
> +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
> +
> struct ec_response_usb_pd_control_v2 {
> uint8_t enabled;
> uint8_t role;
> uint8_t polarity;
> char state[32];
> - uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */
> - uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
> - /* CL:1500994 Current cable type */
> - uint8_t reserved_cable_type;
> + uint8_t cc_state; /* enum pd_cc_states representing cc state */
> + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
> + uint8_t reserved; /* Reserved for future use */
> + uint8_t control_flags; /* USB_PD_CTRL_*flags */
> + uint8_t cable_speed; /* TBT_SS_* cable speed */
> + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
> } __ec_align1;
>
> #define EC_CMD_USB_PD_PORTS 0x0102
>
Thanks Enric!
On Fri, Jun 26, 2020 at 2:11 AM Enric Balletbo i Serra
<[email protected]> wrote:
>
> Hi Prashant,
>
> On 24/6/20 10:09, Prashant Malani wrote:
> > To support Thunderbolt compatibility mode, synchronize
> > ec_response_usb_pd_control_v2 with the Chrome EC version, so that
> > we get the Thunderbolt related control fields and macros.
> >
> > Signed-off-by: Prashant Malani <[email protected]>
>
> Applied both patches for 5.9
>
> > ---
> > .../linux/platform_data/cros_ec_commands.h | 19 +++++++++++++++----
> > 1 file changed, 15 insertions(+), 4 deletions(-)
> >
> > diff --git a/include/linux/platform_data/cros_ec_commands.h b/include/linux/platform_data/cros_ec_commands.h
> > index a7b0fc440c35..b808570bdd04 100644
> > --- a/include/linux/platform_data/cros_ec_commands.h
> > +++ b/include/linux/platform_data/cros_ec_commands.h
> > @@ -4917,15 +4917,26 @@ struct ec_response_usb_pd_control_v1 {
> > #define USBC_PD_CC_UFP_ATTACHED 4 /* UFP attached to usbc */
> > #define USBC_PD_CC_DFP_ATTACHED 5 /* DPF attached to usbc */
> >
> > +/* Active/Passive Cable */
> > +#define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
> > +/* Optical/Non-optical cable */
> > +#define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
> > +/* 3rd Gen TBT device (or AMA)/2nd gen tbt Adapter */
> > +#define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
> > +/* Active Link Uni-Direction */
> > +#define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
> > +
> > struct ec_response_usb_pd_control_v2 {
> > uint8_t enabled;
> > uint8_t role;
> > uint8_t polarity;
> > char state[32];
> > - uint8_t cc_state; /* USBC_PD_CC_*Encoded cc state */
> > - uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
> > - /* CL:1500994 Current cable type */
> > - uint8_t reserved_cable_type;
> > + uint8_t cc_state; /* enum pd_cc_states representing cc state */
> > + uint8_t dp_mode; /* Current DP pin mode (MODE_DP_PIN_[A-E]) */
> > + uint8_t reserved; /* Reserved for future use */
> > + uint8_t control_flags; /* USB_PD_CTRL_*flags */
> > + uint8_t cable_speed; /* TBT_SS_* cable speed */
> > + uint8_t cable_gen; /* TBT_GEN3_* cable rounded support */
> > } __ec_align1;
> >
> > #define EC_CMD_USB_PD_PORTS 0x0102
> >