There have been several attempts in the past few years to allow
building the QUICC engine drivers for platforms other than PPC32. This
is yet another attempt.
v5 can be found here: https://lore.kernel.org/lkml/[email protected]/
Changes in v6:
- add various R-b, A-b tags
- add a patch (48/49) fixing a build issue on ARM with CONFIG_SMP=y
I added that patch last in the series, apart from the "allow to build
on ARM" Kconfig change, to preserve the enumeration of the other
patches from v5.
1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe).
6-8 handle miscellaneous other ppcisms.
9-21 deal with qe_ic: Simplifying the driver significantly by removing
unused code, and removing the platform-specific initialization from
arch/powerpc/.
22-25 deal with raw access to devicetree properties in native endianness.
26-34 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on non-ppc.
35-46 deal with IS_ERR_VALUE() and some other things found while
digging around that part of the code.
47 adds a PPC32 dependency to UCC_GETH - it has some of the same
issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody
has requested that I allow that driver to be built for arm{,64} and
reportedly, the hardware has only ever shipped on PPC SOCs. So instead
of growing this series even bigger, I kept that addition. It's trivial
to remove if somebody cares enough to fix the build errors/warnings
and actually has a platform to test the result on.
48 fixes a build issue on ARM reported by the kbuild bot.
Finally patch 49 lifts the PPC32 restriction from QUICC_ENGINE. At the
request of Li Yang, it doesn't remove the PPC32 dependency but instead
changes it to PPC|| ARM || ARM64 (or COMPILE_TEST), i.e. listing
the platforms that may have a QE.
The series has been built and booted on both an mpc8309-based platform
(ppc) as well as an ls1021a-based platform (arm). The core QE code is
exercised on both, while I could only test the ucc_uart on arm, since
the uarts are not wired up on our mpc8309 board. Qiang Zhao reports
that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64)
board.
Rasmus Villemoes (49):
soc: fsl: qe: remove space-before-tab
soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers
soc: fsl: qe: introduce qe_io{read,write}* wrappers
soc: fsl: qe: avoid ppc-specific io accessors
soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
soc: fsl: qe: drop unneeded #includes
soc: fsl: qe: drop assign-only high_active in qe_ic_init
soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
soc: fsl: qe: remove unused qe_ic_set_* functions
soc: fsl: qe: don't use NO_IRQ in qe_ic.c
soc: fsl: qe: make qe_ic_get_{low,high}_irq static
soc: fsl: qe: simplify qe_ic_init()
soc: fsl: qe: merge qe_ic.h headers into qe_ic.c
soc: fsl: qe: qe.c: use of_property_read_* helpers
soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle()
soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu
soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init()
soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
soc/fsl/qe/qe.h: update include path for cpm.h
serial: ucc_uart: explicitly include soc/fsl/cpm.h
serial: ucc_uart: replace ppc-specific IO accessors
serial: ucc_uart: factor out soft_uart initialization
serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()
serial: ucc_uart: limit brg-frequency workaround to PPC32
serial: ucc_uart: access __be32 field using be32_to_cpu
soc: fsl: qe: change return type of cpm_muram_alloc() to s32
soc: fsl: qe: make cpm_muram_free() return void
soc: fsl: qe: make cpm_muram_free() ignore a negative offset
soc: fsl: qe: drop broken lazy call of cpm_muram_init()
soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error
path
soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c
soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init()
soc: fsl: qe: drop pointless check in qe_sdma_init()
soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c
net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE()
net/wan/fsl_ucc_hdlc: fix reading of __be16 registers
net/wan/fsl_ucc_hdlc: reject muram offsets above 64K
net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
soc: fsl: qe: remove unused #include of asm/irq.h from ucc.c
soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
arch/powerpc/include/asm/cpm.h | 172 +-------
arch/powerpc/platforms/83xx/km83xx.c | 3 +-
arch/powerpc/platforms/83xx/misc.c | 23 --
arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 7 -
arch/powerpc/platforms/85xx/common.c | 23 --
arch/powerpc/platforms/85xx/corenet_generic.c | 12 -
arch/powerpc/platforms/85xx/mpc85xx.h | 2 -
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 -
arch/powerpc/platforms/85xx/twr_p102x.c | 16 -
drivers/net/ethernet/freescale/Kconfig | 2 +-
drivers/net/wan/fsl_ucc_hdlc.c | 23 +-
drivers/net/wan/fsl_ucc_hdlc.h | 2 +-
drivers/soc/fsl/qe/Kconfig | 3 +-
drivers/soc/fsl/qe/gpio.c | 34 +-
drivers/soc/fsl/qe/qe.c | 104 ++---
drivers/soc/fsl/qe/qe_common.c | 50 +--
drivers/soc/fsl/qe/qe_ic.c | 285 ++++++-------
drivers/soc/fsl/qe/qe_ic.h | 99 -----
drivers/soc/fsl/qe/qe_io.c | 70 ++--
drivers/soc/fsl/qe/qe_tdm.c | 8 +-
drivers/soc/fsl/qe/ucc.c | 27 +-
drivers/soc/fsl/qe/ucc_fast.c | 86 ++--
drivers/soc/fsl/qe/ucc_slow.c | 60 ++-
drivers/soc/fsl/qe/usb.c | 2 +-
drivers/tty/serial/ucc_uart.c | 385 +++++++++---------
include/soc/fsl/cpm.h | 171 ++++++++
include/soc/fsl/qe/qe.h | 59 ++-
include/soc/fsl/qe/qe_ic.h | 135 ------
include/soc/fsl/qe/ucc_fast.h | 4 +-
include/soc/fsl/qe/ucc_slow.h | 6 +-
35 files changed, 775 insertions(+), 1156 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
create mode 100644 include/soc/fsl/cpm.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h
--
2.23.0
The "soft uart" mechanism is a workaround for a silicon bug which (as
far as I know) only affects some PPC-based SOCs.
The code that determines which microcode blob to request relies on
some powerpc-specific bits (e.g. the mfspr(SPRN_SVR) and hence also
the asm/reg.h header). This makes it a little awkward to allow this
driver to be built for non-PPC based SOCs with a QE, even if they are
not affected by that silicon bug and thus don't need any of the Soft
UART logic.
There's no way around guarding those bits with some ifdeffery, so to
keep that isolated, factor out the
do-we-need-soft-uart-and-if-so-handle-the-firmware to a separate
function, which we can then easily stub out for non-PPC.
Reviewed-by: Timur Tabi <[email protected]>
Acked-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/tty/serial/ucc_uart.c | 110 ++++++++++++++++++----------------
1 file changed, 58 insertions(+), 52 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 8a378ee5d34f..f286e91714cb 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -1183,70 +1183,76 @@ static void uart_firmware_cont(const struct firmware *fw, void *context)
release_firmware(fw);
}
-static int ucc_uart_probe(struct platform_device *ofdev)
+static int soft_uart_init(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
- const unsigned int *iprop; /* Integer OF properties */
- const char *sprop; /* String OF properties */
- struct uart_qe_port *qe_port = NULL;
- struct resource res;
+ struct qe_firmware_info *qe_fw_info;
int ret;
- /*
- * Determine if we need Soft-UART mode
- */
if (of_find_property(np, "soft-uart", NULL)) {
dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
soft_uart = 1;
+ } else {
+ return 0;
}
- /*
- * If we are using Soft-UART, determine if we need to upload the
- * firmware, too.
- */
- if (soft_uart) {
- struct qe_firmware_info *qe_fw_info;
-
- qe_fw_info = qe_get_firmware_info();
-
- /* Check if the firmware has been uploaded. */
- if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
- firmware_loaded = 1;
- } else {
- char filename[32];
- unsigned int soc;
- unsigned int rev_h;
- unsigned int rev_l;
-
- soc = soc_info(&rev_h, &rev_l);
- if (!soc) {
- dev_err(&ofdev->dev, "unknown CPU model\n");
- return -ENXIO;
- }
- sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
- soc, rev_h, rev_l);
-
- dev_info(&ofdev->dev, "waiting for firmware %s\n",
- filename);
+ qe_fw_info = qe_get_firmware_info();
- /*
- * We call request_firmware_nowait instead of
- * request_firmware so that the driver can load and
- * initialize the ports without holding up the rest of
- * the kernel. If hotplug support is enabled in the
- * kernel, then we use it.
- */
- ret = request_firmware_nowait(THIS_MODULE,
- FW_ACTION_HOTPLUG, filename, &ofdev->dev,
- GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
- if (ret) {
- dev_err(&ofdev->dev,
- "could not load firmware %s\n",
- filename);
- return ret;
- }
+ /* Check if the firmware has been uploaded. */
+ if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
+ firmware_loaded = 1;
+ } else {
+ char filename[32];
+ unsigned int soc;
+ unsigned int rev_h;
+ unsigned int rev_l;
+
+ soc = soc_info(&rev_h, &rev_l);
+ if (!soc) {
+ dev_err(&ofdev->dev, "unknown CPU model\n");
+ return -ENXIO;
+ }
+ sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
+ soc, rev_h, rev_l);
+
+ dev_info(&ofdev->dev, "waiting for firmware %s\n",
+ filename);
+
+ /*
+ * We call request_firmware_nowait instead of
+ * request_firmware so that the driver can load and
+ * initialize the ports without holding up the rest of
+ * the kernel. If hotplug support is enabled in the
+ * kernel, then we use it.
+ */
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_HOTPLUG, filename, &ofdev->dev,
+ GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
+ if (ret) {
+ dev_err(&ofdev->dev,
+ "could not load firmware %s\n",
+ filename);
+ return ret;
}
}
+ return 0;
+}
+
+static int ucc_uart_probe(struct platform_device *ofdev)
+{
+ struct device_node *np = ofdev->dev.of_node;
+ const unsigned int *iprop; /* Integer OF properties */
+ const char *sprop; /* String OF properties */
+ struct uart_qe_port *qe_port = NULL;
+ struct resource res;
+ int ret;
+
+ /*
+ * Determine if we need Soft-UART mode
+ */
+ ret = soft_uart_init(ofdev);
+ if (ret)
+ return ret;
qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
if (!qe_port) {
--
2.23.0
asm/cpm.h under arch/powerpc is now just a wrapper for including
soc/fsl/cpm.h. In order to make the qe.h header usable on other
architectures, use the latter path directly.
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
include/soc/fsl/qe/qe.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 9cac04c692fd..521fa3a177e0 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -17,7 +17,7 @@
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
-#include <asm/cpm.h>
+#include <soc/fsl/cpm.h>
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
--
2.23.0
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_io.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index f6b10f38b2f4..99aeb01586bd 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -141,7 +141,6 @@ EXPORT_SYMBOL(par_io_data_set);
int par_io_of_config(struct device_node *np)
{
struct device_node *pio;
- const phandle *ph;
int pio_map_len;
const unsigned int *pio_map;
@@ -150,14 +149,12 @@ int par_io_of_config(struct device_node *np)
return -1;
}
- ph = of_get_property(np, "pio-handle", NULL);
- if (ph == NULL) {
+ pio = of_parse_phandle(np, "pio-handle", 0);
+ if (pio == NULL) {
printk(KERN_ERR "pio-handle not available\n");
return -1;
}
- pio = of_find_node_by_phandle(*ph);
-
pio_map = of_get_property(pio, "pio-map", &pio_map_len);
if (pio_map == NULL) {
printk(KERN_ERR "pio-map is not set!\n");
--
2.23.0
This driver is currently PPC-only, and on powerpc, NO_IRQ is 0, so
this doesn't change functionality. However, not every architecture
defines NO_IRQ, and some define it as -1, so the detection of a failed
irq_of_parse_and_map() (which returns 0 on failure) would be wrong on
those. So to prepare for allowing this driver to build on other
architectures, drop all references to NO_IRQ.
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe_ic.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 4839dcd5c5d3..8f74bc6efd5c 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -282,7 +282,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -293,12 +293,12 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -309,7 +309,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
@@ -320,7 +320,7 @@ static void qe_ic_cascade_low(struct irq_desc *desc)
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
struct irq_chip *chip = irq_desc_get_chip(desc);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
if (chip->irq_eoi)
@@ -333,7 +333,7 @@ static void qe_ic_cascade_high(struct irq_desc *desc)
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
struct irq_chip *chip = irq_desc_get_chip(desc);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
if (chip->irq_eoi)
@@ -347,10 +347,10 @@ static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
struct irq_chip *chip = irq_desc_get_chip(desc);
cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
+ if (cascade_irq == 0)
cascade_irq = qe_ic_get_low_irq(qe_ic);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
chip->irq_eoi(&desc->irq_data);
@@ -386,7 +386,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
qe_ic->virq_high = irq_of_parse_and_map(node, 0);
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
- if (qe_ic->virq_low == NO_IRQ) {
+ if (!qe_ic->virq_low) {
printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
kfree(qe_ic);
return;
@@ -423,8 +423,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, low_handler);
- if (qe_ic->virq_high != NO_IRQ &&
- qe_ic->virq_high != qe_ic->virq_low) {
+ if (qe_ic->virq_high && qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
irq_set_chained_handler(qe_ic->virq_high, high_handler);
}
--
2.23.0
Having to call qe_ic_init() from platform-specific code makes it
awkward to allow building the QE drivers for ARM. It's also a needless
duplication of code, and slightly error-prone: Instead of the caller
needing to know the details of whether the QUICC Engine High and QUICC
Engine Low are actually the same interrupt (see e.g. the machine_is()
in mpc85xx_mds_qeic_init), just let the init function choose the
appropriate handlers after it has parsed the DT and figured it out. If
the two interrupts are distinct, use separate handlers, otherwise use
the handler which first checks the CHIVEC register (for the high
priority interrupts), then the CIVEC.
All existing callers pass 0 for flags, so continue to do that from the
new single caller. Later cleanups will remove that argument
from qe_ic_init and simplify the body, as well as make qe_ic_init into
a proper init function for an IRQCHIP_DECLARE, eliminating the need to
manually look up the fsl,qe-ic node.
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c | 16 ----------
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/83xx/mpc83xx.h | 2 --
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -------
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 27 -----------------
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -----------
arch/powerpc/platforms/85xx/twr_p102x.c | 15 ----------
drivers/soc/fsl/qe/qe_ic.c | 29 +++++++++++++++++--
include/soc/fsl/qe/qe_ic.h | 7 -----
13 files changed, 26 insertions(+), 102 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 273145aed90a..5c6227f7bc37 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -34,7 +34,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index 779791c0570f..6935a5b9fbd1 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/ipic.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -90,24 +89,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index b428835e5919..1c73af104d19 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -33,7 +33,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 4588ce632484..87f68ca06255 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -22,7 +22,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 4a4efa906d35..5b484da9533e 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -41,7 +41,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index 9923059cb111..b7119e443920 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -17,7 +17,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 459145623334..d343f6ce2599 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -73,10 +73,8 @@ extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_qe_init_IRQ(void);
extern void mpc83xx_ipic_and_qe_init_IRQ(void);
#else
-static inline void __init mpc83xx_qe_init_IRQ(void) {}
#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 7ee2c6628f64..8c1bb3941642 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -24,7 +24,6 @@
#include <asm/mpic.h>
#include <asm/ehv_pic.h>
#include <asm/swiotlb.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
@@ -38,8 +37,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -47,13 +44,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 5ca254256c47..4bc49e5ec0b6 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -45,7 +45,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include "smp.h"
@@ -270,33 +269,8 @@ static void __init mpc85xx_mds_qe_init(void)
}
}
-static void __init mpc85xx_mds_qeic_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
-}
#else
static void __init mpc85xx_mds_qe_init(void) { }
-static void __init mpc85xx_mds_qeic_init(void) { }
#endif /* CONFIG_QUICC_ENGINE */
static void __init mpc85xx_mds_setup_arch(void)
@@ -371,7 +345,6 @@ static void __init mpc85xx_mds_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
- mpc85xx_mds_qeic_init();
}
static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index d3c540ee558f..14b5a61d49c1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -23,7 +23,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -44,10 +43,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -62,18 +57,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 720b0c0f03ba..b099f5607120 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -19,7 +19,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -31,26 +30,12 @@ static void __init twr_p1025_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- } else
- pr_err("Could not find qe-ic node\n");
-#endif
}
/* ************************************************************************
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index f170926ce4d1..a062efac398b 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -314,10 +314,10 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static void __init qe_ic_init(struct device_node *node, unsigned int flags)
{
+ void (*low_handler)(struct irq_desc *desc);
+ void (*high_handler)(struct irq_desc *desc);
struct qe_ic *qe_ic;
struct resource res;
u32 temp = 0, ret;
@@ -349,6 +349,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
kfree(qe_ic);
return;
}
+ if (qe_ic->virq_high != qe_ic->virq_low) {
+ low_handler = qe_ic_cascade_low_mpic;
+ high_handler = qe_ic_cascade_high_mpic;
+ } else {
+ low_handler = qe_ic_cascade_muxed_mpic;
+ high_handler = NULL;
+ }
/* default priority scheme is grouped. If spread mode is */
/* required, configure cicr accordingly. */
@@ -381,6 +388,22 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
}
}
+static int __init qe_ic_of_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return -ENODEV;
+ }
+ qe_ic_init(np, 0);
+ of_node_put(np);
+ return 0;
+}
+subsys_initcall(qe_ic_of_init);
+
void qe_ic_set_highest_priority(unsigned int virq, int high)
{
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index bfaa233d8328..a47a0d26acbd 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -54,16 +54,9 @@ enum qe_ic_grp_id {
};
#ifdef CONFIG_QUICC_ENGINE
-void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc));
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
#else
-static inline void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
-{}
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{ return 0; }
static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
--
2.23.0
The QUICC engine drivers use the powerpc-specific out_be32() etc. In
order to allow those drivers to build for other architectures, those
must be replaced by iowrite32be(). However, on powerpc, out_be32() is
a simple inline function while iowrite32be() is out-of-line. So in
order not to introduce a performance regression on powerpc when making
the drivers work on other architectures, introduce qe_io* helpers.
Also define the qe_{clr,set,clrset}bits* helpers in terms of these new
macros.
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
include/soc/fsl/qe/qe.h | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index a1aa4eb28f0c..9cac04c692fd 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -241,21 +241,37 @@ static inline int qe_alive_during_sleep(void)
#define qe_muram_offset cpm_muram_offset
#define qe_muram_dma cpm_muram_dma
-#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
-#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+#ifdef CONFIG_PPC32
+#define qe_iowrite8(val, addr) out_8(addr, val)
+#define qe_iowrite16be(val, addr) out_be16(addr, val)
+#define qe_iowrite32be(val, addr) out_be32(addr, val)
+#define qe_ioread8(addr) in_8(addr)
+#define qe_ioread16be(addr) in_be16(addr)
+#define qe_ioread32be(addr) in_be32(addr)
+#else
+#define qe_iowrite8(val, addr) iowrite8(val, addr)
+#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
+#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
+#define qe_ioread8(addr) ioread8(addr)
+#define qe_ioread16be(addr) ioread16be(addr)
+#define qe_ioread32be(addr) ioread32be(addr)
+#endif
+
+#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
+#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
-#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
-#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
+#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
-#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
-#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
+#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
#define qe_clrsetbits_be32(addr, clear, set) \
- iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_be16(addr, clear, set) \
- iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_8(addr, clear, set) \
- iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
/* Structure that defines QE firmware binary files.
*
--
2.23.0
In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().
Reviewed-by: Timur Tabi <[email protected]>
Signed-off-by: Rasmus Villemoes <[email protected]>
---
drivers/soc/fsl/qe/qe.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 456bd7416876..85737e6f5b62 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
+#include <linux/iopoll.h>
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
@@ -108,7 +109,8 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
- u32 ret;
+ u32 val;
+ int ret;
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
@@ -135,13 +137,12 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
}
/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
- /* On timeout (e.g. failure), the expression will be false (ret == 0),
- otherwise it will be true (ret == 1). */
+ ret = readx_poll_timeout_atomic(qe_ioread32be, &qe_immr->cp.cecr, val,
+ (val & QE_CR_FLG) == 0, 0, 100);
+ /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);
- return ret == 1;
+ return ret == 0;
}
EXPORT_SYMBOL(qe_issue_cmd);
--
2.23.0
On 11/28/19 8:55 AM, Rasmus Villemoes wrote:
> There have been several attempts in the past few years to allow
> building the QUICC engine drivers for platforms other than PPC32. This
> is yet another attempt.
>
> v5 can be found here:https://lore.kernel.org/lkml/[email protected]/
If it helps:
Entire series:
Acked-by: Timur Tabi <[email protected]>
I've worked on all code covered by this patchset except for the hdlc
driver. I don't know if my ACKs are acceptable to everyone, but you
have them regardless.
On 01/12/2019 17.10, Timur Tabi wrote:
> On 11/28/19 8:55 AM, Rasmus Villemoes wrote:
>> There have been several attempts in the past few years to allow
>> building the QUICC engine drivers for platforms other than PPC32. This
>> is yet another attempt.
>>
>> v5 can be found
>> here:https://lore.kernel.org/lkml/[email protected]/
>>
>
> If it helps:
>
> Entire series:
> Acked-by: Timur Tabi <[email protected]>
Thanks. I'll leave it to Li Yang whether to apply that - they already
all (except for the last-minute build fix) have your R-b.
Li Yang, any chance you could pick up these patches so they have plenty
of time in -next until 5.6?
Thanks,
Rasmus
On Mon, Dec 2, 2019 at 2:14 AM Rasmus Villemoes
<[email protected]> wrote:
>
> On 01/12/2019 17.10, Timur Tabi wrote:
> > On 11/28/19 8:55 AM, Rasmus Villemoes wrote:
> >> There have been several attempts in the past few years to allow
> >> building the QUICC engine drivers for platforms other than PPC32. This
> >> is yet another attempt.
> >>
> >> v5 can be found
> >> here:https://lore.kernel.org/lkml/[email protected]/
> >>
> >
> > If it helps:
> >
> > Entire series:
> > Acked-by: Timur Tabi <[email protected]>
>
> Thanks. I'll leave it to Li Yang whether to apply that - they already
> all (except for the last-minute build fix) have your R-b.
>
> Li Yang, any chance you could pick up these patches so they have plenty
> of time in -next until 5.6?
Sure. I will. I'm waiting for the Ack from David on the networking side.
Regards,
Leo
From: Li Yang <[email protected]>
Date: Mon, 2 Dec 2019 16:56:39 -0600
> On Mon, Dec 2, 2019 at 2:14 AM Rasmus Villemoes
> <[email protected]> wrote:
>>
>> On 01/12/2019 17.10, Timur Tabi wrote:
>> > On 11/28/19 8:55 AM, Rasmus Villemoes wrote:
>> >> There have been several attempts in the past few years to allow
>> >> building the QUICC engine drivers for platforms other than PPC32. This
>> >> is yet another attempt.
>> >>
>> >> v5 can be found
>> >> here:https://lore.kernel.org/lkml/[email protected]/
>> >>
>> >
>> > If it helps:
>> >
>> > Entire series:
>> > Acked-by: Timur Tabi <[email protected]>
>>
>> Thanks. I'll leave it to Li Yang whether to apply that - they already
>> all (except for the last-minute build fix) have your R-b.
>>
>> Li Yang, any chance you could pick up these patches so they have plenty
>> of time in -next until 5.6?
>
> Sure. I will. I'm waiting for the Ack from David on the networking side.
Acked-by: David S. Miller <[email protected]>
On Thu, Nov 28, 2019 at 8:59 AM Rasmus Villemoes
<[email protected]> wrote:
>
> There have been several attempts in the past few years to allow
> building the QUICC engine drivers for platforms other than PPC32. This
> is yet another attempt.
>
> v5 can be found here: https://lore.kernel.org/lkml/[email protected]/
>
> Changes in v6:
>
> - add various R-b, A-b tags
>
> - add a patch (48/49) fixing a build issue on ARM with CONFIG_SMP=y
>
> I added that patch last in the series, apart from the "allow to build
> on ARM" Kconfig change, to preserve the enumeration of the other
> patches from v5.
>
> 1-5 are about replacing in_be32 etc. in the core QE code (drivers/soc/fsl/qe).
>
> 6-8 handle miscellaneous other ppcisms.
>
> 9-21 deal with qe_ic: Simplifying the driver significantly by removing
> unused code, and removing the platform-specific initialization from
> arch/powerpc/.
>
> 22-25 deal with raw access to devicetree properties in native endianness.
>
> 26-34 makes drivers/tty/serial/ucc_uart.c (CONFIG_SERIAL_QE) ready to build on non-ppc.
>
> 35-46 deal with IS_ERR_VALUE() and some other things found while
> digging around that part of the code.
>
> 47 adds a PPC32 dependency to UCC_GETH - it has some of the same
> issues that have been fixed in the ucc_uart and ucc_hdlc cases. Nobody
> has requested that I allow that driver to be built for arm{,64} and
> reportedly, the hardware has only ever shipped on PPC SOCs. So instead
> of growing this series even bigger, I kept that addition. It's trivial
> to remove if somebody cares enough to fix the build errors/warnings
> and actually has a platform to test the result on.
>
> 48 fixes a build issue on ARM reported by the kbuild bot.
>
> Finally patch 49 lifts the PPC32 restriction from QUICC_ENGINE. At the
> request of Li Yang, it doesn't remove the PPC32 dependency but instead
> changes it to PPC|| ARM || ARM64 (or COMPILE_TEST), i.e. listing
> the platforms that may have a QE.
>
> The series has been built and booted on both an mpc8309-based platform
> (ppc) as well as an ls1021a-based platform (arm). The core QE code is
> exercised on both, while I could only test the ucc_uart on arm, since
> the uarts are not wired up on our mpc8309 board. Qiang Zhao reports
> that the ucc_hdlc driver does indeed work on a ls1043ardb (arm64)
> board.
Series applied for next on my soc tree. Thanks!
Regards,
Leo
>
> Rasmus Villemoes (49):
> soc: fsl: qe: remove space-before-tab
> soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
> soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers
> soc: fsl: qe: introduce qe_io{read,write}* wrappers
> soc: fsl: qe: avoid ppc-specific io accessors
> soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
> soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
> soc: fsl: qe: drop unneeded #includes
> soc: fsl: qe: drop assign-only high_active in qe_ic_init
> soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
> soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
> soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
> powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
> powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
> soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
> soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
> soc: fsl: qe: remove unused qe_ic_set_* functions
> soc: fsl: qe: don't use NO_IRQ in qe_ic.c
> soc: fsl: qe: make qe_ic_get_{low,high}_irq static
> soc: fsl: qe: simplify qe_ic_init()
> soc: fsl: qe: merge qe_ic.h headers into qe_ic.c
> soc: fsl: qe: qe.c: use of_property_read_* helpers
> soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle()
> soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu
> soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init()
> soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
> soc/fsl/qe/qe.h: update include path for cpm.h
> serial: ucc_uart: explicitly include soc/fsl/cpm.h
> serial: ucc_uart: replace ppc-specific IO accessors
> serial: ucc_uart: factor out soft_uart initialization
> serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
> serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()
> serial: ucc_uart: limit brg-frequency workaround to PPC32
> serial: ucc_uart: access __be32 field using be32_to_cpu
> soc: fsl: qe: change return type of cpm_muram_alloc() to s32
> soc: fsl: qe: make cpm_muram_free() return void
> soc: fsl: qe: make cpm_muram_free() ignore a negative offset
> soc: fsl: qe: drop broken lazy call of cpm_muram_init()
> soc: fsl: qe: refactor cpm_muram_alloc_common to prevent BUG on error
> path
> soc: fsl: qe: avoid IS_ERR_VALUE in ucc_slow.c
> soc: fsl: qe: drop use of IS_ERR_VALUE in qe_sdma_init()
> soc: fsl: qe: drop pointless check in qe_sdma_init()
> soc: fsl: qe: avoid IS_ERR_VALUE in ucc_fast.c
> net/wan/fsl_ucc_hdlc: avoid use of IS_ERR_VALUE()
> net/wan/fsl_ucc_hdlc: fix reading of __be16 registers
> net/wan/fsl_ucc_hdlc: reject muram offsets above 64K
> net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
> soc: fsl: qe: remove unused #include of asm/irq.h from ucc.c
> soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
>
> arch/powerpc/include/asm/cpm.h | 172 +-------
> arch/powerpc/platforms/83xx/km83xx.c | 3 +-
> arch/powerpc/platforms/83xx/misc.c | 23 --
> arch/powerpc/platforms/83xx/mpc832x_mds.c | 3 +-
> arch/powerpc/platforms/83xx/mpc832x_rdb.c | 3 +-
> arch/powerpc/platforms/83xx/mpc836x_mds.c | 3 +-
> arch/powerpc/platforms/83xx/mpc836x_rdk.c | 3 +-
> arch/powerpc/platforms/83xx/mpc83xx.h | 7 -
> arch/powerpc/platforms/85xx/common.c | 23 --
> arch/powerpc/platforms/85xx/corenet_generic.c | 12 -
> arch/powerpc/platforms/85xx/mpc85xx.h | 2 -
> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 28 --
> arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 18 -
> arch/powerpc/platforms/85xx/twr_p102x.c | 16 -
> drivers/net/ethernet/freescale/Kconfig | 2 +-
> drivers/net/wan/fsl_ucc_hdlc.c | 23 +-
> drivers/net/wan/fsl_ucc_hdlc.h | 2 +-
> drivers/soc/fsl/qe/Kconfig | 3 +-
> drivers/soc/fsl/qe/gpio.c | 34 +-
> drivers/soc/fsl/qe/qe.c | 104 ++---
> drivers/soc/fsl/qe/qe_common.c | 50 +--
> drivers/soc/fsl/qe/qe_ic.c | 285 ++++++-------
> drivers/soc/fsl/qe/qe_ic.h | 99 -----
> drivers/soc/fsl/qe/qe_io.c | 70 ++--
> drivers/soc/fsl/qe/qe_tdm.c | 8 +-
> drivers/soc/fsl/qe/ucc.c | 27 +-
> drivers/soc/fsl/qe/ucc_fast.c | 86 ++--
> drivers/soc/fsl/qe/ucc_slow.c | 60 ++-
> drivers/soc/fsl/qe/usb.c | 2 +-
> drivers/tty/serial/ucc_uart.c | 385 +++++++++---------
> include/soc/fsl/cpm.h | 171 ++++++++
> include/soc/fsl/qe/qe.h | 59 ++-
> include/soc/fsl/qe/qe_ic.h | 135 ------
> include/soc/fsl/qe/ucc_fast.h | 4 +-
> include/soc/fsl/qe/ucc_slow.h | 6 +-
> 35 files changed, 775 insertions(+), 1156 deletions(-)
> delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
> create mode 100644 include/soc/fsl/cpm.h
> delete mode 100644 include/soc/fsl/qe/qe_ic.h
>
> --
> 2.23.0
>
Hi Rasmus,
Le 28/11/2019 à 15:55, Rasmus Villemoes a écrit :
> The QUICC engine drivers use the powerpc-specific out_be32() etc. In
> order to allow those drivers to build for other architectures, those
> must be replaced by iowrite32be(). However, on powerpc, out_be32() is
> a simple inline function while iowrite32be() is out-of-line. So in
> order not to introduce a performance regression on powerpc when making
> the drivers work on other architectures, introduce qe_io* helpers.
>
> Also define the qe_{clr,set,clrset}bits* helpers in terms of these new
> macros.
Since commit https://github.com/linuxppc/linux/commit/894fa235eb4ca0bfa692dbe4932c2f940cdc8c1e
ioread/iowrite wrappers are also inlined on PPC32, so this commit can now be reverted.
Christophe
>
> Reviewed-by: Timur Tabi <[email protected]>
> Signed-off-by: Rasmus Villemoes <[email protected]>
> ---
> include/soc/fsl/qe/qe.h | 34 +++++++++++++++++++++++++---------
> 1 file changed, 25 insertions(+), 9 deletions(-)
>
> diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
> index a1aa4eb28f0c..9cac04c692fd 100644
> --- a/include/soc/fsl/qe/qe.h
> +++ b/include/soc/fsl/qe/qe.h
> @@ -241,21 +241,37 @@ static inline int qe_alive_during_sleep(void)
> #define qe_muram_offset cpm_muram_offset
> #define qe_muram_dma cpm_muram_dma
>
> -#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
> -#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
> +#ifdef CONFIG_PPC32
> +#define qe_iowrite8(val, addr) out_8(addr, val)
> +#define qe_iowrite16be(val, addr) out_be16(addr, val)
> +#define qe_iowrite32be(val, addr) out_be32(addr, val)
> +#define qe_ioread8(addr) in_8(addr)
> +#define qe_ioread16be(addr) in_be16(addr)
> +#define qe_ioread32be(addr) in_be32(addr)
> +#else
> +#define qe_iowrite8(val, addr) iowrite8(val, addr)
> +#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
> +#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
> +#define qe_ioread8(addr) ioread8(addr)
> +#define qe_ioread16be(addr) ioread16be(addr)
> +#define qe_ioread32be(addr) ioread32be(addr)
> +#endif
> +
> +#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
> +#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
>
> -#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
> -#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
> +#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
> +#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
>
> -#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
> -#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
> +#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
> +#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
>
> #define qe_clrsetbits_be32(addr, clear, set) \
> - iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
> + qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
> #define qe_clrsetbits_be16(addr, clear, set) \
> - iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
> + qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
> #define qe_clrsetbits_8(addr, clear, set) \
> - iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
> + qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
>
> /* Structure that defines QE firmware binary files.
> *
>
On Tue, Jan 19, 2021 at 11:35 AM Christophe Leroy
<[email protected]> wrote:
>
> Hi Rasmus,
>
> Le 28/11/2019 à 15:55, Rasmus Villemoes a écrit :
> > The QUICC engine drivers use the powerpc-specific out_be32() etc. In
> > order to allow those drivers to build for other architectures, those
> > must be replaced by iowrite32be(). However, on powerpc, out_be32() is
> > a simple inline function while iowrite32be() is out-of-line. So in
> > order not to introduce a performance regression on powerpc when making
> > the drivers work on other architectures, introduce qe_io* helpers.
> >
> > Also define the qe_{clr,set,clrset}bits* helpers in terms of these new
> > macros.
>
> Since commit https://github.com/linuxppc/linux/commit/894fa235eb4ca0bfa692dbe4932c2f940cdc8c1e
> ioread/iowrite wrappers are also inlined on PPC32, so this commit can now be reverted.
Yes. That will be great.
>
> Christophe
>
> >
> > Reviewed-by: Timur Tabi <[email protected]>
> > Signed-off-by: Rasmus Villemoes <[email protected]>
> > ---
> > include/soc/fsl/qe/qe.h | 34 +++++++++++++++++++++++++---------
> > 1 file changed, 25 insertions(+), 9 deletions(-)
> >
> > diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
> > index a1aa4eb28f0c..9cac04c692fd 100644
> > --- a/include/soc/fsl/qe/qe.h
> > +++ b/include/soc/fsl/qe/qe.h
> > @@ -241,21 +241,37 @@ static inline int qe_alive_during_sleep(void)
> > #define qe_muram_offset cpm_muram_offset
> > #define qe_muram_dma cpm_muram_dma
> >
> > -#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
> > -#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
> > +#ifdef CONFIG_PPC32
> > +#define qe_iowrite8(val, addr) out_8(addr, val)
> > +#define qe_iowrite16be(val, addr) out_be16(addr, val)
> > +#define qe_iowrite32be(val, addr) out_be32(addr, val)
> > +#define qe_ioread8(addr) in_8(addr)
> > +#define qe_ioread16be(addr) in_be16(addr)
> > +#define qe_ioread32be(addr) in_be32(addr)
> > +#else
> > +#define qe_iowrite8(val, addr) iowrite8(val, addr)
> > +#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
> > +#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
> > +#define qe_ioread8(addr) ioread8(addr)
> > +#define qe_ioread16be(addr) ioread16be(addr)
> > +#define qe_ioread32be(addr) ioread32be(addr)
> > +#endif
> > +
> > +#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
> > +#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
> >
> > -#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
> > -#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
> > +#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
> > +#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
> >
> > -#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
> > -#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
> > +#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
> > +#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
> >
> > #define qe_clrsetbits_be32(addr, clear, set) \
> > - iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
> > + qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
> > #define qe_clrsetbits_be16(addr, clear, set) \
> > - iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
> > + qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
> > #define qe_clrsetbits_8(addr, clear, set) \
> > - iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
> > + qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
> >
> > /* Structure that defines QE firmware binary files.
> > *
> >