From: Ranjan Kumar <[email protected]>
[ Upstream commit ee0017c3ed8a8abfa4d40e42f908fb38c31e7515 ]
If the driver detects that the controller is not ready before sending the
first IOC facts command, it will wait for a maximum of 10 seconds for it to
become ready. However, even if the controller becomes ready within 10
seconds, the driver will still issue a diagnostic reset.
Modify the driver to avoid sending a diag reset if the controller becomes
ready within the 10-second wait time.
Signed-off-by: Ranjan Kumar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Martin K. Petersen <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
---
drivers/scsi/mpt3sas/mpt3sas_base.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/scsi/mpt3sas/mpt3sas_base.c b/drivers/scsi/mpt3sas/mpt3sas_base.c
index e524e1fc53fa3..8325875bfc4ed 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_base.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_base.c
@@ -7238,7 +7238,9 @@ _base_wait_for_iocstate(struct MPT3SAS_ADAPTER *ioc, int timeout)
return -EFAULT;
}
- issue_diag_reset:
+ return 0;
+
+issue_diag_reset:
rc = _base_diag_reset(ioc);
return rc;
}
--
2.43.0
From: Takashi Sakamoto <[email protected]>
[ Upstream commit d0b06dc48fb15902d7da09c5c0861e7f042a9381 ]
When resetting the bus after a gap count error, use a long rather than
short bus reset.
IEEE 1394-1995 uses only long bus resets. IEEE 1394a adds the option of
short bus resets. When video or audio transmission is in progress and a
device is hot-plugged elsewhere on the bus, the resulting bus reset can
cause video frame drops or audio dropouts. Short bus resets reduce or
eliminate this problem. Accordingly, short bus resets are almost always
preferred.
However, on a mixed 1394/1394a bus, a short bus reset can trigger an
immediate additional bus reset. This double bus reset can be interpreted
differently by different nodes on the bus, resulting in an inconsistent gap
count after the bus reset. An inconsistent gap count will cause another bus
reset, leading to a neverending bus reset loop. This only happens for some
bus topologies, not for all mixed 1394/1394a buses.
By instead sending a long bus reset after a gap count inconsistency, we
avoid the doubled bus reset, restoring the bus to normal operation.
Signed-off-by: Adam Goldman <[email protected]>
Link: https://sourceforge.net/p/linux1394/mailman/message/58741624/
Signed-off-by: Takashi Sakamoto <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
---
drivers/firewire/core-card.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
diff --git a/drivers/firewire/core-card.c b/drivers/firewire/core-card.c
index be195ba834632..d446a72629414 100644
--- a/drivers/firewire/core-card.c
+++ b/drivers/firewire/core-card.c
@@ -500,7 +500,19 @@ static void bm_work(struct work_struct *work)
fw_notice(card, "phy config: new root=%x, gap_count=%d\n",
new_root_id, gap_count);
fw_send_phy_config(card, new_root_id, generation, gap_count);
- reset_bus(card, true);
+ /*
+ * Where possible, use a short bus reset to minimize
+ * disruption to isochronous transfers. But in the event
+ * of a gap count inconsistency, use a long bus reset.
+ *
+ * As noted in 1394a 8.4.6.2, nodes on a mixed 1394/1394a bus
+ * may set different gap counts after a bus reset. On a mixed
+ * 1394/1394a bus, a short bus reset can get doubled. Some
+ * nodes may treat the double reset as one bus reset and others
+ * may treat it as two, causing a gap count inconsistency
+ * again. Using a long bus reset prevents this.
+ */
+ reset_bus(card, card->gap_count != 0);
/* Will allocate broadcast channel after the reset. */
goto out;
}
--
2.43.0
From: Kailang Yang <[email protected]>
[ Upstream commit b34bf65838f7c6e785f62681605a538b73c2808c ]
It had pop noise from Headphone port when system reboot state.
If NID 58h Index 0x0 to fill default value, it will reduce pop noise.
Signed-off-by: Kailang Yang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Takashi Iwai <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
---
sound/pci/hda/patch_realtek.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/pci/hda/patch_realtek.c b/sound/pci/hda/patch_realtek.c
index a6e6ed1355abf..3a86f0fd78278 100644
--- a/sound/pci/hda/patch_realtek.c
+++ b/sound/pci/hda/patch_realtek.c
@@ -3675,6 +3675,7 @@ static void alc285_hp_init(struct hda_codec *codec)
int i, val;
int coef38, coef0d, coef36;
+ alc_write_coefex_idx(codec, 0x58, 0x00, 0x1888); /* write default value */
alc_update_coef_idx(codec, 0x4a, 1<<15, 1<<15); /* Reset HP JD */
coef38 = alc_read_coef_idx(codec, 0x38); /* Amp control */
coef0d = alc_read_coef_idx(codec, 0x0d); /* Digital Misc control */
--
2.43.0
From: Prike Liang <[email protected]>
[ Upstream commit c671ec01311b4744b377f98b0b4c6d033fe569b3 ]
Currently, GPU resets can now be performed successfully on the Raven
series. While GPU reset is required for the S3 suspend abort case.
So now can enable gpu reset for S3 abort cases on the Raven series.
Signed-off-by: Prike Liang <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Sasha Levin <[email protected]>
---
drivers/gpu/drm/amd/amdgpu/soc15.c | 45 +++++++++++++++++-------------
1 file changed, 25 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 6a3486f52d698..ef5b3eedc8615 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -605,11 +605,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
return AMD_RESET_METHOD_MODE1;
}
+static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
+{
+ u32 sol_reg;
+
+ sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
+
+ /* Will reset for the following suspend abort cases.
+ * 1) Only reset limit on APU side, dGPU hasn't checked yet.
+ * 2) S3 suspend abort and TOS already launched.
+ */
+ if (adev->flags & AMD_IS_APU && adev->in_s3 &&
+ !adev->suspend_complete &&
+ sol_reg)
+ return true;
+
+ return false;
+}
+
static int soc15_asic_reset(struct amdgpu_device *adev)
{
/* original raven doesn't have full asic reset */
- if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
- (adev->apu_flags & AMD_APU_IS_RAVEN2))
+ /* On the latest Raven, the GPU reset can be performed
+ * successfully. So now, temporarily enable it for the
+ * S3 suspend abort case.
+ */
+ if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
+ (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
+ !soc15_need_reset_on_resume(adev))
return 0;
switch (soc15_asic_reset_method(adev)) {
@@ -1490,24 +1513,6 @@ static int soc15_common_suspend(void *handle)
return soc15_common_hw_fini(adev);
}
-static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
-{
- u32 sol_reg;
-
- sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
-
- /* Will reset for the following suspend abort cases.
- * 1) Only reset limit on APU side, dGPU hasn't checked yet.
- * 2) S3 suspend abort and TOS already launched.
- */
- if (adev->flags & AMD_IS_APU && adev->in_s3 &&
- !adev->suspend_complete &&
- sol_reg)
- return true;
-
- return false;
-}
-
static int soc15_common_resume(void *handle)
{
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
--
2.43.0
On 2024-03-11 11:14, Sasha Levin wrote:
> From: Prike Liang <[email protected]>
>
> [ Upstream commit c671ec01311b4744b377f98b0b4c6d033fe569b3 ]
>
> Currently, GPU resets can now be performed successfully on the Raven
> series. While GPU reset is required for the S3 suspend abort case.
> So now can enable gpu reset for S3 abort cases on the Raven series.
This looks suspicious to me. I'm not sure what conditions made the GPU
reset successful. But unless all the changes involved were also
backported, this should probably not be applied to older kernel
branches. I'm speculating it may be related to the removal of AMD IOMMUv2.
Regards,
Felix
>
> Signed-off-by: Prike Liang <[email protected]>
> Acked-by: Alex Deucher <[email protected]>
> Signed-off-by: Alex Deucher <[email protected]>
> Signed-off-by: Sasha Levin <[email protected]>
> ---
> drivers/gpu/drm/amd/amdgpu/soc15.c | 45 +++++++++++++++++-------------
> 1 file changed, 25 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> index 6a3486f52d698..ef5b3eedc8615 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> @@ -605,11 +605,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
> return AMD_RESET_METHOD_MODE1;
> }
>
> +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> +{
> + u32 sol_reg;
> +
> + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> +
> + /* Will reset for the following suspend abort cases.
> + * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> + * 2) S3 suspend abort and TOS already launched.
> + */
> + if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> + !adev->suspend_complete &&
> + sol_reg)
> + return true;
> +
> + return false;
> +}
> +
> static int soc15_asic_reset(struct amdgpu_device *adev)
> {
> /* original raven doesn't have full asic reset */
> - if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> - (adev->apu_flags & AMD_APU_IS_RAVEN2))
> + /* On the latest Raven, the GPU reset can be performed
> + * successfully. So now, temporarily enable it for the
> + * S3 suspend abort case.
> + */
> + if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> + (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
> + !soc15_need_reset_on_resume(adev))
> return 0;
>
> switch (soc15_asic_reset_method(adev)) {
> @@ -1490,24 +1513,6 @@ static int soc15_common_suspend(void *handle)
> return soc15_common_hw_fini(adev);
> }
>
> -static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> -{
> - u32 sol_reg;
> -
> - sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> -
> - /* Will reset for the following suspend abort cases.
> - * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> - * 2) S3 suspend abort and TOS already launched.
> - */
> - if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> - !adev->suspend_complete &&
> - sol_reg)
> - return true;
> -
> - return false;
> -}
> -
> static int soc15_common_resume(void *handle)
> {
> struct amdgpu_device *adev = (struct amdgpu_device *)handle;
On Wed, Mar 13, 2024 at 4:12 PM Felix Kuehling <[email protected]> wrote:
>
> On 2024-03-11 11:14, Sasha Levin wrote:
> > From: Prike Liang <[email protected]>
> >
> > [ Upstream commit c671ec01311b4744b377f98b0b4c6d033fe569b3 ]
> >
> > Currently, GPU resets can now be performed successfully on the Raven
> > series. While GPU reset is required for the S3 suspend abort case.
> > So now can enable gpu reset for S3 abort cases on the Raven series.
>
> This looks suspicious to me. I'm not sure what conditions made the GPU
> reset successful. But unless all the changes involved were also
> backported, this should probably not be applied to older kernel
> branches. I'm speculating it may be related to the removal of AMD IOMMUv2.
>
We should get confirmation from Prike, but I think he tested this on
older kernels as well.
Alex
> Regards,
> Felix
>
>
> >
> > Signed-off-by: Prike Liang <[email protected]>
> > Acked-by: Alex Deucher <[email protected]>
> > Signed-off-by: Alex Deucher <[email protected]>
> > Signed-off-by: Sasha Levin <[email protected]>
> > ---
> > drivers/gpu/drm/amd/amdgpu/soc15.c | 45 +++++++++++++++++-------------
> > 1 file changed, 25 insertions(+), 20 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > index 6a3486f52d698..ef5b3eedc8615 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > @@ -605,11 +605,34 @@ soc15_asic_reset_method(struct amdgpu_device *adev)
> > return AMD_RESET_METHOD_MODE1;
> > }
> >
> > +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> > +{
> > + u32 sol_reg;
> > +
> > + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> > +
> > + /* Will reset for the following suspend abort cases.
> > + * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> > + * 2) S3 suspend abort and TOS already launched.
> > + */
> > + if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> > + !adev->suspend_complete &&
> > + sol_reg)
> > + return true;
> > +
> > + return false;
> > +}
> > +
> > static int soc15_asic_reset(struct amdgpu_device *adev)
> > {
> > /* original raven doesn't have full asic reset */
> > - if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> > - (adev->apu_flags & AMD_APU_IS_RAVEN2))
> > + /* On the latest Raven, the GPU reset can be performed
> > + * successfully. So now, temporarily enable it for the
> > + * S3 suspend abort case.
> > + */
> > + if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> > + (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
> > + !soc15_need_reset_on_resume(adev))
> > return 0;
> >
> > switch (soc15_asic_reset_method(adev)) {
> > @@ -1490,24 +1513,6 @@ static int soc15_common_suspend(void *handle)
> > return soc15_common_hw_fini(adev);
> > }
> >
> > -static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> > -{
> > - u32 sol_reg;
> > -
> > - sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> > -
> > - /* Will reset for the following suspend abort cases.
> > - * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> > - * 2) S3 suspend abort and TOS already launched.
> > - */
> > - if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> > - !adev->suspend_complete &&
> > - sol_reg)
> > - return true;
> > -
> > - return false;
> > -}
> > -
> > static int soc15_common_resume(void *handle)
> > {
> > struct amdgpu_device *adev = (struct amdgpu_device *)handle;
[AMD Official Use Only - General]
> From: Alex Deucher <[email protected]>
> Sent: Thursday, March 14, 2024 4:46 AM
> To: Kuehling, Felix <[email protected]>
> Cc: Sasha Levin <[email protected]>; [email protected];
> [email protected]; Liang, Prike <[email protected]>; Deucher,
> Alexander <[email protected]>; Koenig, Christian
> <[email protected]>; Pan, Xinhui <[email protected]>;
> [email protected]; [email protected]; Zhang, Hawking
> <[email protected]>; Lazar, Lijo <[email protected]>; Ma, Le
> <[email protected]>; Zhu, James <[email protected]>; Xiao, Shane
> <[email protected]>; Jiang, Sonny <[email protected]>; amd-
> [email protected]; [email protected]
> Subject: Re: [PATCH AUTOSEL 5.15 3/5] drm/amdgpu: Enable gpu reset for S3
> abort cases on Raven series
>
> On Wed, Mar 13, 2024 at 4:12 PM Felix Kuehling <[email protected]>
> wrote:
> >
> > On 2024-03-11 11:14, Sasha Levin wrote:
> > > From: Prike Liang <[email protected]>
> > >
> > > [ Upstream commit c671ec01311b4744b377f98b0b4c6d033fe569b3 ]
> > >
> > > Currently, GPU resets can now be performed successfully on the Raven
> > > series. While GPU reset is required for the S3 suspend abort case.
> > > So now can enable gpu reset for S3 abort cases on the Raven series.
> >
> > This looks suspicious to me. I'm not sure what conditions made the GPU
> > reset successful. But unless all the changes involved were also
> > backported, this should probably not be applied to older kernel
> > branches. I'm speculating it may be related to the removal of AMD
> IOMMUv2.
> >
>
> We should get confirmation from Prike, but I think he tested this on older
> kernels as well.
>
> Alex
>
> > Regards,
> > Felix
> >
The Raven/Raven2 series GPU reset function was enabled in some older kernel versions such as 5.5 but filtered out in more recent kernel driver versions. Therefore, this patch only applies to the latest kernel version, and it should be safe without affecting other cases by enabling the Raven GPU reset only on the S3 suspend abort case. From the Chrome kernel log indicating that the AMD IOMMUv2 driver is loaded, and with this patch triggering the GPU reset before the AMDGPU device reinitialization, it can effectively handle the S3 suspend abort resume problem on the Raven series.
Was the Raven GPU reset previously disabled due to the AMD IOMMUv2 driver? If so, based on the Chromebook's verification result, the Raven series GPU reset can probably be enabled with IOMMUv2 for other cases as well.
Thanks,
Prike
> >
> > >
> > > Signed-off-by: Prike Liang <[email protected]>
> > > Acked-by: Alex Deucher <[email protected]>
> > > Signed-off-by: Alex Deucher <[email protected]>
> > > Signed-off-by: Sasha Levin <[email protected]>
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/soc15.c | 45 +++++++++++++++++----------
> ---
> > > 1 file changed, 25 insertions(+), 20 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > index 6a3486f52d698..ef5b3eedc8615 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > @@ -605,11 +605,34 @@ soc15_asic_reset_method(struct
> amdgpu_device *adev)
> > > return AMD_RESET_METHOD_MODE1;
> > > }
> > >
> > > +static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> > > +{
> > > + u32 sol_reg;
> > > +
> > > + sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> > > +
> > > + /* Will reset for the following suspend abort cases.
> > > + * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> > > + * 2) S3 suspend abort and TOS already launched.
> > > + */
> > > + if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> > > + !adev->suspend_complete &&
> > > + sol_reg)
> > > + return true;
> > > +
> > > + return false;
> > > +}
> > > +
> > > static int soc15_asic_reset(struct amdgpu_device *adev)
> > > {
> > > /* original raven doesn't have full asic reset */
> > > - if ((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> > > - (adev->apu_flags & AMD_APU_IS_RAVEN2))
> > > + /* On the latest Raven, the GPU reset can be performed
> > > + * successfully. So now, temporarily enable it for the
> > > + * S3 suspend abort case.
> > > + */
> > > + if (((adev->apu_flags & AMD_APU_IS_RAVEN) ||
> > > + (adev->apu_flags & AMD_APU_IS_RAVEN2)) &&
> > > + !soc15_need_reset_on_resume(adev))
> > > return 0;
> > >
> > > switch (soc15_asic_reset_method(adev)) { @@ -1490,24 +1513,6
> > > @@ static int soc15_common_suspend(void *handle)
> > > return soc15_common_hw_fini(adev);
> > > }
> > >
> > > -static bool soc15_need_reset_on_resume(struct amdgpu_device *adev)
> > > -{
> > > - u32 sol_reg;
> > > -
> > > - sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
> > > -
> > > - /* Will reset for the following suspend abort cases.
> > > - * 1) Only reset limit on APU side, dGPU hasn't checked yet.
> > > - * 2) S3 suspend abort and TOS already launched.
> > > - */
> > > - if (adev->flags & AMD_IS_APU && adev->in_s3 &&
> > > - !adev->suspend_complete &&
> > > - sol_reg)
> > > - return true;
> > > -
> > > - return false;
> > > -}
> > > -
> > > static int soc15_common_resume(void *handle)
> > > {
> > > struct amdgpu_device *adev = (struct amdgpu_device *)handle;