Hi Rob,
This patch series contains a number of device tree bindings being
converted to YAML to help with validation.
There will be second, and possibly third rounds later on after those
land in.
Thanks!
Changes in v2:
- rebased against dt/next
- addressed Gregory's feedback on the GPIO binding change
- added Damien's Acked-by to the ATA binding patch
Florian Fainelli (14):
dt-bindings: mmc: Convert Broadcom STB SDHCI binding to YAML
dt-bindings: reset: Convert Broadcom STB reset to YAML
dt-bindings: pwm: Convert BCM7038 PWM binding to YAML
dt-bindings: rtc: Convert Broadcom STB waketimer to YAML
dt-bindings: gpio: Convert Broadcom STB GPIO to YAML
dt-binding: interrupt-controller: Convert BCM7038 L1 intc to YAML
dt-bindings: interrupt-controller: Convert BCM7120 L2 to YAML
dt-bindings: interrupt-controller: Merge BCM3380 with BCM7120
dt-bindings: interrupt-controller: Convert Broadcom STB L2 to YAML
dt-bindings: rng: Convert iProc RNG200 to YAML
dt-bindings: thermal: Convert Broadcom TMON to YAML
dt-bindings: ata: Convert Broadcom SATA to YAML
dt-bindings: bus: Convert GISB arbiter to YAML
dt-bindings: usb: Convert BDC to YAML
.../bindings/ata/brcm,sata-brcm.txt | 45 ------
.../bindings/ata/brcm,sata-brcm.yaml | 91 +++++++++++
.../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ----
.../bindings/bus/brcm,gisb-arb.yaml | 66 ++++++++
.../bindings/gpio/brcm,brcmstb-gpio.txt | 83 ----------
.../bindings/gpio/brcm,brcmstb-gpio.yaml | 105 ++++++++++++
.../brcm,bcm3380-l2-intc.txt | 39 -----
.../brcm,bcm7038-l1-intc.txt | 61 -------
.../brcm,bcm7038-l1-intc.yaml | 91 +++++++++++
.../brcm,bcm7120-l2-intc.txt | 88 -----------
.../brcm,bcm7120-l2-intc.yaml | 149 ++++++++++++++++++
.../interrupt-controller/brcm,l2-intc.txt | 31 ----
.../interrupt-controller/brcm,l2-intc.yaml | 64 ++++++++
.../bindings/mmc/brcm,sdhci-brcmstb.txt | 53 -------
.../bindings/mmc/brcm,sdhci-brcmstb.yaml | 100 ++++++++++++
.../bindings/pwm/brcm,bcm7038-pwm.txt | 20 ---
.../bindings/pwm/brcm,bcm7038-pwm.yaml | 43 +++++
.../bindings/reset/brcm,brcmstb-reset.txt | 27 ----
.../bindings/reset/brcm,brcmstb-reset.yaml | 48 ++++++
.../bindings/rng/brcm,iproc-rng200.txt | 16 --
.../bindings/rng/brcm,iproc-rng200.yaml | 29 ++++
.../bindings/rtc/brcm,brcmstb-waketimer.txt | 20 ---
.../bindings/rtc/brcm,brcmstb-waketimer.yaml | 44 ++++++
.../bindings/thermal/brcm,avs-tmon.txt | 23 ---
.../bindings/thermal/brcm,avs-tmon.yaml | 57 +++++++
.../devicetree/bindings/usb/brcm,bdc.txt | 29 ----
.../devicetree/bindings/usb/brcm,bdc.yaml | 46 ++++++
MAINTAINERS | 6 +-
28 files changed, 936 insertions(+), 572 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
delete mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.txt
create mode 100644 Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml
delete mode 100644 Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
create mode 100644 Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
delete mode 100644 Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
create mode 100644 Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml
delete mode 100644 Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt
create mode 100644 Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
delete mode 100644 Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
create mode 100644 Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml
delete mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt
create mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml
delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt
create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml
--
2.25.1
Convert the Broadcom STB SW_INIT style reset controller binding to YAML.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/reset/brcm,brcmstb-reset.txt | 27 -----------
.../bindings/reset/brcm,brcmstb-reset.yaml | 48 +++++++++++++++++++
2 files changed, 48 insertions(+), 27 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
create mode 100644 Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml
diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
deleted file mode 100644
index ee59409640f2..000000000000
--- a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-Broadcom STB SW_INIT-style reset controller
-===========================================
-
-Broadcom STB SoCs have a SW_INIT-style reset controller with separate
-SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
-reset lines.
-
-Please also refer to reset.txt in this directory for common reset
-controller binding usage.
-
-Required properties:
-- compatible: should be brcm,brcmstb-reset
-- reg: register base and length
-- #reset-cells: must be set to 1
-
-Example:
-
- reset: reset-controller@8404318 {
- compatible = "brcm,brcmstb-reset";
- reg = <0x8404318 0x30>;
- #reset-cells = <1>;
- };
-
- ðernet_switch {
- resets = <&reset 26>;
- reset-names = "switch";
- };
diff --git a/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml
new file mode 100644
index 000000000000..e00efa88a198
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/brcm,brcmstb-reset.yaml
@@ -0,0 +1,48 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/reset/brcm,brcmstb-reset.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Broadcom STB SW_INIT-style reset controller
+
+description:
+ Broadcom STB SoCs have a SW_INIT-style reset controller with separate
+ SET/CLEAR/STATUS registers and possibly multiple banks, each of 32 bit
+ reset lines.
+
+ Please also refer to reset.txt in this directory for common reset
+ controller binding usage.
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+properties:
+ compatible:
+ const: brcm,brcmstb-reset
+
+ reg:
+ maxItems: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ reset: reset-controller@8404318 {
+ compatible = "brcm,brcmstb-reset";
+ reg = <0x8404318 0x30>;
+ #reset-cells = <1>;
+ };
+
+ ethernet_switch {
+ resets = <&reset 26>;
+ reset-names = "switch";
+ };
--
2.25.1
Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML
to help with validation.
Acked-by: Damien Le Moal <[email protected]>
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/ata/brcm,sata-brcm.txt | 45 ---------
.../bindings/ata/brcm,sata-brcm.yaml | 91 +++++++++++++++++++
2 files changed, 91 insertions(+), 45 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
deleted file mode 100644
index b9ae4ce4a0a0..000000000000
--- a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-* Broadcom SATA3 AHCI Controller
-
-SATA nodes are defined to describe on-chip Serial ATA controllers.
-Each SATA controller should have its own node.
-
-Required properties:
-- compatible : should be one or more of
- "brcm,bcm7216-ahci"
- "brcm,bcm7425-ahci"
- "brcm,bcm7445-ahci"
- "brcm,bcm-nsp-ahci"
- "brcm,sata3-ahci"
- "brcm,bcm63138-ahci"
-- reg : register mappings for AHCI and SATA_TOP_CTRL
-- reg-names : "ahci" and "top-ctrl"
-- interrupts : interrupt mapping for SATA IRQ
-
-Optional properties:
-
-- reset: for "brcm,bcm7216-ahci" must be a valid reset phandle
- pointing to the RESCAL reset controller provider node.
-- reset-names: for "brcm,bcm7216-ahci", must be "rescal".
-
-Also see ahci-platform.txt.
-
-Example:
-
- sata@f045a000 {
- compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
- reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
- reg-names = "ahci", "top-ctrl";
- interrupts = <0 30 0>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- phys = <&sata_phy 0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- phys = <&sata_phy 1>;
- };
- };
diff --git a/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
new file mode 100644
index 000000000000..4098d56872ae
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom SATA3 AHCI Controller
+
+description:
+ SATA nodes are defined to describe on-chip Serial ATA controllers.
+ Each SATA controller should have its own node.
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+allOf:
+ - $ref: sata-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7216-ahci
+ - const: brcm,sata3-ahci
+ - items:
+ - enum:
+ - brcm,bcm7445-ahci
+ - const: brcm,sata3-ahci
+ - items:
+ - enum:
+ - brcm,bcm7425-ahci
+ - const: brcm,sata3-ahci
+ - items:
+ - const: brcm,bcm-nsp-ahci
+ - items:
+ - const: brcm,bcm63138-ahci
+
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ items:
+ - const: ahci
+ - const: top-ctrl
+
+ interrupts: true
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - brcm,bcm7216-ahci
+then:
+ properties:
+ resets: true
+ reset-names:
+ items:
+ - const: rescal
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - "#address-cells"
+ - "#size-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sata@f045a000 {
+ compatible = "brcm,bcm7445-ahci", "brcm,sata3-ahci";
+ reg = <0xf045a000 0xa9c>, <0xf0458040 0x24>;
+ reg-names = "ahci", "top-ctrl";
+ interrupts = <0 30 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ phys = <&sata_phy 0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ phys = <&sata_phy 1>;
+ };
+ };
--
2.25.1
Convert the Broadcom STB GISB bus arbiter to YAML to help with
validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../devicetree/bindings/bus/brcm,gisb-arb.txt | 34 ----------
.../bindings/bus/brcm,gisb-arb.yaml | 66 +++++++++++++++++++
2 files changed, 66 insertions(+), 34 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
create mode 100644 Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
deleted file mode 100644
index 10f6d0a8159d..000000000000
--- a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.txt
+++ /dev/null
@@ -1,34 +0,0 @@
-Broadcom GISB bus Arbiter controller
-
-Required properties:
-
-- compatible:
- "brcm,bcm7278-gisb-arb" for V7 28nm chips
- "brcm,gisb-arb" or "brcm,bcm7445-gisb-arb" for other 28nm chips
- "brcm,bcm7435-gisb-arb" for newer 40nm chips
- "brcm,bcm7400-gisb-arb" for older 40nm chips and all 65nm chips
- "brcm,bcm7038-gisb-arb" for 130nm chips
-- reg: specifies the base physical address and size of the registers
-- interrupts: specifies the two interrupts (timeout and TEA) to be used from
- the parent interrupt controller. A third optional interrupt may be specified
- for breakpoints.
-
-Optional properties:
-
-- brcm,gisb-arb-master-mask: 32-bits wide bitmask used to specify which GISB
- masters are valid at the system level
-- brcm,gisb-arb-master-names: string list of the litteral name of the GISB
- masters. Should match the number of bits set in brcm,gisb-master-mask and
- the order in which they appear
-
-Example:
-
-gisb-arb@f0400000 {
- compatible = "brcm,gisb-arb";
- reg = <0xf0400000 0x800>;
- interrupts = <0>, <2>;
- interrupt-parent = <&sun_l2_intc>;
-
- brcm,gisb-arb-master-mask = <0x7>;
- brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
-};
diff --git a/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
new file mode 100644
index 000000000000..483b019275cd
--- /dev/null
+++ b/Documentation/devicetree/bindings/bus/brcm,gisb-arb.yaml
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/brcm,gisb-arb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom GISB bus Arbiter controller
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7445-gisb-arb
+ - const: brcm,gisb-arb
+ - items:
+ - const: brcm,bcm7278-gisb-arb
+ - items:
+ - const: brcm,bcm7435-gisb-arb
+ - items:
+ - const: brcm,bcm7400-gisb-arb
+ - items:
+ - const: brcm,bcm7038-gisb-arb
+ - items:
+ - const: brcm,gisb-arb
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ minItems: 2
+ maxItems: 3
+
+ brcm,gisb-arb-master-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ 32-bits wide bitmask used to specify which GISB masters are valid at the
+ system level
+
+ brcm,gisb-arb-master-names:
+ $ref: /schemas/types.yaml#/definitions/string-array
+ description: >
+ String list of the litteral name of the GISB masters. Should match the
+ number of bits set in brcm,gisb-master-mask and the order in which they
+ appear
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ gisb-arb@f0400000 {
+ compatible = "brcm,gisb-arb";
+ reg = <0xf0400000 0x800>;
+ interrupts = <0>, <2>;
+ interrupt-parent = <&sun_l2_intc>;
+ brcm,gisb-arb-master-mask = <0x7>;
+ brcm,gisb-arb-master-names = "bsp_0", "scpu_0", "cpu_0";
+ };
--
2.25.1
Convert the Broadcom BDC device controller Device Tree binding to YAML
to help with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../devicetree/bindings/usb/brcm,bdc.txt | 29 ------------
.../devicetree/bindings/usb/brcm,bdc.yaml | 46 +++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 47 insertions(+), 30 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.txt
create mode 100644 Documentation/devicetree/bindings/usb/brcm,bdc.yaml
diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.txt b/Documentation/devicetree/bindings/usb/brcm,bdc.txt
deleted file mode 100644
index c9f52b97cef1..000000000000
--- a/Documentation/devicetree/bindings/usb/brcm,bdc.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-Broadcom USB Device Controller (BDC)
-====================================
-
-Required properties:
-
-- compatible: must be one of:
- "brcm,bdc-udc-v2"
- "brcm,bdc"
-- reg: the base register address and length
-- interrupts: the interrupt line for this controller
-
-Optional properties:
-
-On Broadcom STB platforms, these properties are required:
-
-- phys: phandle to one or two USB PHY blocks
- NOTE: Some SoC's have a single phy and some have
- USB 2.0 and USB 3.0 phys
-- clocks: phandle to the functional clock of this block
-
-Example:
-
- bdc@f0b02000 {
- compatible = "brcm,bdc-udc-v2";
- reg = <0xf0b02000 0xfc4>;
- interrupts = <0x0 0x60 0x0>;
- phys = <&usbphy_0 0x0>;
- clocks = <&sw_usbd>;
- };
diff --git a/Documentation/devicetree/bindings/usb/brcm,bdc.yaml b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml
new file mode 100644
index 000000000000..48831b62ab31
--- /dev/null
+++ b/Documentation/devicetree/bindings/usb/brcm,bdc.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/usb/brcm,bdc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom USB Device Controller (BDC)
+
+maintainers:
+ - Al Cooper <[email protected]>
+ - Florian Fainelli <[email protected]>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bdc-udc-v2
+ - brcm,bdc
+
+ reg:
+ maxItems: 1
+
+ interrupts: true
+
+ phys:
+ $ref: "/schemas/types.yaml#/definitions/phandle-array"
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ bdc@f0b02000 {
+ compatible = "brcm,bdc-udc-v2";
+ reg = <0xf0b02000 0xfc4>;
+ interrupts = <0x0 0x60 0x0>;
+ phys = <&usbphy_0 0x0>;
+ clocks = <&sw_usbd>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 2109b6fe8ea3..b18c7fa42a4f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3679,7 +3679,7 @@ M: Al Cooper <[email protected]>
L: [email protected]
L: [email protected]
S: Maintained
-F: Documentation/devicetree/bindings/usb/brcm,bdc.txt
+F: Documentation/devicetree/bindings/usb/brcm,bdc.yaml
F: drivers/usb/gadget/udc/bdc/
BROADCOM BMIPS CPUFREQ DRIVER
--
2.25.1
Convert the Broadcom STB BCM7038 PWM Device Tree binding to YAML to help
with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/pwm/brcm,bcm7038-pwm.txt | 20 ---------
.../bindings/pwm/brcm,bcm7038-pwm.yaml | 43 +++++++++++++++++++
2 files changed, 43 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
create mode 100644 Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
deleted file mode 100644
index 0e662d7f6bd1..000000000000
--- a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
-
-Required properties:
-
-- compatible: must be "brcm,bcm7038-pwm"
-- reg: physical base address and length for this controller
-- #pwm-cells: should be 2. See pwm.yaml in this directory for a description
- of the cells format
-- clocks: a phandle to the reference clock for this block which is fed through
- its internal variable clock frequency generator
-
-
-Example:
-
- pwm: pwm@f0408000 {
- compatible = "brcm,bcm7038-pwm";
- reg = <0xf0408000 0x28>;
- #pwm-cells = <2>;
- clocks = <&upg_fixed>;
- };
diff --git a/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
new file mode 100644
index 000000000000..4080e098f746
--- /dev/null
+++ b/Documentation/devicetree/bindings/pwm/brcm,bcm7038-pwm.yaml
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pwm/brcm,bcm7038-pwm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7038 PWM controller (BCM7xxx Set Top Box PWM controller)
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+allOf:
+ - $ref: pwm.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm7038-pwm
+
+ reg:
+ maxItems: 1
+
+ "#pwm-cells":
+ const: 2
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - "#pwm-cells"
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm: pwm@f0408000 {
+ compatible = "brcm,bcm7038-pwm";
+ reg = <0xf0408000 0x28>;
+ #pwm-cells = <2>;
+ clocks = <&upg_fixed>;
+ };
--
2.25.1
Convert the Broadcom STB BCM7038 Level 1 interrupt controller Device
Tree binding to YAML to help with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../brcm,bcm7038-l1-intc.txt | 61 -------------
.../brcm,bcm7038-l1-intc.yaml | 91 +++++++++++++++++++
2 files changed, 91 insertions(+), 61 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
deleted file mode 100644
index 5ddef1dc0c1a..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-Broadcom BCM7038-style Level 1 interrupt controller
-
-This block is a first level interrupt controller that is typically connected
-directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
-since BCM7038 has contained this hardware.
-
-Key elements of the hardware design include:
-
-- 64, 96, 128, or 160 incoming level IRQ lines
-
-- Most onchip peripherals are wired directly to an L1 input
-
-- A separate instance of the register set for each CPU, allowing individual
- peripheral IRQs to be routed to any CPU
-
-- Atomic mask/unmask operations
-
-- No polarity/level/edge settings
-
-- No FIFO or priority encoder logic; software is expected to read all
- 2-5 status words to determine which IRQs are pending
-
-Required properties:
-
-- compatible: should be "brcm,bcm7038-l1-intc"
-- reg: specifies the base physical address and size of the registers;
- the number of supported IRQs is inferred from the size argument
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
- node; valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
-- brcm,irq-can-wake: If present, this means the L1 controller can be used as a
- wakeup source for system suspend/resume.
-
-Optional properties:
-
-- brcm,int-fwd-mask: if present, a bit mask to indicate which interrupts
- have already been configured by the firmware and should be left unmanaged.
- This should have one 32-bit word per status/set/clear/mask group.
-
-If multiple reg ranges and interrupt-parent entries are present on an SMP
-system, the driver will allow IRQ SMP affinity to be set up through the
-/proc/irq/ interface. In the simplest possible configuration, only one
-reg range and one interrupt-parent is needed.
-
-Example:
-
-periph_intc: periph_intc@1041a400 {
- compatible = "brcm,bcm7038-l1-intc";
- reg = <0x1041a400 0x30 0x1041a600 0x30>;
-
- interrupt-controller;
- #interrupt-cells = <1>;
-
- interrupt-parent = <&cpu_intc>;
- interrupts = <2>, <3>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
new file mode 100644
index 000000000000..5ecb6faa70dc
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7038-l1-intc.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7038-l1-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7038-style Level 1 interrupt controller
+
+description: >
+ This block is a first level interrupt controller that is typically connected
+ directly to one of the HW INT lines on each CPU. Every BCM7xxx set-top chip
+ since BCM7038 has contained this hardware.
+
+ Key elements of the hardware design include:
+
+ - 64, 96, 128, or 160 incoming level IRQ lines
+
+ - Most onchip peripherals are wired directly to an L1 input
+
+ - A separate instance of the register set for each CPU, allowing individual
+ peripheral IRQs to be routed to any CPU
+
+ - Atomic mask/unmask operations
+
+ - No polarity/level/edge settings
+
+ - No FIFO or priority encoder logic; software is expected to read all
+ 2-5 status words to determine which IRQs are pending
+
+ If multiple reg ranges and interrupt-parent entries are present on an SMP
+ system, the driver will allow IRQ SMP affinity to be set up through the
+ /proc/irq/ interface. In the simplest possible configuration, only one
+ reg range and one interrupt-parent is needed.
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm7038-l1-intc
+
+ reg:
+ description: >
+ Specifies the base physical address and size of the registers
+ the number of supported IRQs is inferred from the size argument
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts:
+ description: >
+ Specifies the interrupt line(s) in the interrupt-parent controller node;
+ valid values depend on the type of parent interrupt controller
+
+ brcm,irq-can-wake:
+ type: boolean
+ description: >
+ If present, this means the L1 controller can be used as a
+ wakeup source for system suspend/resume.
+
+ brcm,int-fwd-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description:
+ If present, a bit mask to indicate which interrupts have already been
+ configured by the firmware and should be left unmanaged. This should
+ have one 32-bit word per status/set/clear/mask group.
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ periph_intc: interrupt-controller@1041a400 {
+ compatible = "brcm,bcm7038-l1-intc";
+ reg = <0x1041a400 0x30>, <0x1041a600 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>, <3>;
+ };
--
2.25.1
The two bindings are very similar and should be covered by the same
document, do that so we can get rid of an additional binding file.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../brcm,bcm3380-l2-intc.txt | 39 -------------------
.../brcm,bcm7120-l2-intc.yaml | 30 +++++++++++++-
2 files changed, 28 insertions(+), 41 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
deleted file mode 100644
index 37aea40d5430..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm3380-l2-intc.txt
+++ /dev/null
@@ -1,39 +0,0 @@
-Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
-
-This interrupt controller shows up in various forms on many BCM338x/BCM63xx
-chipsets. It has the following properties:
-
-- outputs a single interrupt signal to its interrupt controller parent
-
-- contains one or more enable/status word pairs, which often appear at
- different offsets in different blocks
-
-- no atomic set/clear operations
-
-Required properties:
-
-- compatible: should be "brcm,bcm3380-l2-intc"
-- reg: specifies one or more enable/status pairs, in the following format:
- <enable_reg 0x4 status_reg 0x4>...
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-Example:
-
-irq0_intc: interrupt-controller@10000020 {
- compatible = "brcm,bcm3380-l2-intc";
- reg = <0x10000024 0x4 0x1000002c 0x4>,
- <0x10000020 0x4 0x10000028 0x4>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&cpu_intc>;
- interrupts = <2>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
index e0c6dce40d13..8be7fe29e6a9 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Broadcom BCM7120-style Level 2 interrupt controller
+title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
maintainers:
- Florian Fainelli <[email protected]>
@@ -59,16 +59,31 @@ description: >
..
31 ........................ X
+ The BCM3380 Level 1 / Level 2 interrrupt controller shows up in various forms
+ on many BCM338x/BCM63xx chipsets. It has the following properties:
+
+ - outputs a single interrupt signal to its interrupt controller parent
+
+ - contains one or more enable/status word pairs, which often appear at
+ different offsets in different blocks
+
+ - no atomic set/clear operations
+
allOf:
- $ref: /schemas/interrupt-controller.yaml#
properties:
compatible:
- const: brcm,bcm7120-l2-intc
+ items:
+ - enum:
+ - brcm,bcm7120-l2-intc
+ - brcm,bcm3380-l2-intc
reg:
description: >
Specifies the base physical address and size of the registers
+ minItems: 1
+ maxItems: 4
interrupt-controller: true
@@ -121,3 +136,14 @@ examples:
brcm,int-map-mask = <0xeb8>, <0x140>;
brcm,int-fwd-mask = <0x7>;
};
+
+ - |
+ irq1_intc: interrupt-controller@10000020 {
+ compatible = "brcm,bcm3380-l2-intc";
+ reg = <0x10000024 0x4>, <0x1000002c 0x4>,
+ <0x10000020 0x4>, <0x10000028 0x4>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <2>;
+ };
--
2.25.1
Convert the Broadcom BCM7120 Level 2 interrupt controller Device Tree
binding to YAML to help with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../brcm,bcm7120-l2-intc.txt | 88 -------------
.../brcm,bcm7120-l2-intc.yaml | 123 ++++++++++++++++++
2 files changed, 123 insertions(+), 88 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
deleted file mode 100644
index addd86b6ca2f..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Broadcom BCM7120-style Level 2 interrupt controller
-
-This interrupt controller hardware is a second level interrupt controller that
-is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
-platforms. It can be found on BCM7xxx products starting with BCM7120.
-
-Such an interrupt controller has the following hardware design:
-
-- outputs multiple interrupts signals towards its interrupt controller parent
-
-- controls how some of the interrupts will be flowing, whether they will
- directly output an interrupt signal towards the interrupt controller parent,
- or if they will output an interrupt signal at this 2nd level interrupt
- controller, in particular for UARTs
-
-- has one 32-bit enable word and one 32-bit status word
-
-- no atomic set/clear operations
-
-- not all bits within the interrupt controller actually map to an interrupt
-
-The typical hardware layout for this controller is represented below:
-
-2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
-
-0 -----[ MUX ] ------------|==========> GIC interrupt 75
- \-----------\
- |
-1 -----[ MUX ] --------)---|==========> GIC interrupt 76
- \------------|
- |
-2 -----[ MUX ] --------)---|==========> GIC interrupt 77
- \------------|
- |
-3 ---------------------|
-4 ---------------------|
-5 ---------------------|
-7 ---------------------|---|===========> GIC interrupt 66
-9 ---------------------|
-10 --------------------|
-11 --------------------/
-
-6 ------------------------\
- |===========> GIC interrupt 64
-8 ------------------------/
-
-12 ........................ X
-13 ........................ X (not connected)
-..
-31 ........................ X
-
-Required properties:
-
-- compatible: should be "brcm,bcm7120-l2-intc"
-- reg: specifies the base physical address and size of the registers
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an interrupt
- source, should be 1.
-- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
- node, valid values depend on the type of parent interrupt controller
-- brcm,int-map-mask: 32-bits bit mask describing how many and which interrupts
- are wired to this 2nd level interrupt controller, and how they match their
- respective interrupt parents. Should match exactly the number of interrupts
- specified in the 'interrupts' property.
-
-Optional properties:
-
-- brcm,irq-can-wake: if present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-- brcm,int-fwd-mask: if present, a bit mask to configure the interrupts which
- have a mux gate, typically UARTs. Setting these bits will make their
- respective interrupt outputs bypass this 2nd level interrupt controller
- completely; it is completely transparent for the interrupt controller
- parent. This should have one 32-bit word per enable/status pair.
-
-Example:
-
-irq0_intc: interrupt-controller@f0406800 {
- compatible = "brcm,bcm7120-l2-intc";
- interrupt-parent = <&intc>;
- #interrupt-cells = <1>;
- reg = <0xf0406800 0x8>;
- interrupt-controller;
- interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
- brcm,int-map-mask = <0xeb8>, <0x140>;
- brcm,int-fwd-mask = <0x7>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
new file mode 100644
index 000000000000..e0c6dce40d13
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm7120-l2-intc.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM7120-style Level 2 interrupt controller
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+description: >
+ This interrupt controller hardware is a second level interrupt controller that
+ is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
+ platforms. It can be found on BCM7xxx products starting with BCM7120.
+
+ Such an interrupt controller has the following hardware design:
+
+ - outputs multiple interrupts signals towards its interrupt controller parent
+
+ - controls how some of the interrupts will be flowing, whether they will
+ directly output an interrupt signal towards the interrupt controller parent,
+ or if they will output an interrupt signal at this 2nd level interrupt
+ controller, in particular for UARTs
+
+ - has one 32-bit enable word and one 32-bit status word
+
+ - no atomic set/clear operations
+
+ - not all bits within the interrupt controller actually map to an interrupt
+
+ The typical hardware layout for this controller is represented below:
+
+ 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
+
+ 0 -----[ MUX ] ------------|==========> GIC interrupt 75
+ \-----------\
+ |
+ 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
+ \------------|
+ |
+ 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
+ \------------|
+ |
+ 3 ---------------------|
+ 4 ---------------------|
+ 5 ---------------------|
+ 7 ---------------------|---|===========> GIC interrupt 66
+ 9 ---------------------|
+ 10 --------------------|
+ 11 --------------------/
+
+ 6 ------------------------\
+ |===========> GIC interrupt 64
+ 8 ------------------------/
+
+ 12 ........................ X
+ 13 ........................ X (not connected)
+ ..
+ 31 ........................ X
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ const: brcm,bcm7120-l2-intc
+
+ reg:
+ description: >
+ Specifies the base physical address and size of the registers
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts: true
+
+ "brcm,int-map-mask":
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: >
+ 32-bits bit mask describing how many and which interrupts are wired to
+ this 2nd level interrupt controller, and how they match their respective
+ interrupt parents. Should match exactly the number of interrupts
+ specified in the 'interrupts' property.
+
+ brcm,irq-can-wake:
+ type: boolean
+ description: >
+ If present, this means the L2 controller can be used as a wakeup source
+ for system suspend/resume.
+
+ brcm,int-fwd-mask:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: >
+ if present, a bit mask to configure the interrupts which have a mux gate,
+ typically UARTs. Setting these bits will make their respective interrupt
+ outputs bypass this 2nd level interrupt controller completely; it is
+ completely transparent for the interrupt controller parent. This should
+ have one 32-bit word per enable/status pair.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+examples:
+ - |
+ irq0_intc: interrupt-controller@f0406800 {
+ compatible = "brcm,bcm7120-l2-intc";
+ interrupt-parent = <&intc>;
+ #interrupt-cells = <1>;
+ reg = <0xf0406800 0x8>;
+ interrupt-controller;
+ interrupts = <0x0 0x42 0x0>, <0x0 0x40 0x0>;
+ brcm,int-map-mask = <0xeb8>, <0x140>;
+ brcm,int-fwd-mask = <0x7>;
+ };
--
2.25.1
Convert the Broadcom STB L2 generic Level 2 interrupt controller Device
Tree binding to YAML to help with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../interrupt-controller/brcm,l2-intc.txt | 31 ---------
.../interrupt-controller/brcm,l2-intc.yaml | 64 +++++++++++++++++++
2 files changed, 64 insertions(+), 31 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
deleted file mode 100644
index 021cf822395c..000000000000
--- a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-Broadcom Generic Level 2 Interrupt Controller
-
-Required properties:
-
-- compatible: should be one of:
- "brcm,hif-spi-l2-intc" or
- "brcm,upg-aux-aon-l2-intc" or
- "brcm,l2-intc" for latched interrupt controllers
- should be "brcm,bcm7271-l2-intc" for level interrupt controllers
-- reg: specifies the base physical address and size of the registers
-- interrupt-controller: identifies the node as an interrupt controller
-- #interrupt-cells: specifies the number of cells needed to encode an
- interrupt source. Should be 1.
-- interrupts: specifies the interrupt line in the interrupt-parent irq space
- to be used for cascading
-
-Optional properties:
-
-- brcm,irq-can-wake: If present, this means the L2 controller can be used as a
- wakeup source for system suspend/resume.
-
-Example:
-
-hif_intr2_intc: interrupt-controller@f0441000 {
- compatible = "brcm,l2-intc";
- reg = <0xf0441000 0x30>;
- interrupt-controller;
- #interrupt-cells = <1>;
- interrupt-parent = <&intc>;
- interrupts = <0x0 0x20 0x0>;
-};
diff --git a/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
new file mode 100644
index 000000000000..b1e812e7c714
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Generic Level 2 Interrupt Controller
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,hif-spi-l2-intc
+ - brcm,upg-aux-aon-l2-intc
+ - const: brcm,l2-intc
+ - items:
+ - const: brcm,bcm7271-l2-intc
+ - items:
+ - const: brcm,l2-intc
+
+ reg:
+ maxItems: 1
+ description: >
+ Specifies the base physical address and size of the registers
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 1
+
+ interrupts: true
+
+ brcm,irq-can-wake:
+ type: boolean
+ description: >
+ If present, this means the L2 controller can be used as a wakeup source
+ for system suspend/resume.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - interrupts
+
+examples:
+ - |
+ hif_intr2_intc: interrupt-controller@f0441000 {
+ compatible = "brcm,l2-intc";
+ reg = <0xf0441000 0x30>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <0x0 0x20 0x0>;
+ };
--
2.25.1
Convert the Broadcom iProc RNG200 HWRNG Device Tree binding to YAML to
help with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/rng/brcm,iproc-rng200.txt | 16 ----------
.../bindings/rng/brcm,iproc-rng200.yaml | 29 +++++++++++++++++++
2 files changed, 29 insertions(+), 16 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt
create mode 100644 Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt
deleted file mode 100644
index 802523196ee5..000000000000
--- a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-HWRNG support for the iproc-rng200 driver
-
-Required properties:
-- compatible : Must be one of:
- "brcm,bcm2711-rng200"
- "brcm,bcm7211-rng200"
- "brcm,bcm7278-rng200"
- "brcm,iproc-rng200"
-- reg : base address and size of control register block
-
-Example:
-
-rng {
- compatible = "brcm,iproc-rng200";
- reg = <0x18032000 0x28>;
-};
diff --git a/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
new file mode 100644
index 000000000000..53baaec966e0
--- /dev/null
+++ b/Documentation/devicetree/bindings/rng/brcm,iproc-rng200.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/rng/brcm,iproc-rng200.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: HWRNG support for the iproc-rng200 driver
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - brcm,bcm2711-rng200
+ - brcm,bcm7211-rng200
+ - brcm,bcm7278-rng200
+ - brcm,iproc-rng200
+ reg:
+ description: base address and size of control register block
+
+additionalProperties: false
+
+examples:
+ - |
+ rng@18032000 {
+ compatible = "brcm,iproc-rng200";
+ reg = <0x18032000 0x28>;
+ };
--
2.25.1
Convert the Broadcom AVS TMON Device Tree binding to YAML to help with
validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/thermal/brcm,avs-tmon.txt | 23 --------
.../bindings/thermal/brcm,avs-tmon.yaml | 57 +++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 58 insertions(+), 24 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt
create mode 100644 Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml
diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt
deleted file mode 100644
index 74a9ef09db8b..000000000000
--- a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-* Broadcom STB thermal management
-
-Thermal management core, provided by the AVS TMON hardware block.
-
-Required properties:
-- compatible: must be one of:
- "brcm,avs-tmon-bcm7216"
- "brcm,avs-tmon-bcm7445"
- "brcm,avs-tmon"
-- reg: address range for the AVS TMON registers
-- interrupts: temperature monitor interrupt, for high/low threshold triggers,
- required except for "brcm,avs-tmon-bcm7216"
-- interrupt-names: should be "tmon"
-
-Example:
-
- thermal@f04d1500 {
- compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
- reg = <0xf04d1500 0x28>;
- interrupts = <0x6>;
- interrupt-names = "tmon";
- interrupt-parent = <&avs_host_l2_intc>;
- };
diff --git a/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml
new file mode 100644
index 000000000000..fb5c273b8bc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/brcm,avs-tmon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB thermal management
+
+description: Thermal management core, provided by the AVS TMON hardware block.
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+allOf:
+ - $ref: thermal-sensor.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,avs-tmon-bcm7216
+ - brcm,avs-tmon-bcm7445
+ - const: brcm,avs-tmon
+
+ reg:
+ maxItems: 1
+ description: >
+ Address range for the AVS TMON registers
+
+ interrupts:
+ maxItems: 1
+
+ interrupt-names:
+ items:
+ - const: tmon
+
+ "#thermal-sensor-cells":
+ const: 0
+
+additionalProperties: false
+
+required:
+ - compatible
+ - reg
+ - "#thermal-sensor-cells"
+
+examples:
+ - |
+ thermal@f04d1500 {
+ compatible = "brcm,avs-tmon-bcm7445", "brcm,avs-tmon";
+ reg = <0xf04d1500 0x28>;
+ interrupts = <0x6>;
+ interrupt-names = "tmon";
+ interrupt-parent = <&avs_host_l2_intc>;
+ #thermal-sensor-cells = <0>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 9ac67c885159..2109b6fe8ea3 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3936,7 +3936,7 @@ M: Markus Mayer <[email protected]>
M: [email protected]
L: [email protected]
S: Maintained
-F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.txt
+F: Documentation/devicetree/bindings/thermal/brcm,avs-tmon.yaml
F: drivers/thermal/broadcom/brcmstb*
BROADCOM STB DPFE DRIVER
--
2.25.1
Convert the Broadcom STB GPIO Device Tree binding to YAML to help with
validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/gpio/brcm,brcmstb-gpio.txt | 83 --------------
.../bindings/gpio/brcm,brcmstb-gpio.yaml | 105 ++++++++++++++++++
MAINTAINERS | 2 +-
3 files changed, 106 insertions(+), 84 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
deleted file mode 100644
index 5d468ecd1809..000000000000
--- a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
+++ /dev/null
@@ -1,83 +0,0 @@
-Broadcom STB "UPG GIO" GPIO controller
-
-The controller's registers are organized as sets of eight 32-bit
-registers with each set controlling a bank of up to 32 pins. A single
-interrupt is shared for all of the banks handled by the controller.
-
-Required properties:
-
-- compatible:
- Must be "brcm,brcmstb-gpio"
-
-- reg:
- Define the base and range of the I/O address space containing
- the brcmstb GPIO controller registers
-
-- #gpio-cells:
- Should be <2>. The first cell is the pin number (within the controller's
- pin space), and the second is used for the following:
- bit[0]: polarity (0 for active-high, 1 for active-low)
-
-- gpio-controller:
- Specifies that the node is a GPIO controller.
-
-- brcm,gpio-bank-widths:
- Number of GPIO lines for each bank. Number of elements must
- correspond to number of banks suggested by the 'reg' property.
-
-Optional properties:
-
-- interrupts:
- The interrupt shared by all GPIO lines for this controller.
-
-- interrupts-extended:
- Alternate form of specifying interrupts and parents that allows for
- multiple parents. This takes precedence over 'interrupts' and
- 'interrupt-parent'. Wakeup-capable GPIO controllers often route their
- wakeup interrupt lines through a different interrupt controller than the
- primary interrupt line, making this property necessary.
-
-- #interrupt-cells:
- Should be <2>. The first cell is the GPIO number, the second should specify
- flags. The following subset of flags is supported:
- - bits[3:0] trigger type and level flags
- 1 = low-to-high edge triggered
- 2 = high-to-low edge triggered
- 4 = active high level-sensitive
- 8 = active low level-sensitive
- Valid combinations are 1, 2, 3, 4, 8.
- See also Documentation/devicetree/bindings/interrupt-controller/interrupts.txt
-
-- interrupt-controller:
- Marks the device node as an interrupt controller
-
-- wakeup-source:
- GPIOs for this controller can be used as a wakeup source
-
-Example:
- upg_gio: gpio@f040a700 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
- gpio-controller;
- interrupt-controller;
- reg = <0xf040a700 0x80>;
- interrupt-parent = <&irq0_intc>;
- interrupts = <0x6>;
- brcm,gpio-bank-widths = <32 32 32 24>;
- };
-
- upg_gio_aon: gpio@f04172c0 {
- #gpio-cells = <2>;
- #interrupt-cells = <2>;
- compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
- gpio-controller;
- interrupt-controller;
- reg = <0xf04172c0 0x40>;
- interrupt-parent = <&irq0_aon_intc>;
- interrupts = <0x6>;
- interrupts-extended = <&irq0_aon_intc 0x6>,
- <&aon_pm_l2_intc 0x5>;
- wakeup-source;
- brcm,gpio-bank-widths = <18 4>;
- };
diff --git a/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
new file mode 100644
index 000000000000..8c27932df2c5
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
@@ -0,0 +1,105 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/brcm,brcmstb-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB "UPG GIO" GPIO controller
+
+description: >
+ The controller's registers are organized as sets of eight 32-bit
+ registers with each set controlling a bank of up to 32 pins. A single
+ interrupt is shared for all of the banks handled by the controller.
+
+maintainers:
+ - Doug Berger <[email protected]>
+ - Florian Fainelli <[email protected]>
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - brcm,bcm7445-gpio
+ - const: brcm,brcmstb-gpio
+
+ reg:
+ maxItems: 1
+ description: >
+ Define the base and range of the I/O address space containing
+ the brcmstb GPIO controller registers
+
+ "#gpio-cells":
+ const: 2
+ description: >
+ The first cell is the pin number (within the controller's
+ pin space), and the second is used for the following:
+ bit[0]: polarity (0 for active-high, 1 for active-low)
+
+ gpio-controller: true
+
+ "brcm,gpio-bank-widths":
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ description: >
+ Number of GPIO lines for each bank. Number of elements must
+ correspond to number of banks suggested by the 'reg' property.
+
+ interrupts:
+ maxItems: 1
+ description: >
+ The interrupt shared by all GPIO lines for this controller.
+
+ "#interrupt-cells":
+ const: 2
+ description: |
+ The first cell is the GPIO number, the second should specify
+ flags. The following subset of flags is supported:
+ - bits[3:0] trigger type and level flags
+ 1 = low-to-high edge triggered
+ 2 = high-to-low edge triggered
+ 4 = active high level-sensitive
+ 8 = active low level-sensitive
+ Valid combinations are 1, 2, 3, 4, 8.
+
+ interrupt-controller: true
+
+ wakeup-source:
+ type: boolean
+ description: >
+ GPIOs for this controller can be used as a wakeup source
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - "brcm,gpio-bank-widths"
+
+additionalProperties: false
+
+examples:
+ - |
+ upg_gio: gpio@f040a700 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf040a700 0x80>;
+ interrupt-parent = <&irq0_intc>;
+ interrupts = <0x6>;
+ brcm,gpio-bank-widths = <32 32 32 24>;
+ };
+
+ upg_gio_aon: gpio@f04172c0 {
+ #gpio-cells = <2>;
+ #interrupt-cells = <2>;
+ compatible = "brcm,bcm7445-gpio", "brcm,brcmstb-gpio";
+ gpio-controller;
+ interrupt-controller;
+ reg = <0xf04172c0 0x40>;
+ interrupt-parent = <&irq0_aon_intc>;
+ interrupts = <0x6>;
+ wakeup-source;
+ brcm,gpio-bank-widths = <18 4>;
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a2345ce8521..9ac67c885159 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3761,7 +3761,7 @@ BROADCOM BRCMSTB GPIO DRIVER
M: Gregory Fong <[email protected]>
L: [email protected]
S: Supported
-F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
+F: Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
F: drivers/gpio/gpio-brcmstb.c
BROADCOM BRCMSTB I2C DRIVER
--
2.25.1
Convert the Broadcom STB waketimer Device Tree binding to YAML to help
with validation.
Signed-off-by: Florian Fainelli <[email protected]>
---
.../bindings/rtc/brcm,brcmstb-waketimer.txt | 20 ---------
.../bindings/rtc/brcm,brcmstb-waketimer.yaml | 44 +++++++++++++++++++
2 files changed, 44 insertions(+), 20 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
create mode 100644 Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml
diff --git a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
deleted file mode 100644
index d946f28502b3..000000000000
--- a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Broadcom STB wake-up Timer
-
-The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
-ability to wake up the system from low-power suspend/standby modes.
-
-Required properties:
-- compatible : should contain "brcm,brcmstb-waketimer"
-- reg : the register start and length for the WKTMR block
-- interrupts : The TIMER interrupt
-- clocks : The phandle to the UPG fixed clock (27Mhz domain)
-
-Example:
-
-waketimer@f0411580 {
- compatible = "brcm,brcmstb-waketimer";
- reg = <0xf0411580 0x14>;
- interrupts = <0x3>;
- interrupt-parent = <&aon_pm_l2_intc>;
- clocks = <&upg_fixed>;
-};
diff --git a/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml
new file mode 100644
index 000000000000..9fe079917a98
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/brcm,brcmstb-waketimer.yaml
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/rtc/brcm,brcmstb-waketimer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom STB wake-up Timer
+
+maintainers:
+ - Florian Fainelli <[email protected]>
+
+description:
+ The Broadcom STB wake-up timer provides a 27Mhz resolution timer, with the
+ ability to wake up the system from low-power suspend/standby modes.
+
+allOf:
+ - $ref: "rtc.yaml#"
+
+properties:
+ compatible:
+ const: brcm,brcmstb-waketimer
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ description: the TIMER interrupt
+ maxItems: 1
+
+ clocks:
+ description: clock reference in the 27MHz domain
+ maxItems: 1
+
+additionalProperties: false
+
+examples:
+ - |
+ rtc@f0411580 {
+ compatible = "brcm,brcmstb-waketimer";
+ reg = <0xf0411580 0x14>;
+ interrupts = <0x3>;
+ interrupt-parent = <&aon_pm_l2_intc>;
+ clocks = <&upg_fixed>;
+ };
--
2.25.1
On Mon, Dec 6, 2021 at 10:26 AM Florian Fainelli <[email protected]> wrote:
>
> Convert the Broadcom STB GPIO Device Tree binding to YAML to help with
> validation.
>
> Signed-off-by: Florian Fainelli <[email protected]>
Acked-by: Gregory Fong <[email protected]>
Hello,
On Mon, Dec 06, 2021 at 10:26:05AM -0800, Florian Fainelli wrote:
> Convert the Broadcom STB BCM7038 PWM Device Tree binding to YAML to help
> with validation.
>
> Signed-off-by: Florian Fainelli <[email protected]>
Acked-by: Uwe Kleine-K?nig <[email protected]>
I assume you intend to take these patches all together via the bcm tree?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | https://www.pengutronix.de/ |
On Mon, 06 Dec 2021 10:26:07 -0800, Florian Fainelli wrote:
> Convert the Broadcom STB GPIO Device Tree binding to YAML to help with
> validation.
>
> Signed-off-by: Florian Fainelli <[email protected]>
> ---
> .../bindings/gpio/brcm,brcmstb-gpio.txt | 83 --------------
> .../bindings/gpio/brcm,brcmstb-gpio.yaml | 105 ++++++++++++++++++
> MAINTAINERS | 2 +-
> 3 files changed, 106 insertions(+), 84 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
> create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1564132
gpio@4172c0: interrupts-extended: [[6, 6], [7, 5]] is too long
arch/arm/boot/dts/bcm7445-bcm97445svmb.dt.yaml
On Mon, 06 Dec 2021 10:26:11 -0800, Florian Fainelli wrote:
> Convert the Broadcom STB L2 generic Level 2 interrupt controller Device
> Tree binding to YAML to help with validation.
>
> Signed-off-by: Florian Fainelli <[email protected]>
> ---
> .../interrupt-controller/brcm,l2-intc.txt | 31 ---------
> .../interrupt-controller/brcm,l2-intc.yaml | 64 +++++++++++++++++++
> 2 files changed, 64 insertions(+), 31 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1564135
interrupt-controller@3e1000: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+'
arch/arm/boot/dts/bcm7445-bcm97445svmb.dt.yaml
interrupt-controller@7ef00100: compatible: 'oneOf' conditional failed, one must be fixed:
arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml
On Mon, 06 Dec 2021 10:26:14 -0800, Florian Fainelli wrote:
> Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML
> to help with validation.
>
> Acked-by: Damien Le Moal <[email protected]>
> Signed-off-by: Florian Fainelli <[email protected]>
> ---
> .../bindings/ata/brcm,sata-brcm.txt | 45 ---------
> .../bindings/ata/brcm,sata-brcm.yaml | 91 +++++++++++++++++++
> 2 files changed, 91 insertions(+), 45 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
> create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
>
Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.
Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.
Full log is available here: https://patchwork.ozlabs.org/patch/1564108
ahci@41000: $nodename:0: 'ahci@41000' does not match '^sata(@.*)?$'
arch/arm/boot/dts/bcm958522er.dt.yaml
arch/arm/boot/dts/bcm958525er.dt.yaml
arch/arm/boot/dts/bcm958525xmc.dt.yaml
arch/arm/boot/dts/bcm958622hr.dt.yaml
arch/arm/boot/dts/bcm958623hr.dt.yaml
arch/arm/boot/dts/bcm958625hr.dt.yaml
arch/arm/boot/dts/bcm958625k.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64w.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx65.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx65w.dt.yaml
arch/arm/boot/dts/bcm988312hr.dt.yaml
ahci@41000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dma-coherent', 'sata-port@0', 'sata-port@1' were unexpected)
arch/arm/boot/dts/bcm958522er.dt.yaml
arch/arm/boot/dts/bcm958525er.dt.yaml
arch/arm/boot/dts/bcm958525xmc.dt.yaml
arch/arm/boot/dts/bcm958622hr.dt.yaml
arch/arm/boot/dts/bcm958623hr.dt.yaml
arch/arm/boot/dts/bcm958625hr.dt.yaml
arch/arm/boot/dts/bcm958625k.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64w.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx65.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx65w.dt.yaml
arch/arm/boot/dts/bcm988312hr.dt.yaml
ahci@41000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'sata-port@0', 'sata-port@1' were unexpected)
arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dt.yaml
arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dt.yaml
sata@a000: compatible: 'oneOf' conditional failed, one must be fixed:
arch/arm/boot/dts/bcm963138dvt.dt.yaml
On 12/7/21 6:58 AM, Rob Herring wrote:
> On Mon, 06 Dec 2021 10:26:07 -0800, Florian Fainelli wrote:
>> Convert the Broadcom STB GPIO Device Tree binding to YAML to help with
>> validation.
>>
>> Signed-off-by: Florian Fainelli <[email protected]>
>> ---
>> .../bindings/gpio/brcm,brcmstb-gpio.txt | 83 --------------
>> .../bindings/gpio/brcm,brcmstb-gpio.yaml | 105 ++++++++++++++++++
>> MAINTAINERS | 2 +-
>> 3 files changed, 106 insertions(+), 84 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.txt
>> create mode 100644 Documentation/devicetree/bindings/gpio/brcm,brcmstb-gpio.yaml
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1564132
>
>
> gpio@4172c0: interrupts-extended: [[6, 6], [7, 5]] is too long
> arch/arm/boot/dts/bcm7445-bcm97445svmb.dt.yaml
The property is correct AFAICT, we have:
interrupts-extended = <&irq0_aon_intc 0x6>,
<&aon_pm_l2_intc 0x5>;
with both interrupt controllers having #interrupt-cells = <1>. I tried
documenting the interrupts-extended for brcm,brcmstb-gpio.yaml to have
maxItems: 2 but that does not eliminate the warning. Do you have any
suggestions?
--
Florian
On 12/6/21 11:59 PM, Uwe Kleine-König wrote:
> Hello,
>
> On Mon, Dec 06, 2021 at 10:26:05AM -0800, Florian Fainelli wrote:
>> Convert the Broadcom STB BCM7038 PWM Device Tree binding to YAML to help
>> with validation.
>>
>> Signed-off-by: Florian Fainelli <[email protected]>
>
> Acked-by: Uwe Kleine-König <[email protected]>
>
> I assume you intend to take these patches all together via the bcm tree?
Yes, or having Rob pick them up, either way is fine.
--
Florian
On 12/7/21 6:58 AM, Rob Herring wrote:
> On Mon, 06 Dec 2021 10:26:11 -0800, Florian Fainelli wrote:
>> Convert the Broadcom STB L2 generic Level 2 interrupt controller Device
>> Tree binding to YAML to help with validation.
>>
>> Signed-off-by: Florian Fainelli <[email protected]>
>> ---
>> .../interrupt-controller/brcm,l2-intc.txt | 31 ---------
>> .../interrupt-controller/brcm,l2-intc.yaml | 64 +++++++++++++++++++
>> 2 files changed, 64 insertions(+), 31 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.txt
>> create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,l2-intc.yaml
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1564135
>
>
> interrupt-controller@3e1000: 'interrupt-names' does not match any of the regexes: 'pinctrl-[0-9]+'
> arch/arm/boot/dts/bcm7445-bcm97445svmb.dt.yaml
>
> interrupt-controller@7ef00100: compatible: 'oneOf' conditional failed, one must be fixed:
> arch/arm64/boot/dts/broadcom/bcm2711-rpi-400.dt.yaml
> arch/arm64/boot/dts/broadcom/bcm2711-rpi-4-b.dt.yaml
> arch/arm64/boot/dts/broadcom/bcm2711-rpi-cm4-io.dt.yaml
> arch/arm/boot/dts/bcm2711-rpi-400.dt.yaml
> arch/arm/boot/dts/bcm2711-rpi-4-b.dt.yaml
> arch/arm/boot/dts/bcm2711-rpi-cm4-io.dt.yaml
Both fixed in v3.
--
Florian
On 12/7/21 6:58 AM, Rob Herring wrote:
> On Mon, 06 Dec 2021 10:26:14 -0800, Florian Fainelli wrote:
>> Convert the Broadcom SATA3 AHCI controller Device Tree binding to YAML
>> to help with validation.
>>
>> Acked-by: Damien Le Moal <[email protected]>
>> Signed-off-by: Florian Fainelli <[email protected]>
>> ---
>> .../bindings/ata/brcm,sata-brcm.txt | 45 ---------
>> .../bindings/ata/brcm,sata-brcm.yaml | 91 +++++++++++++++++++
>> 2 files changed, 91 insertions(+), 45 deletions(-)
>> delete mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.txt
>> create mode 100644 Documentation/devicetree/bindings/ata/brcm,sata-brcm.yaml
>>
>
> Running 'make dtbs_check' with the schema in this patch gives the
> following warnings. Consider if they are expected or the schema is
> incorrect. These may not be new warnings.
>
> Note that it is not yet a requirement to have 0 warnings for dtbs_check.
> This will change in the future.
>
> Full log is available here: https://patchwork.ozlabs.org/patch/1564108
>
>
> ahci@41000: $nodename:0: 'ahci@41000' does not match '^sata(@.*)?$'
> arch/arm/boot/dts/bcm958522er.dt.yaml
> arch/arm/boot/dts/bcm958525er.dt.yaml
> arch/arm/boot/dts/bcm958525xmc.dt.yaml
> arch/arm/boot/dts/bcm958622hr.dt.yaml
> arch/arm/boot/dts/bcm958623hr.dt.yaml
> arch/arm/boot/dts/bcm958625hr.dt.yaml
> arch/arm/boot/dts/bcm958625k.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64w.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx65.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx65w.dt.yaml
> arch/arm/boot/dts/bcm988312hr.dt.yaml
>
> ahci@41000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'dma-coherent', 'sata-port@0', 'sata-port@1' were unexpected)
> arch/arm/boot/dts/bcm958522er.dt.yaml
> arch/arm/boot/dts/bcm958525er.dt.yaml
> arch/arm/boot/dts/bcm958525xmc.dt.yaml
> arch/arm/boot/dts/bcm958622hr.dt.yaml
> arch/arm/boot/dts/bcm958623hr.dt.yaml
> arch/arm/boot/dts/bcm958625hr.dt.yaml
> arch/arm/boot/dts/bcm958625k.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64w.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx65.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx65w.dt.yaml
> arch/arm/boot/dts/bcm988312hr.dt.yaml
>
> ahci@41000: Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'sata-port@0', 'sata-port@1' were unexpected)
> arch/arm/boot/dts/bcm958625-meraki-mx64-a0.dt.yaml
> arch/arm/boot/dts/bcm958625-meraki-mx64w-a0.dt.yaml
>
> sata@a000: compatible: 'oneOf' conditional failed, one must be fixed:
> arch/arm/boot/dts/bcm963138dvt.dt.yaml
All of those fixed in v3.
--
Florian
On Mon, 2021-12-06 at 10:26 -0800, Florian Fainelli wrote:
> Convert the Broadcom STB SW_INIT style reset controller binding to YAML.
>
> Signed-off-by: Florian Fainelli <[email protected]>
Acked-by: Philipp Zabel <[email protected]>
regards
Philipp